7805ALP MAXWELL | Alldatasheet
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All data sheets are subject to change without notice (858) 503-3300 Fax: (858) 503-3301- www.maxwell.com 16-Bit Latchup Protected ADC 7805ALP ©2005 Maxwell Technologies All rights reserved.
01.10.05 Rev 9
FEATURES:
- 16-bit organization Latchup Protection Technology™ AD-PAK® radiation-hardened against natural space radia- tion Total dose hardness: - > 50 krads(Si), depending upon space mission Latchup converted to reset. - Rate based on cross section and mission. Package: - 28 pin RAD-PAK® flat pack - 28 pin RAD-PAK® DIP 100 kHz min sampling rate Standard ± 10V input range Advance CMOS technology - 86 dB min SINAD with 20 kHz input - Single 5V supply operation - Utilizes internal or external reference - Full parallel data output - Power dissipation: 132 mW max DESCRIPTION: Maxwell Technologies’ 7805ALP high-speed analog-to-digital converter features a greater than 50 krad (Si) total dose toler- ance, depending upon space mission. Using Mawell’s radia- tion-hardened R AD-PAK® packaging technology, the 7805ALP incorporates the commercial ADS7805 from Burr Brown. This device is latchup protected by Maxwell Technologies’ LPT™ technology. The 7805ALP, 16-bit sampling CMOS A/D . The device contains a complete 16-bit capacitor-based SAR A/D with S/H, reference, clock, interface for microprocessor use, and three-state output drivers. The 7805ALP is specified at a 100 kHz sampling rate, and guaranteed over the full tempera- ture range. Laser-trimmed scaling resistors provide an indus- try-standard ± 10V input range, while the innovative design allows operation from a single 5V supply, with power dissipa- tion of under 132 mW. Maxwell Technologies' patented R AD-PAK® packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, R AD-PAK® provides greater than 50 krad (Si) radiation dose tolerance. This product is available with screening up to Maxwell Technologies self-defiened Class K. Logic Diagram
TABLE 1. 7805ALP PINOUT DESCRIPTION 2 AGND1 Analog ground. Used internally as ground reference point. 4 CAP Reference buffer capacitor. 2.2 µ F tantalum capacitor to ground. HIGH*, D15 must not be driven high. 7 D14 0 Data bit 14. When STATUS is HIGH*, D14 must not be driven high. 8 D13 0 Data bit 13. When STATUS is HIGH*, D13 must not be driven high. 9 D12 0 Data bit 12. When STATUS is HIGH*, D12 must not be driven high. 10 D11 0 Data bit 11. When STATUS is HIGH*, D11 must not be driven high. 11 D10 0 Data bit 10. When STATUS is HIGH*, D10 must not be driven high. 12 D9 0 Data bit 9. When STATUS is HIGH*, D9 must not be driven high. 13 D8 0 Data bit 8. When STATUS is HIGH*, D8 must not be driven high.
14 DGND Digital Ground
15 D7 0 Data bit 7. When STATUS is HIGH*, D7 must not be driven high. 16 D6 0 Data bit 6. When STATUS is HIGH*, D6 must not be driven high. 17 D5 0 Data bit 5. When STATUS is HIGH*, D5 must not be driven high. 18 D4 0 Data bit 4. When STATUS is HIGH*, D4 must not be driven high. 19 D3 0 Data bit 3. When STATUS is HIGH*, D3 must not be driven high. 20 D2 0 Data bit 2. When STATUS is HIGH*, D2 must not be driven high. 21 D1 0 Data bit 1. When STATUS is HIGH*, D1 must not be driven high. HIGH*, D0 must not be driven high.
23 STATUS* 0 STATUS when HIGH indicates latchup protection is active and output data is
invalid. Capacitive loading should not exceed 1000 pF.
24 R/C
IW i t h C S LOW and BUSY HIGH, a falling edge of R/C initiates a new conversion. When STATUS is HIGH*, CS and R/C must not be driven high. sion. When STATUS is HIGH*, CS and R/C must not be driven high.
26 BUSY 0 At the start of a conversion, BUSY goes LOW and stays LOW until the conversion
is completed and the digital outputs have been updated. 28 V S Supply input. Nominally 5V. Decouple to ground with 10 µ F tantalum capacitor.
TABLE 2. 7805ALP ABSOLUTE MAXIMUM RATINGS TABLE 3. 7805ALP DC ACCURACY SPECIFICATIONS
- Typical rms noise at worst case transitions and temperatures.
- Measured with various fixed resistors.
- Full scale error is worst case - Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions, di vided
by the transition voltage (not divided by the full-scale range) and included the effect of offset error. TABLE 4. 7805ALP DIGITAL INPUTS
TABLE 5. 7805ALP ANALOG INPUTS
- Tested by application of signal.
TABLE 6. 7805ALP THROUGHPUT SPEED TABLE 7. 7805ALP AC ACCURACY SPECIFICATIONS
- All specifications in dB are referred to a full-scale 10V input.
- Full-power bandwidth defined as full-scale input frequency at which signal-to-(noise + distortion) degrades to 60 dB or 10 bits of
TABLE 4. 7805ALP DIGITAL INPUTS
TABLE 8. 7805ALP SAMPLING DYNAMICS
- Recovers to specified performance after 2 x f S input overvoltage.
TABLE 9. 7805ALP REFERENCE TABLE 10. (VS = 5V, TA = -40 TO +85°C UNLESS OTHERWISE SPECIFIED)
- Tested by application of signal.
TABLE 11. 7805ALP DIGITAL OUTPUTS
TABLE 12. 7805ALP POWER SUPPLIES TABLE 13. 7805ALP DIGITAL TIMING TABLE 14. 7805ALP TEMPERATURE
- Tested by application of signal.
TABLE 15. 7805ALP CONVERSION TIMING1
- Tested by application of signal.
TABLE 16. 7805ALP CONTROL LINE FUNCTION FOR READ AND CONVERT 1 X X None. Databus is in Hi-Z state. " 0 1 Initiates conversion "n". Databus remains in Hi-Z state. 0 " 1 Initiates conversion "n". Databus enters Hi-Z state. 01 Conversion "n" completed. Valid data from conversion "n" on the databus. " 1 1 Enables databus with valid data from conversion "n". " 1 0 Enables databus with valid data from conversion "n-1". Conversion "n" in progress. 00 New conversion initiated without acquisition of a new signal. Data will be invalid. CS and/or R/C must be HIGH when BUSY goes HIGH. X X 0 New convert commands ignored. Conversion "n" in progress. TABLE 15. 7805ALP CONVERSION TIMING1
FIGURE 1. CONVERSION TIMING WITH OUTPUTS ENABLED AFTER CONVERSION (CS TIED LOW) FIGURE 2. USING CS TO CONTROL CONVERSION AND READ TIMING
cuitry consists of a protected device, the ADS7805 die, a current sensor, a power switch, and a status output driver. FIGURE 3. LATCHUP PROTECTION DIAGRAM protected device, it is critical that external circuitry driving the device I/O pins does not backdrive the device supply. Backdriving the supply could contribute to an extended or even a permanent latchup condition.
A summary of the pin differences between the ADS7805 and 7805A is provided below. tion circuit for connecting the 7805A to an 8-bit data bus. TABLE 16. PIN DIFFERENCES 23 BYTE STATUS A high level STATUS signal indicates that power is removed from the ADS7805 die. STATUS pin at customer request.
27 VANA DECPLNG The ADS7805 VANA and V
28 V DIG VS This is the power supply input for the LPT circuitry and the protected ADS7805 die. power switch circuitry is located between this pin and the DECPLNG pin.
FIGURE 4. TYPICAL 7805A APPLICATION CIRCUIT FIGURE 5. TYPICAL 7805A CIRCUIT WITH 16-BIT BUS INTERFACE
FIGURE 6. TYPICAL 7805A CIRCUIT WITH 8-BIT BUS INTERFACE is low, power is applied to the ADS7805 die. The STATUS signal can be used to measure the supply recovery time. The status signal can exhibit multiple transitions when power is re-applied and the decoupling capacitors are charged. event and power cycling effects on the reference circuits and the settling times of their respective filter capacitors. TABLE 17. LPT™ OPERATING CHARACTERISTICS
FIGURE 7. LPT™ TEST CIRCUIT TABLE 17. LPT™ OPERATING CHARACTERISTICS
FIGURE 9. SEU AND SEL CROSS SECTION
15All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP Note: All dimensions in inches
28 PIN RAD-PAK® FLAT PACKAGE
A 0.177 0.192 0.207 b 0.015 0.017 0.022 c 0.004 0.005 0.009 D -- 0.800 0.808 E 0.400 0.410 0.420 E1 -- -- 0.440 E2 0.295 0.300 -- E3 0.000 0.055 -- e 0.050 BSC L 0.390 0.400 0.410 Q 0.028 0.032 0.036 S1 0.000 0.067 -- N2 8
16All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP Note: All dimensions in inches 28-PIN RAD-PAK® DUAL IN LINE PACKAGE SYMBOL DIMENSION MIN NOM MAX A -- 0.185 0.225 b 0.014 0.018 0.026 b2 0.045 0.050 0.065 c 0.008 0.010 0.018 D -- 1.600 1.616 E 0.585 0.595 0.605 eA 0.600 BSC eA/2 0.300 BSC e 0.100 BSC L 0.165 0.175 0.185 Q 0.015 0.030 0.075 S1 0.005 0.125 -- S2 0.005 -- -- N2 8
17All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP Important Notice: These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
18All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. 16-Bit Latchup Protected ADC 7805ALP 1) Products are manufactured and screened to Maxwell Technologies self-defined Class H and Class K flows. Model Number Feature Option Details7805ALP RP X X Screening Flow Package Radiation Feature Base Product Nomenclature MCM1 K = Maxwell Self-Defined Class K H = Maxwell Self-Defined Class H I = Industrial (testing @ -40°C, +25°C, +85°C) E = Engineering (testing @ +25°C) D = Dual In-line Package (DIP) F = Flat Pack RP = RAD-PAK® package 16-Bit Latchup Protected ADC