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Technical content

Features

  • Supports both 1/3 duty 1/2 bias and 1/3 duty 1/3 bias LCD drive under serial data control. LC75833E, LC75833W: up to 105 segments LC75833JE: up to 93 segments (without the S12, S23, S24, S35 segment output pins from the LC75833E, LC75833W)
  • Serial data input supports CCB format communication with the system controller.
  • Serial data control of the power-saving mode based backup function and all the segments forced off function
  • Serial data control of switching between the segment output port and the general-purpose output port functions
  • High generality, since display data is displayed directly without decoder intervention.
  • Independent V LCD for the LCD driver block (VLCD can be set to any voltage in the range 2.7 to 6.0 volts, regardless of the logic block power-supply voltage.)
  • The INH pin can force the display to the off state.
  • RC oscillator circuit Package Dimensions unit: mm 3156-QFP48E unit: mm 3163A-SQFP48 unit: mm 3148-QFP44MA
  • CCB is a trademark of SANYO ELECTRIC CO., LTD.
  • CCB is SANYO’s original bus format and all the bus addresses are controlled by SANYO. [LC75833W] [LC75833E] SANYO: QFP48E [LC75833JE] SANYO: SQFP48 SANYO: QIP44MA

Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Note: The LC75833JE does not have the S12, S23, S24, S35 output pins. Allowable Operating Ranges at Ta = –40 to +85°C, VSS = 0 V No. 5580-2/19 LC75833E, 75833W, 75833JE Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max VDD –0.3 to +7.0 V VLCD max VLCD –0.3 to +7.0 V VIN 1 CE, CL, DI, INH –0.3 to +7.0 V Input voltage VIN 2 OSC –0.3 to VDD + 0.3 V VIN 3 VLCD 1, VLCD 2 –0.3 to VLCD + 0.3 V Output voltage VOUT 1 OSC –0.3 to VDD + 0.3 V VOUT 2 S1 to S35, COM1 to COM3, P1 to P8 –0.3 to VLCD + 0.3 V IOUT 1 S1 to S35 300 µA Output current IOUT 2 COM1 to COM3 3 mA IOUT 3 P1 to P8 5 mA Allowable power dissipation Pd max Ta = 85°C 150 mW Operating temperature Topr –40 to +85 °C Storage temperature Tstg –55 to +125 °C Parameter Symbol Conditions Ratings Unitmin typ max Supply voltage VDD VDD 2.7 6.0 V VLCD VLCD 2.7 6.0 V Input voltage VLCD 1 VLCD 1 2/3 VLCD VLCD V VLCD 2 VLCD 2 1/3 VLCD VLCD V Input high-level voltage VIH CE, CL, DI, INH 0.8 VDD 6.0 V Input low-level voltage VIL CE, CL, DI, INH 0 0.2 VDD V Recommended external resistance R OSC OSC 39 kΩ Recommended external capacitance C OSC OSC 1000 pF Guaranteed oscillation range fOSC OSC 19 38 76 kHz Data setup time tds CL, DI: Figure 2 160 ns Data hold time tdh CL, DI: Figure 2 160 ns CE wait time tcp CE, CL: Figure 2 160 ns CE setup time tcs CE, CL: Figure 2 160 ns CE hold time tch CE, CL: Figure 2 160 ns High-level clock pulse width tøH CL: Figure 2 160 ns Low-level clock pulse width tøL CL: Figure 2 160 ns Rise time tr CE, CL, DI: Figure 2 160 ns Fall time tf CE, CL, DI: Figure 2 160 ns INH switching time tc INH, CE: Figure 3 10 µs

No. 5580-3/19 LC75833E, 75833W, 75833JE Electrical Characteristics for the Allowable Operating Ranges Note: *1 Excluding the bias voltage generation divider resistors built in the VLCD 1 and VLCD 2. (See Figure 1.) The LC75833JE does not have the S12, S23, S24, S35 output pins. Parameter Symbol Conditions Ratings Unitmin typ max Hysteresis width VH CE, CL, DI, INH 0.1 VDD V Input high level current IIH CE, CL, DI, INH; VI= 6.0 V 5.0 µA Input low level current IIL CE, CL, DI, INH; VI= 0 V –5.0 µA VOH 1 S1 to S35; IO = –20 µA VLCD – 0.9 V Output high-level voltage VOH 2 COM1 to COM3; IO = –100 µA VLCD – 0.9 V VOH 3 P1 to P8; IO = –1 mA VLCD – 0.9 V VOL 1 S1 to S35; IO = 20 µA 0.9 V Output low-level voltage VOL 2 COM1 to COM3; IO = 100 µA 0.9 V VOL 3 P1 to P8; IO = 1 mA 0.9 V VMID 1 COM1 to COM3; 1/2 bias, 1/2 VLCD – 0.9 1/2 VLCD + 0.9 VIO = ±100 µA VMID 2 S1 to S35; 1/3 bias, 2/3 VLCD – 0.9 2/3 VLCD + 0.9 VIO = ±20 µA Output middle-level voltage*1 VMID 3 S1 to S35; 1/3 bias, 1/3 VLCD – 0.9 1/3 VLCD + 0.9 VIO = ±20 µA VMID 4 COM1 to COM3; 1/3 bias, 2/3 VLCD – 0.9 2/3 VLCD + 0.9 VIO = ±100 µA VMID 5 COM1 to COM3; 1/3 bias, 1/3 VLCD – 0.9 1/3 VLCD + 0.9 VIO = ±100 µA Oscillator frequency fOSC OSC; ROSC = 39 kΩ C OSC = 1000 pF 30.4 38 45.6 kHz IDD 1 VDD ; power saving mode 5 µA IDD 2 VDD ; VDD = 6.0 V, output open, fosc = 38 k Hz 250 500 µA ILCD 1 VLCD ; power saving mode 5 µA Current drain ILCD 2 VLCD ; VLCD = 6.0 V, output open 100 200 µA1/2 bias, fosc = 38 k Hz ILCD 3 VLCD ; VLCD = 6.0 V, output open 60 120 µA1/3 bias, fosc = 38 k Hz

Note: The LC75833JE does not have the S12, S23, S24, S35 output pins. No. 5580-5/19 LC75833E, 75833W, 75833JE COM2 37 COM3 VDD VLCD VLCD 1 VLCD 2 VSS OSC INH CE CL DI 48 S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S1313 P1/S1 1 12 P2/S2 P3/S3 P4/S4 P5/S5 P6/S6 P7/S7 P8/S8 S10 S11 S12 S25 2536 S26 S27 S28 S29 S30 S31 S32 S33 S34 S35 COM1 LC75833E LC75833W A06549 34COM3 VDD VLCD VLCD 1 VLCD 2 VSS OSC INH CE CL DI 44 S25 S22 S21 S20 S19 S18 S17 S16 S15 S14 S1312 P1/S1 1 11 P2/S2 P3/S3 P4/S4 P5/S5 P6/S6 P7/S7 P8/S8 S10 S11 2333 S26 S27 S28 S29 S30 S31 S32 S33 S34 COM1 COM2 LC75833JE A06582 Common driver Address detector Clock generator Segment driver & latch Shift register INH OSC VDD VLCD VLCD 1 VLCD 2 VSS DI CL CE COM3 COM2 COM1 S35 S34 S8/P8 S2/P2 S1/P1 A06553

Note: The LC75833JE does not have the S12, S23, S24, S35 output pins. No. 5580-6/19 LC75833E, 75833W, 75833JE CE: Chip enable CL: Synchronization clock DI: Transfer data H S1/P1 to S8/P8 S9 to S35 Pin 1 to 8 9 to 35 LC75833E, 75833W LC75833JE 1 to 8 9 to 31 — O Open Segment outputs for displaying the display data transferred by serial data input. The pins S1/P1 to S8/P8 can be used as general-purpose output ports when so set up by the control data. COM1 COM2 COM3 — O OpenCommon driver outputs. The frame frequency fO is given by: fO = (fOSC /384) Hz. OSC 44 40 CE CL DI Serial data transfer inputs. These pins are connected to the control microprocessor. — I/O VDD I GND Oscillator connection An oscillator circuit is formed by connecting an external resistor and capacitor to this pin. V LCD 1 41 37 — I Open Used to apply the LCD drive 2/3-bias voltage externally. This pin must be connected to VLCD 2 when 1/2-bias drive is used. VLCD 2 42 38 — I Open Used to apply the LCD drive 1/3-bias voltage externally. This pin must be connected to VLCD 1 when 1/2-bias drive is used. VDD 39 35 — — —Logic block power supply. Provide a voltage in the range 2.7 to 6.0 V. VLCD 40 36 — — —LCD driver block power supply. Provide a voltage in the range 2.7 to 6.0 V. VSS 43 39 — — —Ground pin. Connect to ground. INH 45 41 L I GND Display off control input

  • INH = low (VSS ): Off S1/P1 to S8/P8 = Low (These pins are forcibly set to the segment output port function and fixed at the V SS level.) S9 to S35 = Low (VSS ), COM1 to COM3 = Low (VSS )
  • INH = high (VDD ):On Note that serial data transfers can be performed when the display is forced off by this pin. Active I/O Handling when unusedFunctions Pin No.

Serial Data Transfer Format 1. When CL is stopped at the low level Note: DD ... Direction data No. 5580-7/19 LC75833E, 75833W, 75833JE D32D3D2D101000110 A3A2A1A0B3B2B1B0 D33 D34 D35 D36 0 0 0 P0 P1 P2 P3 DR SC BU 0 0 CCB address 8 bits Display data 36 bits Control data 10 bits DD 2 bits CE CL DI D68D39D38D3701000110 A3A2A1A0B3B2B1B0 D69 D70 D71 D72 0 0 0 0 0 0 0 0 0 0 0 1 CCB address 8 bits Display data 36 bits Fixed data 10 bits DD 2 bits D104D75D74D7301000110 A3A2A1A0B3B2B1B0 D105 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CCB address 8 bits Display data 33 bits Fixed data 13 bits DD 2 bits A06554

  1. When CL is stopped at the high level Note: DD ... Direction data must be set to 0. No. 5580-8/19 LC75833E, 75833W, 75833JE D32D3D2D101000110 A3A2A1A0B3B2B1B0 D33 D34 D35 D36 0 0 0 P0 P1 P2 P3 DR SC BU 0 0 CCB address 8 bits Display data 36 bits Control data 10 bits DD 2 bits CE CL DI D68D39D38D3701000110 A3A2A1A0B3B2B1B0 D69 D70 D71 D72 0 0 0 0 0 0 0 0 0 0 0 1 CCB address 8 bits Display data 36 bits Fixed data 10 bits DD 2 bits D104D75D74D7301000110 A3A2A1A0B3B2B1B0 D105 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 CCB address 8 bits Display data 33 bits Fixed data 13 bits DD 2 bits A06555

Serial Data Transfer Examples

  • At the LC75833E and LC75833W when 73 or more segments are used, at the LC75833JE when 64 or more segments are used. 144 bits of serial data must be sent. Note: At the LC75833JE, the display data D34 to D36, D67 to D72, D103 to D105 must be set to 0.
  • At the LC75833E and LC75833W when used with less than 73 segments, at the LC75833JE when used with less than 64 segments. Transfer either 48 bits or 96 bits of serial data depending on the number of segments used. However, the serial data shown in the figure below (the display data D1 to D36 and the control data) must be sent. Note: At the LC75833JE, the display data D34 to D36 must be set to 0. Control Data Functions 1. P0 to P3: Segment output port/general-purpose output port switching control data. These control data bits switch the S1/P1 to S8/P8 output pins between their segment output port and general-purpose output port functions. Note: Sn (n = 1 to 8): Segment output ports Pn (n = 1 to 8): General-purpose output ports No. 5580-9/19 LC75833E, 75833W, 75833JE Control data Output pin states P0 P1 P2 P3 S1/P1 S2/P2 S3/P3 S4/P4 S5/P5 S6/P6 S7/P7 S8/P8 0 0 0 0 S1 S2 S3 S4 S5 S6 S7 S8 0 0 0 1 P1 S2 S3 S4 S5 S6 S7 S8 0 0 1 0 P1 P2 S3 S4 S5 S6 S7 S8 0 0 1 1 P1 P2 P3 S4 S5 S6 S7 S8 0 1 0 0 P1 P2 P3 P4 S5 S6 S7 S8 0 1 0 1 P1 P2 P3 P4 P5 S6 S7 S8 0 1 1 0 P1 P2 P3 P4 P5 P6 S7 S8 0 1 1 1 P1 P2 P3 P4 P5 P6 P7 S8 1 0 0 0 P1 P2 P3 P4 P5 P6 P7 P8 D1 D2 D3 D31 D32 D330 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D34 D35 D36 0 0 0 P0 P1 P2 P3 DR SC BU 0 0 8 bits 48 bits D37 D38 D39 D67 D68 D690 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D70 D71 D72 0 0 0 0 0 0 0 0 0 0 0 1 D73 D74 D75 D103 D104 D1050 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 A06556 D1 D2 D3 D31 D32 D330 1 1 0 0 0 1 0 B0 B1 B2 B3 A0 A1 A2 A3 D34 D35 D36 0 0 0 P0 P1 P2 P3 DR SC BU 0 0 8 bits 48 bits A06557

Also note that when the general-purpose output port function is selected, the output pins and the display data will have the correspondences listed in the tables below. For example, if the output pin S4/P4 has the general-purpose output port function selected, it will output a high level (VLCD ) when the display data D10 is 1, and will output a low level (VSS) when D10 is 0. 2. DR: 1/2-bias drive or 1/3-bias drive switching control data This control data bit selects either 1/2-bias drive or 1/3-bias drive. 3. SC: Segments on/off control data This control data bit controls the on/off state of the segments. However, note that when the segments are turned off by setting SC to 1, the segments are turned off by outputting segment off waveforms from the segment output pins. 4. BU: Normal mode/power-saving mode control data This control data bit selects either normal mode or power-saving mode. No. 5580-10/19 LC75833E, 75833W, 75833JE DR Drive type 0 1/3-bias drive 1 1/2-bias drive SC Display state 0 On

1 Off

0 Normal mode

Power saving mode (The OSC pin oscillator is stopped, and the common and segment output pins go to the VSS level. However, the 1 S1/P1 to S8/P8 output pins that are set to be general-purpose output ports by the control data P0 to P3 can be used as general- purpose output ports.) Output pin Corresponding display data S1/P1 D1 S2/P2 D4 S3/P3 D7 S4/P4 D10 Output pin Corresponding display data S5/P5 D13 S6/P6 D16 S7/P7 D19 S8/P8 D22

Display Data to Segment Output Pin Correspondence Note: This applies to the case where the S1/P1 to S8/P8 output pins are set to be segment output ports. The LC75833JE do not have the S12, S23, S24, S35 output pins. For example, the table below lists the segment output states for the S11 output pin. No. 5580-11/19 LC75833E, 75833W, 75833JE Segment COM1 COM2 COM3output pin S1/P1 D1 D2 D3 S2/P2 D4 D5 D6 S3/P3 D7 D8 D9 S4/P4 D10 D11 D12 S5/P5 D13 D14 D15 S6/P6 D16 D17 D18 S7/P7 D19 D20 D21 S8/P8 D22 D23 D24 S9 D25 D26 D27 S10 D28 D29 D30 S11 D31 D32 D33 S12 D34 D35 D36 S13 D37 D38 D39 S14 D40 D41 D42 S15 D43 D44 D45 S16 D46 D47 D48 S17 D49 D50 D51 S18 D52 D53 D54 Segment COM1 COM2 COM3output pin S19 D55 D56 D57 S20 D58 D59 D60 S21 D61 D62 D63 S22 D64 D65 D66 S23 D67 D68 D69 S24 D70 D71 D72 S25 D73 D74 D75 S26 D76 D77 D78 S27 D79 D80 D81 S28 D82 D83 D84 S29 D85 D86 D87 S30 D88 D89 D90 S31 D91 D92 D93 S32 D94 D95 D96 S33 D97 D98 D99 S34 D100 D101 D102 S35 D103 D104 D105 Display data Segment output pin (S11) state D31 D32 D33 0 0 0 The LCD segments corresponding to COM1 to COM3 are off. 0 0 1 The LCD segments corresponding to COM3 is on. 0 1 0 The LCD segments corresponding to COM2 is on. 0 1 1 The LCD segments corresponding to COM2 and COM3 are on. 1 0 0 The LCD segments corresponding to COM1 is on. 1 0 1 The LCD segments corresponding to COM1 and COM3 are on. 1 1 0 The LCD segments corresponding to COM1 and COM2 are on. 1 1 1 The LCD segments corresponding to COM1 to COM3 are on.

1/3-Duty 1/2-Bias Drive Technique No. 5580-12/19 LC75833E, 75833W, 75833JE 1/3-Duty 1/2-Bias Waveforms fosc 384 [Hz] COM1 VLCD VLCD1 , VLCD2 0 V VLCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V V LCD VLCD1 , VLCD2 0 V COM2 COM3 A06558 LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on (lit). LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on.

384 [Hz] COM1 VLCD VLCD1 VLCD2 0 V VLCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V V LCD VLCD1 VLCD2 0 V COM2 COM3 1/3-Duty 1/3-Bias Technique No. 5580-13/19 LC75833E, 75833W, 75833JE LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are turned off. LCD driver output when only LCD segments corresponding to COM1 are on (lit). LCD driver output when only LCD segments corresponding to COM2 are on. LCD driver output when LCD segments corresponding to COM1 and COM2 are on. LCD driver output when only LCD segments corresponding to COM3 are on. LCD driver output when LCD segments corresponding to COM1 and COM3 are on. LCD driver output when LCD segments corresponding to COM2 and COM3 are on. LCD driver output when all LCD segments corresponding to COM1, COM2, and COM3 are on. 1/3-Duty 1/3-Bias Waveforms A06559

The INH pin and Display Control Since the LSI internal data (the display data and the control data) is undefined when power is first applied, applications should set the INH pin low at the same time as power is applied to turn off the display (LC75833E, LC75833W: This sets the S1/P1 to S8/P8, S9 to S35, and COM1 to COM3 to the VSS level. LC75833JE: This sets the S1/P1 to S8/P8, S9 to S11, S13 to S22, S25 to S34, and COM1 to COM3 to the VSS level.) and during this period send serial data from the controller. The controller should then set the INH pin high after the data transfer has completed. This procedure prevents meaningless displays at power on. (See Figure 3.) Notes on the Power On/Off Sequences on and off.

  • At power on: Logic block power supply (VDD ) on fi LCD driver block power supply (VLCD ) on
  • At power off: LCD driver block power supply (VLCD ) off fi Logic block power supply (VDD ) off However, if the logic and LCD driver block use a shared power supply, then the power supplies can be turned on and off at the same time. Figure 3 Notes on Controller Transfer of Display Data Since the LC75833E, LC75833W, and LC75833JE accept display data divided into three separate transfer operations, we recommend that applications transfer all of the display data within a period of less than 30 ms to prevent observable degradation of display quality. No. 5580-14/19 LC75833E, 75833W, 75833JE VDD VLCD INH CE D1 to D36 P0 to P3Internal data Internal data Internal data DR, SC, BU (D37 to D72) (D73 to D105) t 1 t 2 t 3 VIL tc VIL Display and control data transfer Undefined Undefined Undefined Defined Defined Defined Undefined Undefined Undefined A 06560 Note: At the LC75833JE, the display data D34 to D36, D67 to D72, D103 to D105 must be set to 0. Note: t1 ‡ 0 t2 > 0 t3 ‡ 0 (t2 > t3) tc ... 10 µs min

Sample Application Circuit 1 1/2 Bias (for use with normal size panels)

  • LC75833E, LC75833W Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF.
  • LC75833JE Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 5580-15/19 LC75833E, 75833W, 75833JE VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S33 S34 S35 +3 V +5 V C ‡ 0.047 µF From the controller OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control A 06561 LCD panel (up to 105 segments) C VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S10 S11 S13 S22 S25 S34 +3 V +5 V From the controller OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control LCD panel (up to 93 segments) A 06583 C ‡ 0.047 µF C

Sample Application Circuit 2 1/2 Bias (for use with large panels)

  • LC75833E, LC75833W Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF.
  • LC75833JE Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 5580-16/19 LC75833E, 75833W, 75833JE VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S33 S34 S35 +3 V +5 V From the controller OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control A 06562 LCD panel (up to 105 segments) C ‡ 0.047 µF 10kΩ ‡ R ‡ 1kΩ C R R VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S10 S11 S13 S22 S25 S34 OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control A 06584 +3 V +5 V From the controller LCD panel (up to 93 segments) C ‡ 0.047 µF 10kΩ ‡ R ‡ 1kΩ C R R

Sample Application Circuit 3 1/3 Bias (for use with normal size panels)

  • LC75833E, LC75833W Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF.
  • LC75833JE Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 4801-17/19 LC75833E, 75833W, 75833JE VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S33 S34 S35 +3 V +5 V C ‡ 0.047 µF From the controller OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control A 06562 CC LCD panel (up to 105 segments) VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S10 S11 S13 S22 S25 S34 OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control A 06584 +3 V +5 V C ‡ 0.047 µF From the controller CC LCD panel (up to 93 segments)

Sample Application Circuit 4 1/3 Bias (for use with large panels)

  • LC75833E, LC75833W Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. No. 5580-18/19 LC75833E, 75833W, 75833JE VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S33 S34 S35 OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control A 06563 LCD panel (up to 105 segments) +3 V +5 V From the controller C ‡ 0.047 µF 10 kΩ ‡ R ‡ 1 kΩ C C R R R

PS No. 5580-19/19 LC75833E, 75833W, 75833JE

  • LC75833JE Note: *2 When a capacitor except the recommended external capacitance (COSC = 1000 pF) is connected the OSC pin, we recommend that applications connect the OSC pin with a capacitor in the range 220 to 2200pF. This catalog provides information as of March 1998. Specifications and information herein are subject to change without notice. n No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. n Anyone purchasing any products described or contained herein for an above-mentioned use shall: ‹ Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: \` Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. n Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. VDD VSS VLCD VLCD1 VLCD2 INH CE CL DI COM1 COM2 COM3 P1/S1 P2/S2 P8/S8 S10 S11 S13 S22 S25 S34 +3 V +5 V From the controller OSC (P1) (P2) (P8) General-purpose output ports Used for functions such as backlight control LCD panel (up to 93 segments) A 06585 C ‡ 0.047 µF 10 kΩ ‡ R ‡ 1 kΩ C C R R R