7554A

UPD7554A RENESAS | Alldatasheet

Document overview

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Technical content

Datasheet sections

• 1.1 PORT FUNCTIONS
• 1.2 OTHER THAN PORTS
• 1.3 PIN MASK OPTION
• 1.4 CAUTION ON USE OF P00/INT0 PIN AND RESET PIN
• 1.5 PIN INPUT/OUTPUT CIRCUITS
• 1.6 RECOMMENDED CONNECTION OF UNUSED µPD7554A PINS
• 1.7 OPERATION OF INPUT/OUTPUT PORTS
• 2.1 PROGRAM COUNTER (PC): 10 BITS
• 2.2 STACK POINTER (SP): 6 BITS
• 2.3 PROGRAM MEMORY (ROM): 1024 WORDS × 8 BITS
• 2.4 GENERAL REGISTER
• 2.5 DATA MEMORY (RAM): 64 × 4 BITS
• 2.6 ACCUMULATOR (A): 4 BITS
• 2.7 ARITHMETIC LOGIC UNIT (ALU): 4 BITS
• 2.8 PROGRAM STATUS WORD (PSW): 4 BITS
• 2.9 SYSTEM CLOCK GENERATOR
• 2.10 CLOCK CONTROL CIRCUIT
• 2.11 TIMER/EVENT COUNTER
• 2.12 SERIAL INTERFACE
• 2.13 TEST CONTROL CIRCUIT
• 3.1 STOP MODE
• 3.2 HALT MODE
• 3.3 CANCELLING THE STANDBY MODE

To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.com April 1st, 2010 Renesas Electronics Corporation Issued by: Renesas Electronics Corporation (http://www.renesas.com) Send any inquiries to http://www.renesas.com/inquiry.

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DESCRIPTION

The µPD7554A is a product of the µPD7554, 7564 sub-series which is a 4-bit single-chip microcomputer with a small number of ports in a small package, which is enabled to operate even at the super-low voltage of 2.0 V so that it is optimized for handy-type systems operating with dry cells. The µPD7554A is a low-order model in the µPD7500 series ( µPD7554A only). This device incorporates a serial interface, and serves as the sub-CPU for a high-order model of that series or the 8-bit microcomputer. It is optimized for distributed processing of the system. The µPD7554A has outputs to directly drive a triac and LEDs and allows selection among many types of input/ output circuits using their respective mask options, sharply reducing the number of external circuits required. Details of functions are described in the User’s Manual shown below. Be sure to read in design. µPD7554, 7564 User’s Manual: IEM-1111D 4-BIT SINGLE-CHIP MICROCOMPUTER µPD7554A, 7554A(A) MOS INTEGRATED CIRCUIT DATA SHEET The mark H shows major revised points. The information in this document is subject to change without notice.

FEATURES

• Range of supply voltage 7554A : 2.0 to 6.0 V 7554A(A) : 2.7 to 6.0 V
• Drive with two 1.5 V manganese cells
• 47 types of instructions (Subset of µPD7500H SET B)
• Instruction cycle External clock : 2.86 µs (in operation at 700 kHz, 5 V) RC oscillation : 4 µs (in operation at 500 kHz, 5 V)
• Program memory (ROM) capacity: 1024 × 8 bits
• Data memory (RAM) capacity: 64 × 4 bits
• Test source: One external source and two internal sources Document No. IC-2419C (O. D. No. IC-7835C) Date Published January 1995 P Printed in Japan © 19941989 APPLICATION µPD7554A : Sub-CPU including handy-type system, PPC, printer, VCR, audio equipments, etc. µPD7554A(A) : Automotive and transportation equipments, etc. H The quality level and absolute maximum ratings of the µPD7554A and the µPD7554A(A) differ. Except where specifically noted, explanations here concern the µPD7554A as a representative product. If you are using the µPD7554A(A), use the information presented here after checking the functional differences.
• 8-bit timer/event counter
• 16 I/O lines (Total output current of all pins: 100 mA)
• Can directly drive a triac and a LED: P80 to P83
• Can directly drive LEDs: P100 to P103 and P110 to P113
• Mask option function provided for every port
• 8-bit serial interface
• Standby (STOP/HALT) function
• Low supply voltage data retaining function for data memory
• Built-in ceramic oscillator for system clock RC Oscillation with an external resistor R (Incorporat- ing capacitor C) H

µPD7554A, 7554A(A)

ORDERING INFORMATION

Ordering Code Package Quality Grade µPD7554ACS-××× 20-pin plastic shrink DIP (300 mil) Standard µPD7554AG-××× 20-pin plastic SOP (300 mil) Standard µPD7554ACS(A)- ××× 20-pin plastic shrink DIP (300 mil) Special µPD7554AG(A)- ××× 20-pin plastic SOP (300 mil) Special Caution Be sure to specify a mask option when ordering this device. Remarks "××× " is a ROM code number. Please rfer to “Quality grade on NEC Semiconductor Devices” (Document number IEI-1209) published by NEC Corporation to know the specification of quality grade on the devices and its recommended applications. H H PIN CONFIGURATION (TOP VIEW) VSS P113 P112 P111 P110 P103 P102 P101 P100 RESET P00/INT0 P01/SCK P02/SO P03/SI P80 P81 P82 CL2(P83) CL1 VDD PD7554Aµ

µPD7554A, 7554A(A) BLOCK DIAGRAM OF µPD7554A RESETVDD VSS INSTRUCTION DECODER STANDBY CONTROL SYSTEM CLOCK GENERATOR PROGRAM MEMORY 1024 × 8 BITS PROGRAM COUNTER (10) P00/INT0 CL CLOCK CONTROL TIMER/EVENT COUNTER TEST CONTROL SERIAL INTERFACE PORT0 BUFFER PORT8 LATCH BUFFER PORT10 LATCH BUFFER PORT11 LATCH BUFFER

4 P00–P03

3 P80–P82

P83 (CL2)

4 P100–P103

4 P110–P113

A (4)C H (2) L (2) STACK POINTER (6) DATA MEMORY 64 × 4 BITS ALU INT0 P01/SCK P03/SI P02/SO φCL CL1 CL2(P83) CP GENERAL REGISTERS

µPD7554A, 7554A(A)

µPD7554A, 7554A(A) 1. PIN FUNCTIONS

1.1 PORT FUNCTIONS

Pin Name Input/Output Dual-Function Function After RESET Input/Output Pin Circuit P00 Input INT0 S P01 Input/output SCK Input X P02 SO W P03 Input SI S P80 to P82 Output –– O P83 Note Output CL2 P100 to P103 Input/output –– P P110 to P113 Input/output –– Note Mask options are available to specify port functions only when the external clock (CL1) is used.

1.2 OTHER THAN PORTS

Pin Name Input/Output Dual-Function Function After RESET Input/Output Pin Circuit INT0 Input P00 Edge detection testable input pin (Rising edge) S SCK Input/output P01 Serial clock Input/output pin Input X SO Output P02 Serial data output pin Input W SI Input P03 Serial data input pin Input S CL1 Q CL2 P83 RESET R VDD Positive power supply pin VSS GND potential pin 4-bit input port (Port 0) P00 serves also as a count clock (event pulse) input. 4-bit output port (Port 8) High current (15 mA), middle-high voltage (9 V) output 4-bit I/O port (Port 10) Middle-high current (10 mA), middle-high voltage (9 V) input/output 4-bit I/O port (Port 11) Middle-high current (10 mA), middle-high voltage (9 V) input/output High impedance High impedance or high-level output Connection pin for resistor R for RC oscillator When an external clock is used, its input must be connected to CL1, and CL2 can be used as P83 using the mask option. System reset input pin (high-level active) A pull-down resistor can be incorporated using the mask option.

µPD7554A, 7554A(A)

1.3 PIN MASK OPTION

Each pin is provided with the following mask options which can be selected for each bit according to the purpose: Pin Name Mask Options P00 À No internally provided resistor \ Pull-down resistor internally provided ´ Pull-up resistor internally provided P01 À No internally provided resistor \ Pull-down resistor internally provided ´ Pull-up resistor internally provided P02 À No internally provided resistor \ Pull-down resistor internally provided ´ Pull-up resistor internally provided P03 À No internally provided resistor \ Pull-down resistor internally provided ´ Pull-up resistor internally provided P80 À N-channel open-drain output \ CMOS (push-pull) output P81 À N-channel open-drain output \ CMOS (push-pull) output P82 À N-channel open-drain output \ CMOS (push-pull) output P83/CL2 À Used as CL2 or P83N-ch open-drain output pin. \ Used as P83 pin (push-pull output). P100 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided P101 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided P102 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided P103 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided P110 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided P111 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided P112 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided P113 À N-channel open-drain I/O \ Push-pull I/O ´ N-channel open-drain + I/O with pull-up resistor internally provided System clock Note À RC oscillation \ External clock RESET À Pull-down resistor is not internally provided \ Pull-down resistor is internally provided Note When using RC oscillation, switch the P83/CL2 pin to the CL2 pin. There is no mask option for PROM products. For more information, see the µPD75P54 Data Sheet (IC-2830). H

µPD7554A, 7554A(A)

1.4 CAUTION ON USE OF P00/INT0 PIN AND RESET PIN

In addition to the functions shown in 1.1, 1.2 and 1.3, the P00/INT0 pin and RESET pin have a function for setting the test mode in which the internal operation of the µPD7554A is tested (IC test only). When a potential greater than V SS is applied to either of these pins, the test mode is set. As a result, if noise exceeding V SS is applied during normal operation, the test mode will be entered and normal operation may be impeded. If, for example, the routing of the wiring between the P00/INT0 pin and RESET pin is long, the above problem may occur as the result of inter-wiring noise between these pins. Therefore, wiring should be carried out so as to suppress inter-wiring noise as far as possible. If it is not possible to suppress noise, anti-noise measures should be taken using external parts as shown in the figures below.

• Connection of diode with small V F between P00/ INT4/RESET pin and V SS
• Connection of capacitor between P00/INT0/ RESET pin and V SS VDD VDD P00/INT0, RESET VSS VDD VDD P00/INT0, RESET VSS Diode with Small V F

µPD7554A, 7554A(A)

1.5 PIN INPUT/OUTPUT CIRCUITS

This section presents the input/output circuit for each pin of the µPD7554A in a partly simplified format: (1) Type A (for Type W) VDD P–ch N–ch IN Forming an input buffer conformable to the CMOS specification (2) Type D (for Types W and X) VDD P–ch N–ch OUT data output disable Forming a push-pull output which becomes high impedance (with both P-ch and N-ch off) in response to RESET input

µPD7554A, 7554A(A) (3) Type O VDD P–ch N–ch OUT data output disable Mask Option (Middle-High Voltage, High-Current) (4) Type P VDD P–ch N–ch OUT data output disable Mask Option (Middle-High Voltage, High-Current) Middle-High Input Buffer (5) Type Q CL1 CL2/P83 Type 0 RC Oscillator Mask Option

µPD7554A, 7554A(A) (6) Type R Mask Option (7) Type S IN Mask Option VDD (8) Type W IN/OUT VDD Type D Type A data output disable Mask Option

µPD7554A, 7554A(A) (9) Type X IN/OUT VDD Type D data output disable Mask Option

1.6 RECOMMENDED CONNECTION OF UNUSED µPD7554A PINS

Pin Recommended Connection P00/INT0 Connect to V SS. P01 to P03 Connect to V SS or VDD. P80 to P82 Leave open. P100 to P103 P110 to P113 Input state : Connect to V SS or VDD. Output state: Leave open.

µPD7554A, 7554A(A)

1.7 OPERATION OF INPUT/OUTPUT PORTS

(1) P00 to P03 (Port 0) The port 0 is a 4-bit input port consisting of 4-bit input pins P00 to P03. In addition to being used for port input, P00 serves as a count clock input or testable input (INT0), each of P01 to P03 serves as a serial interface input/output. To use P00 as a count clock input, set bits 2 (CM2) and 1 (CM1) of the clock mode register to 01. (See 2.10 “CLOCK CONTROL CIRCUIT” for details.) To use P00 as a INT0, set bit 3 (SM3) of the shift mode register to 1. The serial interface function to use P01 to P03 as a serial interface I/O port is determined by bits 2 and 1 (SM2 and SM1) of the shift mode register. See 2.12 “SERIAL INTERFACE” for details. Even though this port operates using any function other than the port function, execution of the port input instruction (IPL) permits loading data on the P00 to P03 line to the accumulator (A0 to A3) at any time. (2) P80 to P83 (Port 8) The port 8 is a 4-bit output port with an output latch, which consists of 4-bit output pin. The port output instruction (OPL) latches the content of the accumulator (A0 to A3) to the output latch and outputs it to pins P80 to P83. The SPBL and RPBL instructions Note allow bit-by-bit setting and resetting of pins P80 to P83. Note that P83 is to be selected using a mask option, to serve as one of the connection pins of the resistor R for RC oscillation (CL2) or as the bit 3 output of the port 8. Thus, the port 8 is a 3-bit output port (P80 to p82) if RC oscillation is performed, and provides a 4-bit output (P80 to P83) only when an external clock is used. For these ports, mask options for the output format are available to select CMOS (push-pull) output or N-ch open- drain output. The port specified as a N-ch open-drain output and provides an efficient interface to the circuit operating at a different supply voltage because the output buffer has a dielectric strength of 9 V. Contents of the output latch become undefined when the RESET signal is input, then the output becomes high impedance. Note RPBL and SPBL are bit-by-bit setting and resetting instructions. During setting and resetting operations, the RPBL and SPBL instructionrs allow outputting with each (4-bit) port which contains the specified bits. (The content of the output latch is output to any pin other than the specified pins.) The content of the output latch must be initialized with the OPL instruction before executing the RPBL and SPBL instructions.

µPD7554A, 7554A(A) (3) P100 to P103 (Port 10) and P110-P113 (Port 11): Quasi-bidirectional input/output P100 to P103 are 4-bit I/O pins which form the port 10 (4-bit I/O port with an output latch). P110 to P113 are 4- bit I/O pins which form the port 11 (4-bit I/O port with an output latch). The port output instruction (OPL) latches the content of the accumulator to the output latch and outputs it to the 4-bit pins. The data written once in the output latch and the output buffer state are retained until the output instruction to operate the port 10 or 11 is executed or the RESET signal is input. Even though an input instruction is executed for the port 10 or 11, the states of both the output latch and output buffer do not change. The SPBL and RPBL instructions allow bit-by-bit setting and resetting of pins P100 to P103 and P110 to P113. The input/output format of each of the ports 10 and 11 can be selected from among the N-ch open-drain input/ output, N-ch open-drain + pull-up resistor built-in input/output, and CMOS (push-pull) input/output by their respective mask options. The ports 10 and 11 offers the middle withstand voltage of 9 V for the N-ch open-drain input/output, so that they are convenient for interface between circuits which has different supply voltages. When the CMOS (push-pull) input/output is selected, the port cannot return to the input mode once the output instruction is executed. However, the states of the pins of the port can be checked by reading via the port input instruction (IPL). When one of the other two formats is selected, the port can enter the input mode to load the data on the 4-bit line to the accumulator (as a quasi-bidirectional port) when the port receives high level output. Select each type of the input/output format to meet the use of the port: ➀ CMOS input/output i) Uses all 4 bits of the port as input ports. ii) Uses pins of the port as output pins not requiring middle withstand voltage output. ➁ N-ch open-drain input/output i) Uses pins of the port as I/O pins requiring a middle withstand voltage dielectric strength. ii) Uses input pins of the port which also has output pins. iii) Uses each pin of the port for both input and output by switching them over. ➂ N-ch open-drain + pull-up resistor built-in input/output i) Uses input pins of the port which also has output pins, that require a pull-up resistor. ii) Uses each pin of the port for both input and output by switching them over. This requires a pull-up resistor. Caution Before using input pins in the case of ➁ or ➂ , write 1 in the output latch to turn the N-ch transistor off. The content of the output latch becomes undefined when the RESET signal is input. In such a case, the output becomes high level with the N-ch open-drain + pull-up resistor built-in, and becomes high impedance without the resistor.

µPD7554A, 7554A(A) 2. INTERNAL BLOCK FUNCTIONS

2.1 PROGRAM COUNTER (PC): 10 BITS

The program counter is a 10-bit binaryc ounter to retain program memory (ROM) address information. Fig. 2-1 Program Counter Configuration PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 PC When one instruction is executed, usually the program counter is incremented by the number of bytes of the instruction. When the call instruction is executed, the PC is loaded with a nkew call address after the stack memory saves the current contents (return address) of the PC. When the return instruction is executed, the content (return address) of the stack memory is loaded onto the PC. When the jump instruction is executed, the immediate data identifying the destination of the jump is loaded to all or some of bits of the PC. When a skip occurs, the PC is incremented by 2 or 3 during the machine cycle depending on the number of bytes in the next instruction. When the RESET signal is input, all the bits of the PC are cleared to zero.

µPD7554A, 7554A(A)

2.2 STACK POINTER (SP): 6 BITS

The stack pointer is a 6-bit register which retains head address information of the stack memory (LIFO type) which is a part of the data memory. Fig. 2-2 Stack Pointer Configuration SP5 SP4 SP3 SP2 SP1 SP0 SP The stack pointer is decremented when the call instruction is executed. It is incremented when the return instruction is executed. To determine the stack area, initialize the SP using the TAMSP instruction. Note that bit SP0 is loaded with 0 unconditionally when the TAMSP instruction is executed. Set the SP to the value of “the highest address of the stack area + 1” because the stack operation starts with decrementation of the SP. When the highest address of the stack area is 3FH which is the highest address of the data memory, the initial value of SP5-0 must be 00H. For emulation using the µPD7500H (EVAKIT-7500B), set the data to be used for AM when executing the TAMSP instruction. Fig. 2-3 In Execution of TAMSP Instruction A3 A2 A1 A0 (HL) 3 (HL)2 (HL)1 (HL)0 SP5 SP4 SP3 SP2 SP1 SP0 Note that the contents of the SP cannot be read. Caution Be sure to set the SP at the initial stage of the program execution because the SP becomes undefined when the RESET signal is input. Example LHLI 00H LAI 0 ST LAI 4 TAMSP ;SP = 40H

µPD7554A, 7554A(A)

2.3 PROGRAM MEMORY (ROM): 1024 WORDS × 8BITS

The program memory is a mask programmable ROM of 1024 word × 8 bits configuration. It is addressed by the program counter. The program memory stores programs. Address 000H is the reset start address. Fig. 2-4 Program Memory Map (0) 000H (1023) 3FFH Reset Start

2.4 GENERAL REGISTER

General registers H (with two bits) and L (with four bits) operate individually. They also form a pair register HL (H: high order and L: low order) to serve as a data pointer for addressing the data memory. Fig. 2-5 General Register Configuration HL The L register is also used to specify I/O ports and the mode register when an input/output instruction (IPL or OPL) is executed. It also used to specify the bits of a port when the SPBL or RPBL instruction is executed.

µPD7554A, 7554A(A)

2.5 DATA MEMORY (RAM): 64 × 4 BITS

The data memory is a static RAM of 64 word × 4 bits configuration. It is used as the area to store or stack processed data. The data memory may be processed in 8-bit units when paired with the accumulator. Fig. 2-6 Data Memory Map ( 0 ) 00H (63) 3FH

64 Words × 4 Bits

The data memory is addressed in the following three ways:

• Direct: Direct addressing based on immediate data of an instruction
• Register indirect: Indirect addressing according to the contents of the pair register HL (including automatic incrementation and decrementation)
• Stack: Indirect addressing according to the contents of the stack pointer (SP) An arbitrary space of the data memory is available as stack memory. The boundary of the stack area is specified when the TAMSP instruction initializes the SP. After that, the stack area is accessed automatically by the call or return instruction. After the call instruction is executed, the content of the PC and PSW is stored in the order shown in the following diagram: 0 0 PC9 PC8 PSWNote PC3 – PC0 PC7 – PC4 SP – 4 SP – 3 SP – 2 SP – 1 Stack Area Note Bit 1 is fixed at 0. When the return instruction is executed, the content of the PSW is not restored while those of the PC are restored. Data in the data memory is retained at a low supply voltage in the STOP mode.

µPD7554A, 7554A(A)

2.6 ACCUMULATOR (A): 4 BITS

The accumulator is a 4-bit register which plays a major role in many types of arithmetic operations. The accumulator may be processed in 8-bit units when paired with the data memory addressed by the pair register HL. Fig. 2-7 Accumulator Configuration A3 A2 A1 A0 A

2.7 ARITHMETIC LOGIC UNIT (ALU): 4 BITS

The arithmetic logic unit is a 4-bit arithmetic circuit to perform arithmetic and bit processing such as binary addition, logical operation, incrementation, decrementation, and comparison.

2.8 PROGRAM STATUS WORD (PSW): 4 BITS

The program status word consists of skip flags (SK1 and SK0) and a carry flag (C). Bit 1 of the PSW is fixed at 0. Fig. 2-8 Program Status Word Configuration SK1 SK0 0 C PSW 3210 (1) Skip flags (SK1 and SK0) Skip flags store the following skip status:

• Stacking by the LAI instruction
• Stacking by the LHLI instruction
• Skip condition establishment by any instruction other than stack instructions The skip flags are set and reset automatically when respective instructions are executed. (2) Carry flag (C) The carry flag is set to 1 when a carry from bit 3 of the ALU occurs when the add instruction (ACSC) is executed. The flag is reset to 0 when the carry does not occur. The SC and RC instructions respectively set and reset the carry flag. The SKC instruction tests the contents of the flag. The content of the PSW are automatically stored in the stack area when the call instruction is executed. It cannot be restored by the return inhstruction. When the RESET signal is input, SK1 and SK0 are both cleared to zero and C becomes undefined.

µPD7554A, 7554A(A)

2.9 SYSTEM CLOCK GENERATOR

The system clock generator contains an RC oscillator, 1/2 divider, and standby (STOP/HALT) mode control circuit. Fig. 2-9 System Clock Generator STANDBY RELEASE RESET ( ) (To CPU) CL (System Clock) RESET (High) HALTNote STOP Note HALT F/F QS R QS R STOP F/F CL2 CL1 C R 1/2 φ RC Oscillator Note Instruction execution Oscillator Stop The RC oscillator oscillates with an external resistor R connected to pins CL1 and CL2. (A capacitor C is incorporated.) The RC oscillator serves merely as a reverse buffer if inputs an external clock through the CL1 input. The RC oscillator outputs the system clock (CL) which is 1/2 divided to the CPU clock ( φ). The control circuit in the standby mode consists mainly of STOP F/F and HALT F/F. The STOP F/F is set by the STOP instruction, blocking any clock from being supplied. The STOP F/F stops RC oscillation during operation of the RC oscillator (STOP mode). The STOP F/F is reset by the STANDBY RELEASE signal (which goes active when even one test request flag is input) or at the fall of the RESET input, to cause the RC oscillator to start oscillation and supplying each clock. The HALT F/F is set by the HALT instruction to disable the input to the 1/2 divider which generates the CPU clock φ, stopping only the CPU clock φ (HALT mode). The HALT F/F is set and reset as in the case of the STOP F/F. Resetting the HALT F/F cause the RC oscillator to start supplying the CPU clock φ.

µPD7554A, 7554A(A)

2.10 CLOCK CONTROL CIRCUIT

The clock control circuit consists of 2-bit clock mode registers (CM2 and CM1), prescalers 1, 2 and 3, and a multiplexer. The circuit inputs the system clock generator output (CL) and the event pulse (P00). It also selects a clock source and a prescaler according to the specifications of clock mode register and supplies a count pulse (CP) to the timer/event counter. Fig. 2-10 Clock Control Circuit CP CL P00 PRESCALER 1 (1/4) PRESCALER 2 (1/8) PRESCALER 3 (1/8) OPL Note CM2 CM1 Internal Bus Note Instruction execution Use the OPL instruction to set codes in the clock mode registers. Fig. 2-11 Clock Mode Register Format Clock Mode Register Caution When setting codes in the clock mode registers using the OPL instruction, be sure to set bit 0 of the accumulator to 0. (Bit 0 corresponds to CM0 of the µPD7500 of EVAKIT-7500B in emulation.) CM2 CM1 CM2 CM1 Count Pulse Frequency (CP) 0 0 CL × 256 0 1 P00 1 0 CL × 1 1 1 CL × 1

µPD7554A, 7554A(A)

2.11 TIMER/EVENT COUNTER

The timer/event counter is based on an 8-bit count register as shown in Fig. 2-12. Fig. 2-12 Timer/Event Counter 8-BIT COUNT REG TIMERNote RESET CLR CP 8TCNTAMNote INTT (To Test Control Circuit) Note Instruction execution Internal Bus Count Holding Circuit The 8-bit count register is a binary 8-bit up-counter which is incremented whenever a count pulse (CP) is input. The register is cleared to 00H when the TIMER instruction is executed, RESET signal is input, or an overflow occurs (FFH to 00H). As the count pulse, the clock mode register can select one of the following four. See 2.10 “CLOCK CONTROL CIRCUIT”. 4 32 256 The count register continues to be incremented as long as count pulses are input. The TIMER instruction clears the count register to 00H and triggers the timer operation. The count register is incremented in synchronization with the CP (or the rise of the P00 input when an external clock is used). On the count reaches 256, the register returns the count value to 00H from FFH, generates the overflow signal INTT, and sets the INTT test flag INTT RQF. In this way, the count register counts over from 00H. To recognize the overflow, test the flag INTT RQF using the SKI instruction. When the timer/event counter serves as a timer, the reference tiome is determined by the CP frequency. The precision is determined by the RC oscillation or CL1 external input frequency when the system clock system is selected and by the P00 input frequency when the P00 input is selected. The content of the count register can be read at any time by the TCNTAM instruction. This function allows checking the current time of the timer and counting event pulses input to the P00 input. This enables the number of even pulses that have been generated so far (event counter function). The count holding circuit ignores the change of the count pulse (CP) during execution of the TCNTAM instruction. This is to prevent reading undefined data in the count register using the TCNTAM instruction while the counter is being updated. Since the timer/event counter operates the system clock system (CL) or the P00 input for count pulses, it is used to cancel the HALT mode which stops the CPU clock φ as well as the STOP mode which stops the system clock CL. (See 3 “STANDBY FUNCTIONS” .)

µPD7554A, 7554A(A)

2.12 SERIAL INTERFACE

The serial interface consists of an 8-bit shift register, 3-bit shift mode register, and 3-bit counter. It is used for input/output of serial data. Fig. 2-13 Serial Interface Block Diagram INT0P00/INT0 P01/SCK P02/SO P03/SI IPL Note TSIOAMNote TAMSIONote LSB 8–BIT SHIFT REG MSB 3–BIT CNT φ RS F/F R SQ INTS SIO Note SM3 SHIFT MODE REG OPLNote 48 8 Internal Bus Note Instruction execution Remarks 1. φ indicates the internal clock signal (system clock). 2. SM3 and INT0 go to the test control circuit. Input/output of serial data is controlled by the serial clock. The highest bit (bit 7) of the shift register is output from the SO line at rise of the serial clock (SCK pin signal). At its fall, the contents of the shift register is shifted by one bit (bit n -> bit n+1) and data on the SI line is loaded to the lowest bit (bit 0) of the shift register. The 3-bit counter (octal counter) counts serial clock pulses. Wthenever it counts eight clock pulses (on completion of 1-byte serial data transfer), the counter generates an internal test request signal INTS to set the test request flag (INT0/S RQF). Fig. 2-14 Shift Timing INTS RQF Setting Timing SCK SI SO DI7 DO7 MSB DO6 DO5 DO4 DO3 DO2 DO1 DO0 DI6 DI5 DI4 DI3 DI2 DI1 DI0 LSB Remarks 1. DI: Serial data input 2. DO: Serial data output

µPD7554A, 7554A(A) The serial interface sets serial data for transmission in the shift register using the TAMSIO instruction and starts the transfer using the SIO instruction. To recognize the termination of one-byte transfer, check the test request flag INT0/S RQF using the corresponding instruction. The serial interface starts serial data reception, using the SIO instruction, checks the termination of one-byte transfer using the instruction, and then receives data from the shift register by executing the TSIOAM instruction. Two types of serial clock sources are available: one is the system clock φ and the other is the external clock (SCK input). They are selected respectively by bits 2 and 1 (SM2 and SM1) of the shift mode register. When the system clock φ is selected and the SIO instruction is executed, the clock pulse is supplied to the serial interface as a serial clock to control serial data input/output and is output from the SCK pin. When the system clock φ pulse is supplied eight times, the supply to the serial interface is automatically stopped and the SCK output remains high. Since serial data input/output stops automatically after transfer of one byte. The programmer does not need to control the serial clock. In this case, the transfer speed is determined by the system clock frequency. In this mode, it is possible to read receive data (by the TSIOAM instruction) and write data (by the TAMSIO instruction) from and to the shift register only by waiting for 6 machine cycles after execution of the SIO instrucction on the program without waiting until the INT0/S RQF is set. Fig. 2-15 TAMSIO/TSIOAM Instruction Execution Timing SCK SIO TAMSIO TSIOAMWait (6 Machine Cycle)Instruction Execution Machine Cycle When the external clock (SCK input) is selected, the interface inputs serial clock pulses from the SCK input. When an external serial clock pulse is input eight times, the INT0/S RQF is set and the termination of one-byte transfer can be recognized. However, the eight serial clocks to be input must be counted on the side of the external clock source because serial clock disable control is not performed internally. The transfer speed is determined by the external serial clock within the range from DC to the maximum value limited by the standard. When the external clock is used, the SIO, TAMSIO, or TSIOAM instruction the execution must be executed while the serial clock pulse SCK is high. If such an instruction is executed while the SCK is rising or falling or is low, the function of the instruction is not guaranteed.

µPD7554A, 7554A(A) Fig. 2-16 Shift Mode Register Format Shift Mode Register Settings for serial interface operation and the associated mode of the port 0 INT0/INTS selection SM3 Test Sources

0 INTS

1 INT0

Caution When setting a code in the shift mode register using the OPL instruction, be sure to set bit 0 of the accumulator to 0 (Bit 0 corresponds to CM0 of the µPD7500H of EVAKIT-7500B in emulation). In the system which does not require serial interface, the 8-bit shift register can be used as a simple register and data can be read or writtene by the TSIOAM or TAMSIO instruction when serial operation is off.

2.13 TEST CONTROL CIRCUIT

The µPD7554A is provided with the following three types of test sources (one external source and two internal sources): The test control circuit checks consist mainly of test request flags (INTT RQF and INT0/S RQF) which are set by three different test sources and the test request flag control circuit which checks the content of test request flags using the SKI instruction and controls resetting the checked flags. The INT0 and INTS are common in the request flag. Which one is selected is determined by bit 3 (SM3) of the shift mode register. SM3 SM2 SM1 SM2 SM1 P03/SI P02/SO P01/SCK Serial Operation

00 Port input Port input Port input Stop

01 φ continuous output SI input SO output SCK input Operation based on external clock 1 1 SCK output ( φ × 8) Operation based on φ Test Sources Internal/External Request Flag INTT (Overflow from timer/event counter) Internal INTT RQF INT0 (Test request signal from P00 pin) External INT 0/S RQF INTS (Transfer end signal from serial interface) Internal SM3 Test Sources

µPD7554A, 7554A(A) The INTT RQF is set when a timer overflow occurs and is reset by the SKI or TIMER instruction. The INT0/S request flag functions in the following two ways according to the setting of the SM3: (1) SM3 = 0 The INTS is validated. The request flag INT0/S RQF is set when the INTS signal to indicate the termination of 8- bit serial data transfer is issued. The flag is reset when the SKI or SIO instruction is executed. (2) SM3 = 1 The IN0 is validated. The request flag INT0/S RQF is set when the leading edge signal enters the INT0/P00 pin. The flag is reset when the SKI instruction is executed. The OR output of each test request flag is used to cancel the standby mode (STOP/HALT mode). If one or more request flags are set in the standby mode, the standby mode is cancelled. The RESET signal cancels every request flag and the SM3. In the reset initial status, the INTS is selected and the INT0 input is disabled. Fig. 2-17 Test Control Circuit Block Diagram INTS TEST RQF CONTROL SKINote TIMERNote S R INTT RQF Q S R INT0/S RQF QNONSYNC EDGE GATE NONSYNC EDGE GATE SM3 OPL Note SIONote INT0 INTT STANDBY RELEASE Internal Bus Note Instruction execution Remark SM3 is bit 3 of the shift mode register.

µPD7554A, 7554A(A) 3. STANDBY FUNCTIONS The µPD7554A provides two types of standby modes (STOP and HALT modes) to save power while the program is on standby. The STOP and HALT modes are set by the STOP and HALT instructions, respectively. The standby mode halts program execution, however, it holds the contents of all the internal registers and data memory that have been stored. The timer can operate even in the standby mode. The standby mode is canceled when the test request flag (INTT RQF or INT0/S RQF) is set or by RESET input. Note that if even one test request flag is set, the device cannot enter either the STOP or HALT mode even though the STOP or HALT instruction is executed. Before setting the standby mode at a point where a test request flag may be set, execute the SKI instruction to reset the test request flag. Table 3-1 relates the STOP mode to the HALT mode. An essential difference between them is found when RC oscillation supplies the system clock: by stopping the oscillation, the CL output stops in the STOP mode and does not stop in the HALT mode. Thus the amount of the power consumption of the RC oscillator equals to the difference in the amounts of the basic power consumption between the STOP mode and HALT mode. Note that the STOP mode enables the low supply voltage data to be retained in the data memory. Table 3-1 The Relation Between STOP and HALT Modes

3.1 STOP MODE

The STOP mode stops the RC oscillation and 1/2 divider in the system clock generator. Therefore, the operations of requiring the system clock stubsystem (CL and φ) such as the CPU are stopped. Since the STOP mode allows operation of the clock control circuit, the timer can operate if the P00 input is selected as the count pulse (CP). Note that the STOP mode stops only the φ signal, allowing the CL output when system clock generation is not drived by the RC oscillation, but drived by the external CL1 input. In such a case, the STOP mode causes the same state as in the case of the HALT mode described below. Therefore, the STOP instruction is effective for setting the STOP mode only during RC oscillation.

3.2 HALT MODE

The HALT mode stops only the 1/2 divider in the system clock generator (allowing operation of the system clock CL and stopping the CPU clock φ). Therefore, the operations of the CPU requiring the φ signal is stopped in the HALT mode. Since the HALT mode allows operation of the clock control circuit, the circuit inputs the CL signal from the clock generator and the external count clock (P00) to supply the count pulses (CP) for both subsystems selectively to the timer. Thus, the timer can operate depending on the both-system count pulses and continue counting time. Setting RC Oscillation φ P00 CPU Timer Cancellation FactorInstruction (CL) STOP mode STOP × s s INTT RQF l l × INT0/S RQF HALT mode HALT l l l l RESET input l l : Operation enabled s s : Operation enabled depending on mode selection × : Stop

µPD7554A, 7554A(A)

3.3 CANCELLING THE STANDBY MODE

(1) Cancelling the STANDBY mode by test request flag As well as the STOP mode and HALT mode, the STANDBY mode is canceled when the test request flag (INTT RQF or INT0/S RQF) is set in the mode. The program starts executing the instruction that follows the HALT instruction that follows the STOP or HALT instruction. Cancellation of the HALT mode does not affect the content of any register or the data memory, that is retained in the mode. (2) Cancelling the STANDBY mode by RESET input RESET input unconditionally cancels the STANDBY mode as well as nthe STOP mode and HALT mode. Fig. 3-1 shows the STANDBY mode cancel timing. Fig. 3-1 STANDBY Mode Cancel Timing by RESET Input RESET STOP/HALT STOP/HALT ModeOperating Mode Instruction Cancellation Normal Reset Operation (Starting from address 0) The STANDBY mode is maintained while the RESET input is being active (high). When the RESET input goes low, the STANDBY mode is cancelled and the CPU starts to execute the program from address 0 after a normal reset operation. Note that RESET input does not affect the content of the data memory that is retained in the STANDBY mode, however, the contents of the other registers become undefined on cancellation of the mode.

µPD7554A, 7554A(A) 4. RESET FUNCTIONS The µPD7554A is reset and initialized when the RESET pin inputs a high or active RESET signal as follows:

4.1 DETAILS OF INITIALIZATION

(1) The program counter (PC9-PC0) is cleared to zero. (2) The skip flags (SK1 and SK0) in the program status word are reset to zero. (3) The count register in the timer-event counter is cleared to 00H. (4) The clock control circuit becomes as follows:

• Clock mode registers (CM2 and CM1) = 0 256
• Prescalers 1, 2, and 3 = 0 (5) The shift mode register (SM3 to SM1) is cleared to zero. → Shifting of the serial interface is stopped. → The port 0 enters the input mode (high impedance). Note1 → INT0/S, INTS is selected. (6) The test request flag (INTT RQF or INT0/S RQF) is reset to zero. (7) The contents of the data memory and the following registers become undefined: Stack pointer (SP) Accumulator (A) Carry flag (C) General registers (H and L) Output latch of each port (8) The output buffer of every port goes off and has high impedance Note2. The I/O port enters the input mode. Note1. When the pull-up and pull-down resistors are selected using a mask option, the former has high level and the latter has low level. 2. When the pull-up and pull-down resistors are selected in the port 0 using a mask option, the former has high level and the latter has low level. When the pull-up resistor is selected in the ports 10 and 11 using a mask option, the resistor has high level. Caution When the STANDBY mode is cancelled by the RESET signal, the content of the data memory is retained without becoming undefined. When the RESET input is cancelled, the program is executed starting with address 000H. The content of each register shall either be initialized in the process of the program or reinitialized depending on conditions.

µPD7554A, 7554A(A) 5. µPD7554A INSTRUCTION SET (1) Operand representation and description addr 10-bit immediate data or label caddr 10-bit immediate data or label caddr1 100H to 107H, 140H to 147H, 180H to 187H, IC0H to IC7H immediate data or label mem 6-bit immediate data or label n5 5-bit immediate data or label n4 4-bit immediate data or label n2 2-bit immediate data or label bit 2-bit immediate data or label pr HL-, HL+, HL (2) Mnemonics for operation descriptions A : Accumulator H : H register L : L register HL : Pair register HL pr : Pair register HL-, HL+, or HL SP : Stack pointer PC : Program counter C : Carry flag PSW : Program status word SIO : Shift register CT : Count register In : Immediate data to n5, n4 or n2 Pn : Immediate data to addr, caddr, or caddr1 Bn : Immediate data to bit Dn : Immediate data to mem Rn : Immediate data to pr (××) : Content addressed by ×× ×H : Hexadecimal data

µPD7554A, 7554A(A) (3) Port/mode register selection IPL Instruction L Port

0 Port 0

8 Port 8

L F H E H D H C H B H A H 983210 B i t 321032103210 Port Port 11 Port 10 Port 8 (4) Selection of pair register addressing pr R 1 R0 HL– 0 0 HL+ 0 1 HL 1 0

µPD7554A, 7554A(A) Accumulator & Carry Flag Manipulation Instructions Load/Store Instructions Operation Instructions Mne- Ope- Operation Code Operation Skip monic rands B1 B2 Condition L A I n 4 0001I 3 I2 I1 I0 A← n4 Loads n4 to the accumulator. Stack LAI L H I n 2 001010I 1 I0 H← n2 Loads n2 to H register. L A M p r 010100 R 1 R0 A← (pr) pr = HL –, HL +, HL Loads the contents of the memory L = FH(HL –) address by pr to the accumulator. L = 0 (HL +) LHLI n5 1 1 0 I 4 I3 I2 I1 I0 H← 0I4, L← I3–0 Loads n5 to the pair register HL. Stack LHLI S T 01010111 (HL)← A Stores the contents of the accumulator in the memory addressed by HL. STII n4 0100I 3 I2 I1 I0 (HL)← n4, L← L+1 Stores n4 in the memory addressed by HL and increments the L register. X A L 01111011 A ↔ L Exchanges the contents of the accumu- lator and the L register. X A M p r 010101 R 1 R0 A↔ (pr) pr = HL – , HL + , HL Exchanges the contents of the accumu- L = FH(HL–) lator and the memory addressed by pr. L = 0 (HL+) AISC n4 0000I 3 I2 I1 I0 A← A + n4 Adds the accumulator to n4. Carry A S C 01111101 A ← A + (HL) Adds the contents of the accumulator Carry and the memory addressed by HL. Adds the contents of the accumulator, ACSC 01111100 A , C ← A + (HL) + C the memory addressed by HL, and of Carry the carry flag. Calculate the exclusive OR of the E X L 01111110 A ← A ∀ (HL) contents of the accumulator and the memory addressed by HL. C M A 01111111 A ← A–– Complements the accumulator. R C 01111000 C ← 0 Resets the carry flag. S C 01111001 C ← 1 Sets the carry flag. I L S 01011001 L ← L + 1 Increments the L register. L = 0 IDRS mem 0011110100 D 5 D4 D3 D2 D1 D0 (mem)← (mem) + 1 Increments the contents of the memory (mem) = 0addressed by mem. D L S 01011000 L ← L – 1 Decrements the L register. L = FH DDRS mem 0011110000 D 5 D4 D3 D2 D1 D0 (mem)← (mem) – 1 Decrements the contents of the memory (mem) = FHaddressed by mem. R M B b i t 011010 B 1 B0 (HL)bit← 0 Resets the bits specified by B 1–0, of the memory addressed by HL. S M B b i t 011011 B 1 B0 (HL)bit← 1 Sets the bits specified by B 1–0, of the memory addressed by HL. Increment/Decre- ment Instructions Memory Bit Manipulation Instructions Note Instruction Group Note

µPD7554A, 7554A(A) Mne- Ope- Operation Code Operation Skip monic rands B1 B2 Condition JMP addr 001000 P 9 P8 P7 P6 P5 P4 P3 P2 P1 P0 PC9–0← P9–0 Jumps to the address specified by P 9–0. JCP addr 1 0 P 5 P4 P3 P2 P1 P0 PC5–0← P5–0 Jumps to the address specified by replacing PC 5–0 with P 5–0. (SP–1)(SP–2)(SP–4)← PC9–0 Saves the contents of PC and PSW to the CALL caddr 001100 P 9 P8 P7 P6 P5 P4 P3 P2 P1 P0 (SP–3)← PSW, SP← SP – 4 stacxk memory, decrements SP by 4, and PC9–0← P9–0 calls the address specified by caddr. (SP–1)(SP–2)(SP–4)← PC9–0 Saves the contents of PC and PSW to the CAL caddr1 1 1 1 P 4 P3 P2 P1 P0 (SP–3)← PSW, SP← SP – 4 stacxk memory, decrements SP by 4, and PC9–0← 0 1 P4 P3 0 0 0 P 2 P1 P0 calls the address specified by caddr1. R T 01010011 PC9–0← (SP)(SP+2)(SP+3) Restores the contents of the stack SP← SP + 4 memory to PC, and increments SP by 4. PC9–0← (SP)(SP+2)(SP+3) Restores the contents of the stack R T S 01011011 S P ← SP + 4 memory to PC, increments SP by 4, then skip unconditionally and causes unconditional skipping. Transfers the two low-order bits of the TAMSP 0011111100110001 PC5–4← A1–0 accumulator to SP 5–4 and the three high- SP3–1← (HL)3–1, SP0← 0 order bits of the memory addressed by HL to SP 3–1. S K C 01011010 Skip if C = 1 Causes skipping if the carry flag is 1. C = 1 SKABT bit 011101 B 1 B0 Skip if A bit = 1 Causes skipping of the bit of the accumu- Abit = 1lator, which is specified by B 1-0 is 1. Causes skipping of the bit of the memory SKMBT bit 011001 B 1 B0 Skip if (HL) bit = 1 addressed by HL, which is specified by (HL) bit = 1 B1–0 is 1. Causes skipping of the bit of the memory SKMBF bit 011000 B 1 B0 Skip if (HL) bit = 0 addressed by HL, which is specified by (HL) bit = 0 B1–0 is 0. Causes skipping if the contents are the SKAEM 01011111 Skip if A = (HL) same between the accumulator and the A = (HL) memory addressed by HL. SKAEI n4 001111110110I 3 I2 I1 I0 Skip if A = n4 Skips if the accumulator is equal to n4. A = n4 S K I n 2 00111101010000I 1 I0 Skip if INT RQF = 1 Skips if INT RQF is 1, and then sets INT RQF = 1Then reset INT RQF INT RQF to 0. Note Jump Instructions Subroutine/stack control instructions Skip Instructions Note Instruction Group Uncondition- ally

µPD7554A, 7554A(A) Mne- Ope- Operation Code Operation Skip monic rands B1 B2 Condition Transfers the contents of the accumulator SIO7–4← A to the four high-order bits of the shift TAMSIO 0011111100111110 SIO3–0← (HL) register and the contents of the memory addressed by HL to the four low-order bits. Transfers the four high-order bits of the TSIOAM 0011111100111010 A← SIO7–4 shift register to the accumulator and the (HL)← SIO3–0 four low-order bits to the memory addressed by HL. S I O 0011111100110011 Start SIO Starts shifting. TIMER 0011111100110010 Start Timer Starts timer operation. Transfers the four high-order bits of A← CT7–4 the count register to the accumulator TCNTAM 0011111100111011 (HL)← CT3–0 and the four low-order bits to the memory addressed by HL. I P L 01110000 A ← Port (L) Loads the contents of the port specified by the L register to the accumulator. Outputs the contents of the accumu- O P L 01110010 Port/Mode reg. (L) ← A lator to the port specified by the L register or the mode register. RPBL Note2

01011100 Port bit (L) ← 0 Resets the bits of ports 8, 10, and 11,

that are specified by the L register. SPBL Note2

01011101 Port bit (L) ← 1 Sets the bits of ports 8, 10, and 11,

that are specified by the L register. HALT 0011111100110110 Set Halt Mode Sets the HALT mode. STOP 0011111100110111 Set Stop Mode Sets the STOP mode. N O P 00000000 N o operation Performs no operation for one machine cycle. Note1 SIO control instructions Timer control instructions Input/output instructionsCPU control Instructions Note1. Instruction Group 2. SPBL and RPBL are bit-wise set/reset instructions. They perform output to each 4-bit port including the specified bits as well as set and reset operation (They output the contents of the output latch to bits other than the specified bits.). Before executing these instructions, int ialize the contents of the output latch using the OPL instruction.

µPD7554A, 7554A(A) 6. ELECTRICAL SPECIFICATIONS µPD7554A: ABSOLUTE MAXIMUM RATINGS (T a = 25 °C) Parameter Symbol Test Conditions Rating Unit Supply voltage V DD –0.3 to +7.0 V Except ports 10 and 11 –0.3 to V DD + 0.3 V Input voltage V I Ports 10 and 11 Note 1 –0.3 to VDD + 0.3 V Note 2 –0.3 to +11 V Except ports 8, 10, 11 –0.3 to V DD + 0.3 V Output voltage V O Ports 8, 10 and 11 Note 1 –0.3 to VDD + 0.3 V Note 2 –0.3 to +11 V Output current high I OH 1 pin –5 mA All pins in total –15 mA P01, P02 5 mA Output current low I OL 1 pin Port 8 30 mA Others 15 mA All pins in total 100 mA Operating temperature T opt –10 to +70 °C Storage temperature T stg –65 to +150 °C Power consumption P d Ta = 70 °C Shrink DIP 480 mW Mini flat 250 Note 1. CMOS input/output or N-ch open-drain output + pull-up resistor built-in input/output 2. N-ch open-drain input/output Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. H

µPD7554A, 7554A(A) µPD7554A(A): ABSOLUTE MAXIMUM RATINGS (T a = 25 °C) Parameter Symbol Test Conditions Rating Unit Supply voltage V DD –0.3 to +7.0 V Except ports 10 and 11 –0.3 to V DD + 0.3 V Input voltage V I Ports 10 and 11 Note 1 –0.3 to VDD + 0.3 V Note 2 –0.3 to +11 V Except ports 8, 10, 11 –0.3 to V DD + 0.3 V Output voltage V O Ports 8, 10 and 11 Note 1 –0.3 to VDD + 0.3 V Note 2 –0.3 to +11 V Output current high I OH 1 pin –5 mA All pins in total –15 mA P01, P02 5 mA Output current low I OL 1 pin Port 8 30 mA Others 15 mA All pins in total 100 mA Operating temperature T opt –40 to +85 °C Storage temperature T stg –65 to +150 °C Power consumption P d Ta = 85 °C Shrink DIP 350 mW Mini flat 195 Note 1. CMOS input/output or N-ch open-drain output + pull-up resistor built-in input/output 2. N-ch open-drain input/output Caution Even if one of the parameters exceeds its absolute maximum rating even momentarily, the quality of the product may be degraded. The absolute maximum rating therefore specifies the upper or lower limit of the value at which the product can be used without physical damages. Be sure not to exceed or fall below this value when using the product. CAPACITY (T a = 25 °C, VDD = 0 V) Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Input capacity C IN P00, P03 15 pF Output capacity C OUT Port 8 35 pF I/O capacity C IO P01, P02 15 pF Ports 10 and 11 35 pF f = 1 MHz Unmeasured pins returned to 0 V.

µPD7554A, 7554A(A) RESONATOR CHARACTERISTICS µPD7554A : T a = –10 to +70 °C, VDD = 2.7 to 6.0 V µPD7554A(A) : T a = –40 to +85 °C, VDD = 2.7 to 6.0 V Parameter Symbol Test Conditions MIN. TYP. MAX. Unit VDD = 5 V ± 10% 400 500 600 kHz fCC R = 56 k Ω ± 2 % VDD = 3 V ± 10% 200 250 300 kHzR = 100 k Ω ± 2% fC Duty = 50% VDD = 4.5 to 6.0 V 10 710 kHz 10 350 kHz tCR, tCF 0.2 µs tCH, tCL VDD = 4.5 to 6.0 V 0.7 50 µs 1.45 50 µs RESONATOR CHARACTERISTICS (T a = –10 to +70 °C, VDD = 2.5 to 3.3 V) Note Parameter Symbol Test Conditions MIN. TYP. MAX. Unit fCC R = 150 k Ω ± 2% 140 180 220 kHz R = 150 k Ω ± 2% 140 175 210 kHzVDD = 2.5 V System clock input fC Duty = 50 % 10 250 kHzfrequency (CL1) CL1 input rising tCR, tCF 0.2 µsand falling time CL1 input high/low t CH, tCL 25 0 µslevel duration RESONATOR CHARACTERISTICS (T a = –10 to +70 °C, VDD = 2.0 to 3.3 V) Note Parameter Symbol Test Conditions MIN. TYP. MAX. Unit fCC R = 240 k Ω ± 2% 65 120 145 kHz R = 240 k Ω ± 2% 65 100 130 kHzVDD = 2.0 V System clock input fC Duty = 50 % 10 150 kHzfrequency (CL1) CL1 input rising t CR, tCF 0.2 µsand falling time CL1 input high/low t CH, tCL 3.3 50 µslevel duration Note µPD7554A only The following circuits are recommended: À RC oscillation \` External clock CL1 CL2 PD7554Aµ CL1 CL2 PD7554Aµ R CMOS Leave Open System clock oscilla- tor frequency (CL1 and CL2) System clock oscilla- tor frequency (CL1 and CL2) System clock oscilla- tor frequency (CL1 and CL2) System clock input fre- quency (CL1) CL1 input rising and falling time CL1 input high/low level duration

µPD7554A, 7554A(A) DC CHARACTERISTICS µPD7554A : T a = –10 to +70 °C, VDD = 2.7 to 6.0 V µPD7554A(A) : T a = –40 to +85 °C, VDD = 2.7 to 6.0 V Parameter Symbol Test Conditions MIN. TYP. MAX. Unit VIH1 Except CL1 0.7V DD VDD V Input voltage high V IH2 CL1 V DD – 0.5 V DD V VIH3 Ports 10 and 11 Note1 0.7VDD 9V Input voltage low VIL1 Except CL1 0 0.3V DD V VIL2 CL1 0 0.5 V VDD = 4.5 to 6.0 V VDD – 2.0 V Output voltage high V OH IOH = –1 mA IOH = –100 µAV DD – 1.0 V VDD = 4.5 to 6.0 V 0.4 V P01, P02 IOL = 1.6 mA IOL = 400 µA 0.5 V VDD = 4.5 to 6.0 V 0.4 VIOL = 1.6 mA Output voltage low V OL Ports 10 and 11 V DD = 4.5 to 6.0 V 2.0 VIOL = 10 mA IOL = 400 µA 0.5 V VDD = 4.5 to 6.0 V 2.0 VPort 8 I OL = 15 mA IOL = 600 µA 0.5 V ILIH1 VIN = VDD Except CL1 3 µA Input leak current high I LIH2 CL1 10 µA ILIH3 VIN = 9 V, ports 10 and 11 Note1 10 µA Input leak current low ILIL1 VIN = 0 V Except CL1 –3 µA ILIL2 CL1 –10 µA Output leak current high ILOH1 VOUT = VDD 3 µA ILOH2 VOUT = 9 V, ports 8, 10, and 11 Note1 10 µA Output leak current low I LOL VOUT = 0 V –3 µA Input pin built-in resistor Port 0, RESET 23.5 47 70.5 K Ω(pull-up/down resistor) Output pin built-in resistor Ports 10 and 11 7.5 15 22.5 K Ω(pull-up resistor) VDD = 5 V ± 10 % 270 900 µA IDD1 Operating mode R = 56 k Ω ± 2 % VDD = 3 V ± 10 % 80 240 µAR = 100 k Ω ± 2 % Supply current Note2 VDD = 5 V ± 10 % 120 400 µA IDD2 HALT mode R = 56 k Ω ± 2 % VDD = 3 V ± 10 % 35 110 µA R = 100 k Ω ± 2 % IDD3 STOP mode VDD = 5 V ± 10 % 0.1 10 µA VDD = 3 V ± 10 % 0.1 5 µA Note 1. For N-ch open-drain input/output selection 2. The current flowing in built-in pull-up and pull-down resistors is excluded.

µPD7554A, 7554A(A) AC CHARACTERISTICS µPD7554A : T a = –10 to +70 °C, VDD = 2.7 to 6.0 V µPD7554A(A) : T a = –40 to +85 °C, VDD = 2.7 to 6.0 V Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Internal clock cycle time t CY Note VDD = 4.5 to 6.0 V 2.8 200 µs 5.7 200 µs P00 event input frequency f PO Duty = 50% VDD = 4.5 to 6.0 V 0 710 kHz 0 350 kHz P00 input rise/fall time t POR, tPOF 0.2 µs tPOH, tPOL VDD = 4.5 to 6.0 V 0.7 µs 1.45 µs Input VDD = 4.5 to 6.0 V 2.0 µs SCK cycle time t KCY Output 2.5 µs Input 5.0 µs Output 5.7 µs Input VDD = 4.5 to 6.0 V 1.0 µs SCK high/low level width t KH, tKL Output 1.25 µs Input 2.5 µs Output 2.85 µs SI setup time (to SCK ↑ )t SIK 100 ns SI hold time (from SCK ↑)t KSI 100 ns SCK↓→ SO output delay time t KSO VDD = 4.5 to 6.0 V 850 ns 1200 ns INT0 high/low level width t IOH, tIOL 10 µs RESET high/low level tRSH, tRSL 10 µswidth Note tCY = 2/f CC or 2/f C AC Timing Test Point (Except CL1 Input)

0.7 VDD

0.3 VDD

µPD7554A, 7554A(A) DC CHARACTERISTICS (T a = –10 to +70 °C, VDD = 2.5 to 3.3 V) Note1 Parameter Symbol Test Conditions MIN. TYP. MAX. Unit VIH1 Except CL1 0.8 V DD VDD V Input voltage high V IH2 CL1 V DD – 0.3 V DD V VIH3 Ports 10 and 11 Note2 0.8 VDD 9V VIL1 Except CL1 0 0.2V DD V Input voltage low V IL2 CL1 0 0.3 V VIL3 Ports 10 and 11 0 0.2V DD V Output voltage high V OH IOH = –80 µAV DD – 1.0 V P01, P02 I OL = 350 µA 0.5 V Output voltage low V OL Ports 10 and 11 I OL = 350 µA 0.5 V Port 8 I OL = 500 µA 0.5 V ILIH1 VIN = VDD Except CL1 3 µA Input leak current high I LIH2 CL1 10 µA ILIH3 VIN = 9 V, ports 10 and 11 Note2 10 µA Input leak current low ILIL1 VIN = 0 V Except CL1 –3 µA ILIL2 CL1 –10 µA Output leak current high ILOH1 VOUT = VDD 3 µA ILOH2 VOUT = 9 V, ports 8, 10, and 11 Note2 10 µA Output leak current low I LOL VOUT = 0 V –3 µA Input pin built-in resistor Port 0, RESET 23.5 47 70.5 K Ω(pull-up/down resistor) Output pin built-in resistor Ports 10 and 11 7.5 15 22.5 K Ω(pull-up resistor) IDD1 VDD = 3 V ± 10% 55 180 µA VDD = 2.5 V 40 150 µA Supply current Note3 IDD2 HALT mode VDD = 3 V ± 10% 25 80 µA VDD = 2.5 V 18 60 µA IDD3 STOP mode 0.1 5 µA Note 1. µPD7554A only 2. For N-ch open-drain input/output selection 3. The current flowing in built-in pull-up and pull-down resistors is excluded. R = 150 kΩ ± 2% Operating mode

µPD7554A, 7554A(A) AC CHARACTERISTICS (T a = –10 to +70 °C, VDD = 2.5 to 3.3 V) Note1 Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Internal clock cycle time t CYNote2 8.0 200 µs P00 event input frequency f PO 0 250 kHz P00 input rise/fall time t POR, tPOF 0.2 µs P00 input high/low level tPOH, tPOL 2.0 µswidth SCK cycle time t KCY Input 8.0 µs Output 10.0 µs SCK high/low level width t KH, tKL Input 4.0 µs Output 5.0 µs SI setup time (to SCK ↑ )t SIK 300 ns SI hold time (from SCK ↑)t KSI 300 ns SCK↓→ SO output delay time t KSO CL = 100 pF 2000 ns INT0 high/low level width t IOH, tIOL 30 µs RESET high/low level tRSH, tRSL 30 µs width Note1. µPD7554A only 2. tCY = 2/fCC or 2/f C AC Timing Test Point (Except CL1 Input)

0.8 VDD

0.2 VDD

µPD7554A, 7554A(A) DC CHARACTERISTICS (T a = –10 to +70 °C, VDD = 2.0 to 3.3 V) Note1 Parameter Symbol Test Conditions MIN. TYP. MAX. Unit VIH1 Except CL1 0.85V DD VDD V Input voltage high V IH2 CL1 V DD – 0.2 V DD V VIH3 Ports 10 and 11 Note2 0.85VDD 9V VIL1 Except CL1 0 0.15V DD V Input voltage low V IL2 CL1 0 0.2 V VIL3 Ports 10 and 11 0 0.2V DD V Output voltage high V OH IOH = –70 µAV DD – 1.0 V P01, P02 I OL = 270 µA 0.5 V Output voltage low V OL Ports 10 and 11 I OL = 300 µA 0.5 V Port 8 I OL = 400 µA 0.5 V ILIH1 VIN = VDD Except CL1 3 µA Input leak current high I LIH2 CL1 10 µA ILIH3 VIN = 9 V, ports 10 and 11 Note2 10 µA Input leak current low ILIL1 VIN = 0 V Except CL1 –3 µA ILIL2 CL1 –10 µA Output leak current high ILOH1 VOUT = VDD 3 µA ILOH2 VOUT = 9 V, ports 8, 10, and 11 Note2 10 µA Output leak current low I LOL VOUT = 0 V –3 µA Input pin built-in resistor Port 0, RESET 23.5 47 70.5 K Ω(pull-up/ down resistor) Output pin built-in resistor Ports 10 and 11 7.5 15 22.5 K Ω(pull-up resistor) IDD1 VDD = 3 V ± 10% 38 130 µA VDD = 2.0 V 20 70 µA Supply current Note3 IDD2 HALT mode VDD = 3 V ± 10% 17 60 µA VDD = 2.0 V 8 25 µA IDD3 STOP mode 0.1 5 µA Note 1. µPD7554A only 2. For N-ch open-drain input/output selection 3. The current flowing in built-in pull-up and pull-down resistors is excluded. R = 240 kΩ ± 2% Operating mode

µPD7554A, 7554A(A) AC CHARACTERISTICS (T a = –10 to +70 °C, VDD = 2.0 to 3.3 V) Note1 Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Internal clock cycle time t CY Note2 13.4 200 µs P00 event input frequency f PO 0 150 kHz P00 input rise/fall time t POR, tPOF 0.2 µs P00 input high/low level tPOH, tPOL 3.3 µswidth SCK cycle time t KCY Input 13.4 µs Output 16.6 µs SCK high/low level width t KH, tKL Input 6.7 µs Output 8.3 µs SI setup time (to SCK ↑ )t SIK 500 ns SI hold time (to SCK ↑ )t KSI 500 ns SCK↓→ SO output delay time t KSO CL = 100 pF 3500 ns INT0 high/low level width t IOH, tIOL 50 µs RESET high/low level tRSH, tRSL 50 µs width Note 1. µPD7554A only 2. tCY = 2/f CC or 2/f C AC Timing Test Point (Except CL1 Input)

0.85 VDD

0.15 VDD

µPD7554A, 7554A(A) CHARACTERISTICS OF DATA MEMORY DATA RETENTION AT LOW SUPPLY VOLTAGE IN STOP MODE µPD7554A : T a = –10 to +70 °C µPD7554A(A) : T a = –40 to +85 °C Parameter Symbol Test Conditions MIN. TYP. MAX. Unit Data retention supply voltage V DDDR 2.0 6.0 V Data retention supply current I DDDR VDDDR = 2.0 V 0.1 5 µA Data retention high RESET VIHDR 0.9 VDDDR VDDDR +0.2 Vinput voltage RESET setup time t SRS 0 µs RESET hold time t HRS 0 µs Data Retention Timing VDD RESET STOP Instruction Execution STOP tSRS tHRS Data Retention Mode Operating Mode

1 VDDDR

2 VIH1

3 VIHDR

4 IL1

Caution In the data retention mode, every input must be below V DDDR.

µPD7554A, 7554A(A) Clock Timing 1/fP0 tPOL tPOH P00 Input tPOR tPOF 1/fC tCL tCH CL1 Input tCR tCF Serial Transfer Timing tKCY tKL tKH SCK tSIK tKSI tKSO SI SO Output Data Input Data

µPD7554A, 7554A(A) Test Input Timing tIOL tIOH INT0 RESET Input Timing tRSL tRSH RESET

µPD7554A, 7554A(A) 7. CHARACTERISTIC CURVES H H H t1 t2 CL1 t1>t2 : fC = 1 2t2 t1<t2 : fC = 1 2t1 1000 500 100 0123456 0123456 CL1 CL2 R 100 500 t1 t2 t1>t2 : fX = 1 2t2 t1<t2 : fX = 1 2t1 1000 500 100 0123456 : Ta = –10 to +70 °C : Ta = –40 to +85 °C fC vs. VDD Operating Guarantee Range Operating Guarantee Range Clock Input Frequency fC [kHz] Operating Guarantee Range Operating Guarantee Range External Resistor R [kΩ ] Supply Voltage VDD [V] R vs. VDD Operating Guarantee Range P00 Event Input Frequency fP0 [kHz] Supply Voltage VDD [V] fP0 vs. VDD Operating Guarantee Range Supply Voltage VDD [V] µ PD7554A PD7554A(A)µ : Ta = –10 to +70 °C : Ta = –40 to +85 °C µ PD7554A PD7554A(A) µ : Ta = –10 to +70 °C : Ta = –40 to +85 °C µ PD7554A PD7554A(A) µ : PD7554A : PD7554A(A) µ µ : PD7554A : PD7554A(A) µ µ : PD7554A : PD7554A(A) µ µ

µPD7554A, 7554A(A) H H fCC vs. VDD Characteristics Example (Reference Value) (Ta=25°C) 700 600 500 400 300 200 100 0 1234567 R=56kΩ R=100kΩ R=240kΩ Note1 Supply Voltage VDD [V] Clock Oscillation Frequency fCC [kHz] fCC vs. Ta Characteristics Example (Reference Value) 700 600 500 400 300 200 100 0 –40 0 25 50 70 85 Note1 Ambient Temperature Ta [°C] Clock Oscillation Frequency fCC [kHz] Note2 R=56kΩ , VDD=5.0V R=100kΩ , VDD=3.0V R=240kΩ , VDD=2.0V –25 –10 75 Note 1. µPD7554A only 2. µPD7554A only operates within this range

µPD7554A, 7554A(A) H VDD=5.0V VDD=2.5V VDD=2.0V fCC vs. R Characteristics Example (Reference Value) (Ta=25°C) Clock Oscillation Frequency fCC [kHz] 1000 800 600 400 200 Note External Resistor Value [kΩ ] 10 30 50 70 90 200 400 600 800 1000 CL1 CL2 R 100 500 IDD vs. VDD Characteristic Example (Reference Value) 0123456 R = 56 kΩ Operation R = 56 kΩ , HALTNote R = 100 kΩ Operation R = 150 kΩ Operation R = 100 kΩ , HALTNote R = 150 kΩ , HALTNote Supply Current IDD (A )µ Supply Voltage VDD [V] 1000 (Ta = 25 °C) Note µPD7554A only

µPD7554A, 7554A(A) Caution The absolute maximum rating is 30 mA per pin. Caution The absolute maximum rating is 15 mA per pin. Caution The absolute maximum rating is -5 mA per pin. Note µPD7554A only 0123456 VDD = 2.5 VNote (Ta = 25 °C) 0123456 VDD = 2.5 VNote (Ta = 25 °C) 0123456 VDD = 2.5 VNote (Ta = 25 °C) VDD = 3 V VDD = 3 V VDD = 5 V VDD = 5 V VDD = 3 V VDD = 5 V IOL vs. VOL Characteristic Example (Port 8) (Reference Value) Output Current Low IOL [mA] Output Voltage Low VOL [V] IOL vs. VOL Characteristic Example (Port 10, 11) (Reference Value) Output Current Low IOL [mA] Output Voltage Low VOL [V] IOH vs. VOH Characteristic Example (Reference Value) Output Current High IOH [mA] VDD – VOH [V]

µPD7554A, 7554A(A) 8. µPD7554A APPLIED CIRCUITS (1) Tape counter (VTR, deck) PCL SCK SO SI PD75008µ PD75108µ CL1 SCK SI SO RESET P00/INT0 P113 P100 ~ P112P83P82P81P80 PA80Cµ 7-Segment LED UP/DOWN Signal Mechanical Control Microcomputer Tape Counter Microcomputer PD7554A µ Count Pulse Driver etc. (2) Remote control reception + key entry + LED display PD7554Aµ PCL SCK SO SI PD75008µ PD75108µ PCL SCK SO SI P110 P111 P112 CMOS Output P113 RESET P80 P81 P82 P83 P100 P101 P102 P103 P00 PC2800AHA(MS) etc. µ LED PA80CµDriver (Chip Selector Transfer Request)Open-Drain Output On-Chip Pull-Up Resistor Input Key Input 4 × 4 Master Microcomputer etc. Remote Control Signal Amplifier Circuit

µPD7554A, 7554A(A) 9. PACKAGE INFORMATION DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (1/2) Caution Dimentions of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (1/2).

µPD7554A, 7554A(A) DRAWINGS OF MASS-PRODUCTION PRODUCT PACKAGES (2/2)

20 PIN PLASTIC SOP (300 mil)

A B C E F G H I J 13.00 MAX. 1.27 (T.P.) 1.8 MAX. 1.55 7.7±0.3 0.78 MAX. 0.12 1.1 5.6 M 0.1±0.1 N 0.512 MAX. 0.031 MAX. 0.004±0.004 0.071 MAX. 0.061 0.303±0.012 0.220 0.043 0.005 0.050 (T.P.) P20GM-50-300B, C-4 P3 ° 3°+7° NOTE Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition. D 0.40 0.016+0.10 –0.05 K 0.20 0.008+0.10 –0.05 L 0.6±0.2 0.024 0.10 –3° +7° –3° 0.004 +0.008 –0.009 +0.004 –0.002 +0.004 –0.003 A C D G P detail of lead end F E B H I L K M J N M 11 0 1120 Caution Dimentions and materials of ES products are different from those of mass-production products. Refer to DRAWINGS OF ES PRODUCT PACKAGES (2/2). H

µPD7554A, 7554A(A) DRAWINGS OF ES PRODUCT PACKAGES (1/2)

20 PIN SHRINK DIP FOR ES (REFERENCE) (UNIT: mm)

µPD7554A, 7554A(A) DRAWINGS OF ES PRODUCT PACKAGES (2/2)

20 PIN CERAMIC SOP FOR ES (REFERENCE) (UNIT: mm)

µPD7554A, 7554A(A) 10. RECOMMENDED PACKAGING PATTERN OF PLASTIC SOP (REFERENCE) (UNIT: mm) 7.62 1.270.76 0.51 1.27

• This recommended pattern conforms to the General Rules for Integrated Citrcuit Outer Shape (IC-74-2) specified by the Electronic Industries Association of Japan (EIAJ).
• The above pattern dimensions are applicable to all the products designated as EIAJ flat DIP (mini flat) of “Form A 300 mil type”.
• If there is any possibility of causing a solder bridge, adjust the width (0.76) of each pad while maintaining the same length (1.27).

µPD7554A, 7554A(A) 11. RECOMMENDED SOLDERING CONDITIONS Solder µPD7554A on the following recommended conditions. For details of recommended soldering conditions, refer to the information document “Semiconductor device mounting technology manual” (IEI-1207). For details on the soldering method and soldering conditions other than the recommended conditions, call the NEC salesman. Table 11-1 Surface Mounting Type Soldering Conditions µPD7554AG-××× : 20-pin plastic SOP (300 mil) µPD7554AG(A)- ××× : 20-pin plastic SOP (300 mil) Soldering Method Soldering Conditions Recommended Condition Symbol Infrared reflow IR30-00-1 VPS VP15-00-1 Wave soldering WS60-00-1 Pin part heating Pin temperature: 300 °C or below, Duration: 3 sec. max. (per device side) –– Caution Use of more than one soldering method should be avoided (except in the case of pin part heating). Table 11-2 Insertion Type Soldering Conditions µPD7554ACS-××× : 20-pin plastic shrink DIP (300 mil) µPD7554ACS(A)- ××× : 20-pin plastic shrink DIP (300 mil) Soldering Method Soldering Conditions Wave soldering Solder bath temperatures: 260 °C or below, Duration: 10 sec. max. (pin only) Pin part heating Pin temperature: 300 °C or below, Duration: 3 sec. max. (Per pin) Caution Ensure that the application of wave soldering is limited to the pins and no solder touches the main unit directly. H Package peak temperature: 230 °C, Duration: 30 sec. max. (at 210 °C or above), Number of times: Once Package peak temperature: 215 °C, Duration: 40 sec. max. (at 200 °C or above), Number of times: Once Solder bath temperature: 260 °C or below, Duration: 10 sec. max., Number of times: once, Preparatory heating tempererature: 120 °C max. (Package surface temperature)

µPD7554A, 7554A(A) Product Name µPD7554 µPD75P54 µPD7554A µPD7554A(A) µPD7564 µPD75P64 µPD7564A µPD7564A(A) Item RC 4 µs/500 kHz – Instruction cycle/Outside 2.86 µs/700 kHz – system clock (5 V) Ceramic – 2.86 µs/700 kHz Instruction set47 types (SET B) ROM1024 × 8 RAM64 × 4 Total 16 15 Port 0P00-P03 Port 8 P80-P82, P83 (CL2) P80-P82 I/O Ports Withstand voltage 12 V 9 V 12 V 9 V Port 10 and 11 P100-P103, P110-P113 Withstand voltage 12 V 9 V 12 V 9 V Timer/Event Counter8 bits Serial Interface4 channels Package20-pin plastic shrink DIP 20-pin plastic SOP ★APPENDIX A. COMPARISON BETWEEN SERIES PRODUCTS FUNCTIONS

µPD7554A, 7554A(A) APPENDIX B. DEVELOPMENT TOOLS The following development tools are available for developing systems that use µPD7554A. Language Processor Host Machine OS Supply Medium Ordering Code (Product Name) MS-DOS™ 3.5-inch 2HD µS5A13AS7554 PC-9800 series (Ver.3.10 to Ver.5.00ANote) 5-inch 2HD µS5A10AS7554 IBM PC/AT™ PC DOS™ 5-inch 2HC µS7B10AS7554 (Ver. 3.1) PROM Write Tools Note A task swap function is provided in Ver. 5.00/5.00A, but the task swap function cannot be used with this software. Remark Operation of the assembler and PG-1500 controller is only guaranteed on the host machines and OSs shown above. µPD7550/7560 series absolute assembler PROM programmer which allows programming of single-chip microcomputer with typical PROM of 256K to 4M bits by stand-alone or from a host machine by connecting the accessory board and optional programmer adapter. µPD75P54/75P64 PROM programmer adapter. Used by connecting it to the PG-1500. Connects the PG-1500 and host machine by serial and parallel interface and controls the PG-1500 on the host machine. Hardware PG-1500 PA-75P54CS Ordering Code Host Machine OS Supply Medium (Product Name) MS-DOS 3.5-inch 2HD µS5A13PG1500 PC-9800 series (Ver.3.10 to Ver.5.00ANote) IBM PC/AT PC DOS 5-inch 2HC µS7B10PG1500(Ver.3.1) 5-inch 2HD µS5A10PG1500 Software PG-1500 controller

µPD7554A, 7554A(A) Debugging Tools Note A task swap function is provided in Ver. 5.00/5.00A, but the task swap function cannot be used with this software. Caution It is not possible to internally mount a pull-up resistor in a port in the EVAKIT-7500B. When evaluating, arrange to have a pull-up resistor mounted in the user system. Remark Operation of the assembler and PG-1500 controller is only guaranteed on the host machines and OSs shown above. EVAKIT-7500B is an evaluation board that can be used for µPD7500 series models. For µPD7544A, EVAKIT-7500B and option board EV-7554A are combined and used for system development. EVAKIT-7500B can operate alone. EVAKIT-7500B has a built-in serial interface on the board, so it enables debugging when it is connected to a TTY, TYPUTER, or RS- 232-C console. EVAKIT-7500B works as is a real-time tracer and traces state of the program counter and output port in real time. EVAKIT-7500B has a built-in PROM writer and improves debugging efficiency considerably. EV-7554A is an adapter board which is connected to EVAKIT-7500B and evaluates µPD7554A. SE-7554A is a simulation board that has the programs developed by EVAKIT-7500B. SE-7554A evaluates a system in place of µPD7554A. EVAKIT-7500 Control Program connects EVAKIT-7500B and the host machine with RC-232-C and controls EVAKIT-7500B on the host machine. Hardware EV-7554A SE-7554A EVAKIT-7500B Software Ordering Code Host Machine OS Supply Medium (Product Name) PC-9800 MS-DOS 3.5-inch 2HD µS5A13EV7500-P01 series (Ver.3.10 to Ver.5.00ANote) IBM PC PC DOS 5-inch 2HC µS7B11EV7500-P01series (Ver.3.1) 5-inch 2HD µS5A10EV7500-P01 EVAKIT-7500 control program (EVAKIT controller) H

µPD7554A, 7554A(A) APPENDIX C. RELATED DOCUMENTS DOCUMENT RELATED TO DEVICE Document Name Document No. User's Manual IEU-1111D µPD7500-series Selection Guide IF-1027G DOCUMENT RELATED TO DEVELOPMENT TOOL Document Name Document No. EVAKIT-7500B User's Manual EEU-1017C Hardware EV-7554A User's Manual EEU-1034A PG-1500 User's Manual EEU-1335B µPD7550, 7560-series Absolute Assembler User's Manual EEM-1006 Software EVAKIT-7500 Control Program User's Manual MS-DOS base EEM-1356 PC DOS base EEM-1049 PG-1500 Controller User's Manual EEU-1291B OTHER RELATED DOCUMENT Document Name Document No. Package Manual IEI-1213 Semiconductor Device Mounting Technology Manual IEI-1207 Quality Grade on NEC Semiconductor Devices IEI-1209A NEC Semiconductor Device Reliability/Quality Control System IEI-1203A Static Electricity Discharge (ESD) Test IEI-1201 Semiconductor Device Quality Guarantee Guide MEI-1202 Microcomputer-Related Product Guide-Third Party Product Note Remark These documents above are subject to change without notice. Be sure to use the latest document for designing. Note To be published. H

µPD7554A, 7554A(A) [MEMO]

µPD7554A, 7554A(A) NOTES FOR CMOS DEVICES

1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS

Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.

2 HANDLING OF UNUSED INPUT PINS FOR CMOS

Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to V DD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.

3 STATUS BEFORE INITIALIZATION OF MOS DEVICES

Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immedi- ately after power-on for devices having reset function.

µPD7554A, 7554A(A) M4 92.6 [MEMO] MS-DOS is a trademark of MicroSoft Corporation. PC DOS and PC/AT are trademarks of IBM Corporation. No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. The devices listed in this document are not suitable for use in aerospace equipment, submarine cables, nuclear reactor control systems and life support systems. If customers intend to use NEC devices for above applications or they intend to use "Standard" quality grade NEC devices for applications not intended by NEC, please contact our sales people in advance. Application examples recommended by NEC Corporation Standard : Computer, Office equipment, Communication equipment, Test and Measurement equipment, Machine tools, Industrial robots, Audio and Visual equipment, Other consumer products, etc. Special : Automotive and Transportation equipment, Traffic control systems, Antidisaster systems, Anticrime systems, etc. The application circuits and their parameters are for references only and are not intended for use in actual design-in's.