74LS75N

SN54LS75 MOTOROLA | Alldatasheet

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Technical content

NOTES: tn = bit time before enable negative-going transition tn+1 = bit time after enable negative-going transition 5-75 FAST AND LS TTL DATA 4-BIT D LATCH The TTL/MSI SN54/74LS75 and SN54/74LS77 are latches used as tem- porary storage for binary information between processing units and input/out- put or indicator units. Information present at a data (D) input is transferred to the Q output when the Enable is HIGH and the Q output will follow the data input as long as the Enable remains HIGH. When the Enable goes LOW, the information (that was present at the data input at the time the transition oc- curred) is retained at the Q output until the Enable is permitted to go HIGH. The SN54 /74LS75 features complementary Q and Q output from a 4-bit latch and is available in the 16-pin packages. For higher component density applications the SN54/74LS77 4-bit latch is available in the 14-pin package with Q outputs omitted. 14 13 12 11 10 9 1 2 3 4 5 6 7 16 15 CONNECTION DIAGRAMS DIP (TOP VIEW) SN54/74LS75 14 13 12 11 10 9 1 2 3 4 5 6 SN54/74LS77 Q 0 Q 0 Q 1 Q 1 E0–1 GND Q 2Q 2 Q 3 D 0 D 1 E2–3 VCC D 2 D 3 Q 3 Q 0 Q 1 E0–1 GND NC Q 2 Q 3 D 0 D 1 E2–3 VCC D 2 D 3 NC PIN NAMES LOADING (Note a) HIGH LOW D 1–D 4 E0–1 E2–3 Q 1–Q 4 Q 1–Q 4 Data Inputs Enable Input Latches 0, 1 Enable Input Latches 2, 3 Latch Outputs (Note b) Complimentary Latch Outputs (Note b) 0.5 U.L. 2.0 U.L. 2.0 U.L. 10 U.L. 10 U.L. 0.25 U.L. 1.0 U.L. 1.0 U.L. 5 (2.5) U.L. 5 (2.5) U.L. NOTES: a) 1 Unit Load (U.L.) = 40 µA HIGH. Temperature Ranges. TRUTH TABLE (Each latch) tn tn+1 D H L Q H L SN54/74LS75 SN54/74LS77 4-BIT D LATCH LOW POWER SCHOTTKY J SUFFIX CERAMIC CASE 620-09 N SUFFIX PLASTIC CASE 648-08

ORDERING INFORMATION

VCC = PIN 5 GND = PIN 12 2 3 6 7 16 1 15 14 10 11 9 8 D 0 D 1 D 2 D 3 E0–1 E2–3 Q 0 Q 1 Q 2 Q 3Q 0 Q 1 Q 2 Q 3 SN54/74LS75 VCC = PIN 4 GND = PIN 11 NC = PIN 7, 10 1 2 5 6 14 13 9 8 D 0 D 1 D 2 D 3 E0–1 E2–3 Q 0 Q 3Q 1 Q 2 SN54/74LS77 DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 V Guaranteed Input LOW Voltage for All InputsVIL Input LOW Voltage 74 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth TableVOH Output HIGH Voltage 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VOL Output LOW Voltage 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current D Input E Input µA VCC = MAX, VIN = 2.7 V IIH Input HIGH Current D Input E Input 0.1 0.4 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current D Input E Input –0.4 –1.6 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current 12 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Limits Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions tPLH tPHL Propagation Delay, Data to Q 15 9.0 17 ns VCC = 5.0 V C L = 15 pF tPLH tPHL Propagation Delay, Data to Q 12 7.0 15 ns VCC = 5.0 V C L = 15 pFtPLH tPHL Propagation Delay, Enable to Q 15 25 ns VCC = 5.0 V C L = 15 pF tPLH tPHL Propagation Delay, Enable to Q 16 7.0 15 ns

DC CHARACTERISTICS OVER OPERATING TEMPERATURE RANGE (unless otherwise specified) Symbol Parameter Limits Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions VIH Input HIGH Voltage 2.0 V Guaranteed Input HIGH Voltage for All Inputs VIL Input LOW Voltage 54 0.7 V Guaranteed Input LOW Voltage for All InputsVIL Input LOW Voltage 74 0.8 V Guaranteed Input LOW Voltage for All Inputs VIK Input Clamp Diode Voltage –0.65 –1.5 V VCC = MIN, IIN = –18 mA VOH Output HIGH Voltage 54 2.5 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth TableVOH Output HIGH Voltage 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH or VIL per Truth Table VOL Output LOW Voltage 54, 74 0.25 0.4 V IOL = 4.0 mA VCC = VCC MIN, VIN = VIL or VIH per Truth Table VOL Output LOW Voltage 74 0.35 0.5 V IOL = 8.0 mA VIN = VIL or VIH per Truth Table IIH Input HIGH Current D Input E Input µA VCC = MAX, VIN = 2.7 V IIH Input HIGH Current D Input E Input 0.1 0.4 mA VCC = MAX, VIN = 7.0 V IIL Input LOW Current D Input E Input –0.4 –1.6 mA VCC = MAX, VIN = 0.4 V IOS Short Circuit Current (Note 1) –20 –100 mA VCC = MAX ICC Power Supply Current 13 mA VCC = MAX Note 1: Not more than one output should be shorted at a time, nor for more than 1 second. AC CHARACTERISTICS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Limits Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions tPLH tPHL Propagation Delay, Data to Q 11 9.0 17 ns VCC = 5.0 V C L = 15 pFtPLH tPHL Propagation Delay, Enable to Q 10 18 ns VCC = 5.0 V C L = 15 pF

SN54/74LS75 /C0068 SN54/74LS77 LOGIC DIAGRAM DATA ENABLE TO OTHER LATCH Q (SN54/74LS75 ONLY) Q GUARANTEED OPERATING RANGES Symbol Parameter Min Typ Max Unit VCC Supply Voltage 54 4.5 4.75 5.0 5.0 5.5 5.25 V TA Operating Ambient T emperature Range 54 –55 125 IOH Output Current — High 54, 74 –0.4 mA IOL Output Current — Low 54 4.0 8.0 mA AC SETUP REQUIREMENTS (TA = 25°C, VCC = 5.0 V) Symbol Parameter Limits Unit Test ConditionsSymbol Parameter Min Typ Max Unit Test Conditions tW Enable Pulse Width High 20 ns VCC = 5.0 Vts Setup Time 20 ns VCC = 5.0 V th Hold Time 0 ns CC = 5.0 V AC WAVEFORMS D E Q Q 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V 1.3 V1.3 V thts tPLH tPLH tPHL tPHL tPLHtPHL tPHL tPLH DEFINITION OF TERMS SETUP TIME (ts) — is defined as the minimum time required for the correct logic level to be present at the logic input prior to the clock transition from HIGH-to-LOW in order to be recognized and transferred to the outputs. HOLD TIME (th) — is defined as the minimum time following the clock transition from HIGH-to-LOW that the logic level must be maintained at the input in order to ensure continued recognition. A negative HOLD TIME indicates that the correct logic level may be released prior to the clock transition from HIGH-to-LOW and still be recognized.