74LS783

SN74LS783 MOTOROLA | Alldatasheet

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SYNCHRONOUS ADDRESS MULTIPLEXER MOCHPLOXER The SN74LS783/MC6883 brings together the MC6809E (MPU), the MC6847 (Color Video Display Generator) and dy- namic RAM to form a highly effective, compact and cost ef- fective computer and display system. LOW POWER SCHOTTKY © MC6809E, MC6800, MC6801E, MC68000 and MC6847 (VDG) Compatible @ Transparent MPU/VOG/Refresh @ RAM size — 4K, 8K, 16K, 32K or 64K Bytes (Dynamic or Static) , © Addressing Range — 96K Bytes re N SUFFIX © Single Crystal Provides All Timing 40 Ye PLASTIC PACKAGE © Register Programmable: ; cASE7N VDG Addressing Modes VOG Offset (0 to 64K) RAM Size Page Switch " Trt MPU Rate (Address Dependent or Independent) ey rare ate (Address Dependent or Independent! t CERAM a KAGE © System “Device Selects” Decoded ‘On Chip’ CASE 734 @ Timing is Optimized for Standard Dynamic RAMs © +5.0 V Only Operation izati AM te © Easy Synchronization of Multiple S. ‘Systems pin ASSIQNMENT ‘@ DMA Mode tdan—— vecka 40 SYSTEM BLOCK DIAGRAM zea aizfa 39 3myas AIST 38 Device Sac aca Aah 97 fi 510s, A159) 36 [ swrasiae | ve Option 6CJoscour 27 35 TRAST) Lif pewweeee 7 ven ze 34 on {on H 8 C{pao 25 33 | | a ; se H ons za 32 sam Fs 4 aw fs sesame y | H tas 22) 30 ‘~+——] aLs[on Nooo | 12cjRass zi 9 to ole—___] oxy tx H i 300 205 28 Lod Se a baat woe sof 27 oe wy eris77y [ciara 16 CJao sh 2 enna cx a a waa An 2 on fed | p---£----5 10 Jaz asf 23 {{ couor | | 19 jas as 22 [Bxraisza] | | On | 0 | 20Ctena = aafz1 tot 4-630

SN74LS783°MC6883 MAXIMUM RATINGS (Ta = 25°C unless otherwise noted.) Power Supply Voltage | Voc _|-o.st0 +7.0| vde_| Input Voltage (Except Oscin) | v_| -ostor0 | vae_| Input Current (Except Osein) | 4 __[-s0t0+s0[ ma _| Output Voltage | Vo [-osto +70] Vdc _| Operating Ambient Temperature Range | Ta | oto +70 | *c | [input Vottage Ossin | Moen | -0.5 9 Voc] vee | [input Current Oscin | NO tein [0.8 to +8.0] ma] RECOMMENDED OPERATING CONDITIONS Power Supply Vohage [Voc [4750526 | vac _| Operating Abies Yorpersure Range DC CHARACTERISTICS (Uniess otherwise noted specifications epply over recommended power supply and, temperature ranges.) Taput Volage — Woh Logie State [vw [20 | - | - | v_| Input Clamp Voltage (Vcc = Min, lin = -18 mA) All Inputs Except Oscin Input Current — High Logic State at Max input Voltage eA (Vcc = Max. Vin = 5.28 V) VCik Input 200 (Voc = Max. Vin = 5.25 V) DAO Input 100 (Voc = Max, Vin = 5.25 V) Osegut Input 250 (Voc = Max. Vin = 7.0 V) All Other Inputs Except Oscin 100 Input Current High Logic Stete A (Voc = Max, Vin = 2.7 V) All Inputs Except VCIk, Oscin* Input Current — Low Logic State te (Voc = Mex, Vin = 0.4 V) DAO Input (Voc = Max, Vin = 0.4 V) VCIk Input (VCC = Max, Vin = 0.4 V, Oscin = Gnd) Oscout Input (VEC _= Max, Vin = 0.4 V) All Other Inputs Except Oscin Output Voltage — High Logic State _ (Vcc = Min, Ioy = - 1.0 mA) RASO, RAST, CAS, WE Vouic) 3.0 (Vcc = Min. Igy = -0.2 mA) E, O Vouie) |Yec - 0.75 (cc = Min, Io = ~0.2 mA) All Other Outputs Vou 27 ‘Output Voltage — Low Logic State a (Vcc = Min, Io, = 8.0 mA) RASO, RAST, CAS, WE Vouc) 05 (Vcc = Min, lo, = 4.0 mA) E, O Outputs VoLie) 08 (Vcc = Min, lo, = 0.8 mA) VCik Output Vou) oe (cc = Min, Io. = 4.0 mA) All Other Outputs Vo 05 Power Supply Current | icc [ — [eo [230 | ma | Output Short-Circuit Current [ tos [ao [| — [2s [ma] “Including Oscout (when Oxcin i grounded). 4-631 .

SN74LS783°MC6883 AC CHARACTERISTICS (4.75 V<Vcc<5.25 V and 0<TA70°C, unless otherwise noted). Propagation Delay Times {See Circuit in Figure 8) Oscillator-in “%_ to Oscillator-Outs"| tg(OL-OH) Oscillator-in #° to Oscillator-Out® | ta(OH-OL) (Cl = 195 pF) AO thru A1S to 20, 21, 22 thru 27 taiA-2) (Ct = 30 pF) AO thru A15, RW to SO, $1, $3 ta(a-S) (Cl = 95 pF) Oscillator-Out “& to RASO + *a(OL-ROH)| {CL = 95 pF) Oscillator-Out “* to RASO ® ta(OL-ROL) - (CL = 95 pF) Oscillator-Out “& to RAST ta(Ou-R1H)| (CL = 95 pF) Oscillator-Out “* to RAST © t4(OL-RIL) (CL = 195 pF) Oscillator-Out © to CAS tg (OL-cH) (CL = 195 pF) Oscillator-Out © to CAS tg(OL-Ct) (CL = 195 pF) Oscillator-Out % to WE tg(OL-wH) (CL = 195 pF) Oscillator-Out ® to WE t3(0L- Wu {Cl = 100 pF) Oscillator-Out % to E ta(OL-EH) {CL = 100 pF) Oscillator-Out to E © t4(0L-£U (CL = 100 pF) Oscillator-Out % to 0 tg(OL-aH) {CL,= 100 pF) Oscillator-Out © to Q-% t(OL-1) (CL = 30 pF) Oscillator-Out to VCIk + ta(OH-VH) 50 {CL = 30 pF) Oscillator-Out « to VCIk tg(OH-VU 65 {CL = 195 pF) Oscillator-Out % to Row Address ta(OL-AR) {CL = 195 pF) Oscillator-Out * to Column Address ta(OL-AC) {CL = 15 pF) Oscillator-Out *X to DAO _# Earliest(1) ta(OL-DH) 15 = (CL = 15 pF) Oscillator-Out X to DAO -# Latest(1) ta(OL-DH +15 - (Cy 95 pF on RAS. Cy ~ 195 pFon CAS) CAS W to FAS | taycr-nmy| — | 208 [| — | Setup Time for AO thru A15, RW Rate = 16 Rate = ~ 8 Hold Time for AO thru A15, RW Rate = -16 Rate = + 8 LwidthorStow2 tts) | 20 Tso Teo [Tas | ‘Notes: 1. When using the SAM with an MC5B47, the rising edge of DAO is confined within the range shown in the timing diagrams (unless the synchronizing process is incomplete.) The synchronization process requires 8 maximum of 32 cycles of Oscout for completion 2. {WLIHS) wider than 6.0 us may yield more then sequential refresh addresses FIGURE 1 — PROPAGATION DELAY TIMES VERSUS LOAD CAPACITANCE oT] ] LIT] zn 2 1] [oom TT PTT fat Lj er . a Lo ann LA 3,77 fom? TPP ee | ea si-t TT rrrrr re | ee ° 0 100 200 x00 Cr) (1, LOAD CAPACITANCE ip 4-632

SN74LS783¢MC6883 PIN DESCRIPTION TABLE [Name [mo [OC unetion Apply + 5 volts + 5%. SAM draws less than 230 mA. Return Ground for +5 voits. ANS 36 | Most Significant Bit ats 37 AN3 38 | MPU address bits AO-A15. These 16 signals come directly from the MPU and are used to Anz 39 | directly address up to 64K memory locations or to indirectly address up to 96K memory an 1 | locations. (See pages 17 and 18 for memory maps). Each input is approximately equivalent Ato 2 | toone low power Schottky load. a9 3 a8 4 , a7 24 AB 23 AS 2 Aa 21 a3 19 a2 18 Al 7 A0 16_| Least Significant Bit MPU READ or WRITE. This signal comes directly from the MPU and is used to enable writing to the SAM control register, dynamic RAM (via WE), and to enable device select #0. [[osein [5 | Apply 1431818" Mie crystal and 26-90 pF wrimmer to ground. See page 2 8 | Display Address DAO. The primary function of this pin is to Input the least significant bit of @ 16-bit video display address. The more significant 15-bits are outputs from an internal 15-bit counter which is clocked by DAO. The secondary function of this pin is to indirectly input the logic level of the VOG “FS” (field synchronization pulse) for vertical video address updating. 9 | Horizontal Synchronization. The primary function of this pin is to detect the falling edge of VDG "HS" pulse in order to initiate eight dynamic RAM refresh cycles. The secondary function is to reset up to 4 least significant bits of the internal video address counter. 7 | VDG Clock. The primary function of this pin is to output a 3.579545 MHz square wave** to the VDG "Cik” pin. The secondary function resets the SAM when this VCIk pin is pulled to logic "0" level, acting a8 an Input | Oscour_[ 6 | Apply 1.5 kf resistor to 14.31818* MHz crystal and 33 pF capacitor to ground. See page 12._| Most Significant Bit (Device Select Bits). The binary value of S2, S1, SO selects one of eight “chunks” of MPU address space (numbers 0 through 7). Varying in length, these “chunks” provide efficient memory mapping for ROMs, RAMs, Input/Output devices, and MPU Vectors. (Requires 74LS 138-type demultiplexer). Least Significant Bit. E (Enable Clock) “E” and “Q” are 90° out of phase and are both used as MPU clocks for the MC8809E. For the MC6800 and MC6BO1E, only "E” is used. “E” is also used for many MC6B00 peripheral chips. Q (Quadrature Clock). mt 35 | Most Significant Bit zt 34 | First, the least significant address bits from the MPU or “VDG"" are presented to Z0-Z5 (4K zst 33. | x 1 RAMs) or Z0-Z6 (16K x 1 RAMs) or Z0-Z7 (64K x 1 RAMs). Next, the most significant zat 32 | address bits from the MPU or “VDG"" are presented to Z0-Z5 (4K x 1 RAMs) or 20-26 z3t 31 | (16K x 1 RAMs) or ZO ~27 (64K x 1 RAMs). Note that for 4K x 1 and 16K x 1 RAMS, 27 (Pin zt 30 | 35) is not needed for address information. Therefore, Pin 35 is used for a second row zit 29 | address select which is labeled (RAS1). Zot 28 _| Least Significant Bit. ‘RASit 35 | Row Address Strobe One. This pulse strobes the least significant 6,7 or 8 address bits into dynamic RAMs in Bank #1. | RASOr 12. | Row Address Strobe Zero. This pulse strobes the least significant 6,7 or 8 address bits into | dynamic RAMS in Bank #0. Cast 11 | Column Address Strobe. This pulse strobes the most significant 6,7 or 8 address bits into dynamic RAMs. Wer 10_| Write Enable. When low, this pulse enables the MPU to write into dynamic RAM. 114.31818 MHz is 4 times 3.579545 MHz television color subcarrier. Other frequencies may be used. (See page 12) ‘*When VOG and SAM are not yet synchronized the “square wava'” will stretch (see page 10.) 1 ue to fat transitions, ferrite beads in saren with these outputs may be necessary to avoid high frequency (= 60 ME) resonances. | 4-633

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4 Refresh Counter cp] hatvean sosc- 16 U

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SN74LS783¢MC6883 SAM BLOCK DIAGRAM DESCRIPTION MPU Addresses (AO - A15): These 16 signals come directly from the MPU and are used to directly address up to 64K memory locations (K = 1024) or to indirectly address up to 96K memory locations, by using a paging bit “P” (see pages 17 and 18 for memory maps.) Each input is approximately equivalent to one low power Schottky load. VDG Address Counter (B0 - B15): These 16 signals are derived from one input (DAQ) which is the least significant bit of the VDG address. Most of the counter is simply binary. However, to duplicate the various addressing modes of the MC6847 VDG, ADDRESS MODIFIER logic is used. Selected by three VDG mode bits (V2, V1, and V0) from the SAM CONTROL REGISTER, eight address modifications are obtained as shown in Figure 5. Also, notice that bits B9-B15 may be loaded from bits FO-F6 from the CONTROL REGISTER. This allows the starting address of the VDG display to be offset (in %K increments) from $0000 to $FFFFt .B9-B15 are loaded when a VERTICAL PRE-LOAD(VP) pulse is generated. VP goes active (high) when HS from the VDG rises if DAO is high (or a high impedance.) This condition should occur only while the TV electron beam is in vertical blanking and is simply implemented by connecting FS and MS together on the MC6847. The VP pulse also clears bits B1 - B8. Finally, a HORIZONTAL RESET (HR) pulse may also affect the counter by clearing bits B1 - B3 or B1- B4 when HS from the VDG is LOW (see Figure 5.) The HR pulse should occur only while the TV electron beam is in horizontal blanking. In summary, DAO clocks the VDG ADDRESS COUNTER; HR initializes the horizontal portion and VP initializes the vertical portion of the VDG ADDRESS COUNTER. REFresh Address Counter (CO - C6): A seven bit binary counter with outputs labeled CO - C6 supplies bursts of eight” sequential addresses triggered by a HS high to low transition. Thus, while the TV electron beam is in horizontal blanking, eight sequential addresses are accessed. Likewise, the next eight addresses are accessed during the next horizontal blanking period, etc. In this manner, all 128 addresses are refreshed in less than 1.1 milliseconds. Address Multiplexer: Occupying a large portion of the block diagram in Figure 4, is the address multiplexer which outputs bits 20-27 (as addresses to dynamic RAM’s.) Inputs to the address multiplexer include the VDG address (BO - 815) the REFresh address (CO- C6) and the MPU address (A0 - A15) or (AO - A14 plus one paging bit “P”’.) The paging bit “P” is one bit in the SAM CONTROL REGISTER that is used in place of A15 when memory map TYpe #0 is selected (via the SAM CONTROL REGISTER “TY” bit.) Figure 6 shows which inputs are routed to Z0 - 27 and when the routing occurs relative to one SAM machine cycle. Notice that 27 and RAS1 share the same pin. 27 is selected if “M1” in the SAM CONTROL REGISTER |S HIGH (Memory size = 64K.) Address Decode: At the top left of Figure 4, is the Address Decode block. Outputs S2, 1, and SO form a three bit encoded binary word(S). Thus S may be one of eight values (0 through 7) with each value representing a different range of MPU addresses. (To enable peripheral ROM’s or I/O, decode the S2, S1, and SO bits into eight seperate signals by using a 74LS138, 74LS155 or 74LS156. Notice that S2, S1, and SO are not gated with any timing signals such as E or Q.) Along with the A5 - A15 inputs is the MEMORY MAP TYpe bit (TY.) This bit is soft-programmable (as are all 16 bits in the SAM CONTROL REGISTER, and selects one of two memory maps. Memory map #0 is intended to be used in systems that are primarily ROM based. Whereas, memory map #1 is intended for a primarily RAM based system with 64K contiguous RAM locations (minus 256 locations.) The various meanings of S2, S1, SO are tabulated in Figure 16 (page 19) and again on pages 17 and 18. In addition to $2, $1, and SO outputs is a decode of $FFCO through $FFDF which, when gated with E and RM, results in the write strobe for the SAM CONTROL REGISTER. SAM Control Register As shown in Figure 4, the CONTROL REGISTER has 16 “outputs”: VDG Addressing Modes: V2, V1, VO MPU Rate: R1, RO VDG Address OFFset: F6, F5, F4, F3, F2,F1,F0 | Memory Size (RAM) M1, Mo 32K Page Switch Pp Memory Map TYpe: v When the SAM is reset (see page 10,) all 16 bits are cleared. To set any one of these 16 bits, the MPU simply writes to 2 unique** odd address (within $FFC1 through $FFDF.) To clear any one of these 16 bits, the MPU * it FS is held low longer than 8 us, then the number of sequential addresses in one ratresh “BURST” is proportional to the time interval during which HE ia low. ** See pages 17 or 18 for specific addresses. + In this document, the "S'" aymbol always preceods hexidecimal characters, 4-637

Changing the MPU Rate (by changing SAM control register bits RO, R1). Two bits in the SAM control register determine the period of both “E” and "Q’ MPU clocks. Three rate modes are implemented as follows: SLOW © 0 | The frequency of “E” (and “Q") is crystal = 16. This rate mode is automatically selected when the SAM is reset. Note that system timing is least critical in this “SLOW” rate mode. AD. 01 _| The frequency of “E” (and “Q") is either f crystal = 16 orf crystal = 8, depending on the address (Address Dependent) | the MPU is presenting. FAST 1X | The frequency of “E” (and “Q”) is f crystal = 8 This is accomplished by stealing the time that is normally used tor VOG/REFRESH, and using this time for the MPU. Note: Neither VOG display nor dynamic RAM refresh are available in the “FAST” rate mode. (Both are available in SLOW and A.D. rate modes). When changing between any two of the three rate modes, the following procedures must be followed to ensure that MPU timing specifications are met: SLOW Ss hee eset Tis rect patis_ AD. ‘Sequence #1 not allowed except by | FAST Wa (See Below) \\e pi, herdovore renal ‘Set RO, then CLEAR R1 May be ANY address from $0000 to $7FFF SEQUENCE #1;

21.00 BRNOO

87 FF D6 STA #SFFOS... Clears bit RO *Note: “TST” instruction affects MCBBO9E condition code register . Changing the MPU Rate (in Address Dependent Mode) When the SAM control register bits “R1", and “RO” are programmed to "0" and “1”, respectively, the Address Dependent Rate Mode is selected. In this mode, the ~ 16 MPU rate is automatically used when addressing within $0000 to $7FFF* or $FFOO to $FF1F ranges. Otherwise the ~ 8 MPU rate is automatically used. (Refer to Figure 8 for sample “E” and “Q' waveforms yielding ~ 8to ~ 16 and + 16 to ~ 8 rate changes). This mode often nearly doubles the MPU throughput while still providing transparent VOG and dynamic, RAM refresh functions. For example, since much of the MPU’s time may Be spent performing internal MPU functions (address = $FFFF), accessing ROM (address = $8000 to $FEFF) or accessing /0 (address = $FF20 — $FF5F), the faster f crystal + 8 MPU rate may be used much of the time. Note: The VOG operates normally when using the SLOW or A.D. rate modes. However, in the FAST rate mode, the VOG is not allowed access to the dynamic RAM. FIGURE 8 — RATE CHANGE E AND Q WAVEFORMS fast slow fast el LEFLI USI L_F LEE EEE ‘When using Memory Map 0, addresses $0000 to $7FFF may access Dynamic RAM. The MC6808 outputs SFFFF on AO-A15 when no other valid addresses are being presented 4-640

“Systems On Silicon” Concept Total Timing For most applications, the SAM can supply complete system timing from its on-chip precision 14.31818 MHz oscillator. This includes buffered MPU clocks (E and Q), VDG clock, color subcarrier (3.58 MHz), row address select (RAS), column address select (CAS) and write enable (WE). Total Address Decode For most applications, the SAM plus a “1 of 8 decoder” chip completely decodes 1/0, ROM and RAM chip selects without wasting memory address space and without needlessly chopping-up contiguous address space. Chip selects are positioned in address space to allow three types of memory (RAM, local ROM and cartridge ROM) independent room for growth. For example, RAM may grow from address $0000-up, cartridge ROM may grow from address $FEFF-down and local ROM may grow from $FBFF-down. Alternately, if the application requires minimum ROM and maximum contiguous RAM, a second choice of two memory maps places RAM from $0000 to SFEFF. (See pages 17 and 18.) In both memory maps all /O, MPU vectors, SAM control registers, and some reserved address spaces are efficiently contained between addresses $FFOO and $FFFF. How Much RAM? Using nine SAM pins (Z0 - 27 and RASO) the following combinations require no additional address logic. FIGURE 13 — RAM CONFIGURATIONS Address: Chip Select: MSB uss ZBZAZIZAZAZO ---ecvvveesecnrenne eee RASO 2Z4Z3Z2Z1ZO .sosssensenessrtsresnesnese PAST (= 27)4” ~~ ~~ One oF two banks of 4K x 8 (like MCM4027's) 26Z52Z423Z2Z1Z0 oo esseercrssecersessnresseseeesee ASO 2BZEZ4ZIZ2Z1ZO ooecsesvvsssensssennneeenseeen MAST (= 27)” ~~~ = = One or two banks of 16K x 8 (like MCM4116’s) PROGRAMMING GUIDE SAM — Programmability ‘ The SAM contains a 16-bit control register which allows the MC6809E to program the SAM for the following options: 32K Page Switch waco T-bit M@MOTY SIZE oo... ceeeeeeeeneeee 2-dItS Map TYPE eecscseesssvseeeenseeeennene T-bit Note that when the SAM is reset by first applying power or by manual hardware reset,t all control register bits are cleared (to a logic 0"). VDG Addressing Mode Three bits (V2, V1, VO) control the sequence of DISPLAY ADDRESSES generated by the SAM (which are used to scan dynamic RAM for video information). For example, if you wish to display Dynamic RAM data as INTERNAL ALPHANUMERICS VIDEO, you should program? the MC6847 for the INTERNAL ALPHANUMERICS MODE and CLEAR BITS V2, V1 and VO in the SAM. The table on the following page summarizes the available modes:

1 See Figure 7 for manual reset circu

{ Typically, part of« PUA (MCBB21) at location SFFZ2 is used to control MCB847 modes. (See MCEB47 Dats Sheet.) 4-643

[internat Aiphanumerice fo = ox [ x {oo [To x foo [oo To | | Extornat Aiphanumerics [| oo =| x [x fs {x To [oo To | | osemigraprics—¢ | to Sf x [ x foo TT x fo [ o To | | Semigraphics—6 fo ST x [x | os fT x fo foo Too | | Semigraphics—er fo ST x [x | oo fT x foo fs To | | Semigraprics—t2e | oo S| x [| x fo fT x fT 1 To To | | Semigraphics—2ae [| oo | x fT x To fT x fT a Tos To | [FulGraphics—te fs Cf oe Too fo fT x fo To Ta | [FulGraphies—ta fs To To Ts fT x Too Too Tt | | FullGreprics—2c Ts To Ts To Tx Pe To To | [Fu'Graphics— an Ts | oo Ts Ts fT x Poo Pos fT | [FulGrephics—ac fs Ts fo To x Ps To To | [Full Graphics— ar Ts Ps To Ps ke Po fe | FulGrephics—ec fy Ts Ts To xe Po a | FuuGraprics— ea fs Ps Pn Ps xe a a [Direct Memory Accesst_ ss |_ x [ x [ x | x [ x [os [os [os | “6, $12, & $24 modes ore not described in the MC6B47 Date Sheet, See appendix “A 1DMA is identical to 6R except as shown in Figure 5 on page 9 VDG Address Offset Seven bits (F6, F5, F4, F3, F2, F1 and FO) determine the Starting Address for the video display. The “Starting Address” is defined as “the address corresponding to data displayed in the Upper Left corner of the TV screen”. The “Starting Address” is shown below in binary: [re[rs[ra[rs[e2ter[rolofTofTo;TotTofovToTo|o| Most Least Significant Significant Bit Bit Note that the “Starting Address” may be placed anywhere within the 64K address space with a resolution of ‘AK (the size of one alphanumeric page). _ The F6-FO bits take effect during the TV vertical synchronization pulse (i.e., when FS from MC6847 is low). Page Switch One bit (P1) is used “in place of” A15 from the MC6803E in order to refer access within $0000-S7FFF to one of two 32K byte pages of RAM. If the system does not use more than 32K bytes of RAM, P1 can be ignored.** *+When using 4K x 1 RAMS, two banks of eight IC's are allowed. This accounts for Addresses $0000-1FFF. Algo, this same RAM can be addrossed at $2000-S2FFF, $4000-S5FFF and $6000:87FFF 4-644

SN74LS783°MC6883 MPU Rate Two bits (R1, RO) control the clock rate to the MCBB09E MPU. The options are: RATE (FREQUENCY OF “E” CLOCK) [R1| Ro | (0.9 MHz (Crystal Frequency ~ 16) Siow 0.9/1.8 MHz (Address Dependent Rate)

1.8 MHz (Crystal Frequency + 8) Fast

(Typical Crystal Frequency = 14.31818 MHz) In the “address dependent rate” mode, accesses to $0000-$7FFF and $FFOO-SFFIF are slowed to 0.9 MHz (crystal frequency + 16) and all other addresses are accessed at 1.8 MHz (crystal frequency ~ 8.) Memory Size ‘Two bits (M1 and MO) determine RAM memory size. The options are: ‘One or two banks of 4K x 1 dynamic RAMS . [One or two banks of 16K = 1 dynamic RAMs [One bank of 64K x 1 dynamic RAMs Up to 64K static RAM* “Requires @ latch for demultiplexing the RAM address. IMPORTANT! Note: Be sure to program the SAM for the correct memory size before using RAM (i.e., for a subroutine stack). . Map Type One bit (TY) is used to select between two memory map configurations. Refer to pages 17, 18 and 19 for details. When using Map Type "TY = 1", only the “Slow MPU rate may be used. Future versions of the SAM may allow use of all rates. Writing To The SAM Control Register Any bit in the control register (CR) may be set by writing to a specific unique address. Each bit has two unique addresses . . . writing to the even # address clears the bit and writing to the odd # address sets the bit. (Data on the data bus is irrelevant in this procedure.) The specific addresses are tabulated on pages 17 and 18. If desired, a short routine may be written to program the SAM CR “a word at a time”. For example, the following routine copies “B” bits from “A” register to SAM CR addresses beginning with address “X”". SAM? “6 ROR A 765 43 210C 24 06 = BCC SAM2. +!

3001 INX—(LEAX1,X)

A780 «STA (O.X-

2002 BRA _SAM3

[SAM2_ [A781 STA_O.X"~ 5A DEC B . 26 «-F2 «BNE SAM

39 RTS

. 16 4-645

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FIGURE 16 — MEMORY ALLOCATION TABLE (Also, see the memory MAPs on pages 17 and 18.) Type #0: (Primarily for ROM based systems) S=4(82)+2 (s1)}+s0

8 Value

‘SFFF2 to FFFF 2 MC6808E Vectors: Reset , NMi, SWI, IRG, FIRG, SWI2, SWI3. FFEO to FFFY 2 Reserved for future MPU enhancements. FFCO to FFOF 7 SAM Control Register: VO, - V2, FO - F6, P, RO, R1, MO, M1, TY. FF60 to FEBF 7 Roserved for future control register enhancements. FF40 to FFEF 6 Og: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO-Aé. FF20 to FFF 5 VO}: Input/Output (PIAS, ACIAS, etc.) To subdivide, use AO- Ad. FFOO to FFIF 4 VOp: Input/Output (PIAs, ACIAs, etc.) To subdivide, use AO Ad. C000 to FEFF 3 ROM2: 16K addresses. External cartridge ROM*. ‘A000 to BFFF 2 ROM1: 8K addresses. Internal ROM*, Note that MC6809E vector addresses select this ROM*. 8000 to SFFF L ROMO: 8K addresses. Internal ROM*. 0000 to 7FFF | 0 if RW = 1| RAM: 32K addresses. RAM shared by MPU and VOG. 7 if RWW =0 *Not restricted to ROM. For example, RAM or V0 may be used here Type #1: (Primarily for RAM based systems) $= 4(82)+2 (s1)+80 S Value Intended Use SFFF2 to FFFF 2 MCE80SE Vectors: Reset, NMI, SWI, IRQ, FIRG, SWI2, SWI3. FFEO to FFF 2 Reserved for future MPU enhancements. FFCO to FFOF 7 SAM Control Register: VO - V2, FO - Fg, P, RO. R1. MO, M1, TY. FF6O to FFBF 7 Small ROM: Boot load program and initial MC6809 vectors. FF40 to FFSF 6 Og: Input/Output (PIAS, ACIAs, etc.) To subdivide, use A0-A4. FF20 to FFF 5 Oy: Input/Output (PIAS, ACIAs, etc.) To subdivide, use AO- Ad. FFOO to FFIF a Vp: Input/Output (PIAS, ACIAs, etc.) To subdivide, use A2- Ad. 0000 to FEFF [0 if RW = 1| RAM: 64K(~256) addresses, shared by MPU and VDG. (if RW = O then S = 3 for $CO00-SFEFF; S = 2 for $A000-SBFFF; S = 1 for $8000-SSFFF and S = 7 for $0000-S7FFF.) 4-648

SN74LS783¢MC6883 APPENDIX A VDG/SAM Video Display System Offers 3 New Modes by . Paul Fletcher There are three new modes created when the VDG ience B2 should be made equal to BO and B3 should and SAM are used together in a video display sys- be made equal to B1. This eliminates a screen place- tem. These modes offer alphanumeric compatibility ment problem which would cause other codes to with 8 color low-to-high resolution graphics, change patterns when moved vertically on the 64H*64V, 64H*96V, 64H*192V. The new modes S8, ‘screen. The illuminated boxes can be one of eight $12, and $24 are created by placing the VOG in the colors which are controlled by B4 - B6 (see Figure Alpha Internal mode and having the SAM in a 2K, 18). The bytes needed to control all the boxes in the 3K or 6K full color graphics mode. In all modes the 8°12 dot box must be spaced 32 address spaces VDG's S/A and Inv. pins are connected to data bits apart in the display RAM because of the addressing D7 and DD6 to allow switching on the fly between scheme orginally used in the VDG and duplicated Alpha and Semigraphics and between inverted by the SAM. This means to place an alphanumeric and non-inverted alpha. This method is used in character on the TV screen it requires 4, 6, or 12 most VDG systems to obtain maximum flexibility. bytes depending on the mode used. These bytes are The three modes divide the standard 8*12 dot box placed 32 memory locations apart in the display used by the VDG for the standard alpha and semi- RAM (see Figure 18). This multiple byte format al- graphics modes into eight 4*3 dot boxes for the SB lows the mixing of character rows of different char- mode, twelve 4*2 dot boxes for the S12 mode, and acters in the same 8*12 dot box creating new char- twenty-four 4*1 dot boxes for the S24 mode. Figure acters and symbols. It also allows overlining and 17 shows the arrangement of these boxes. One byte underlining in eight colors by switching to semi- is needed to contro! two horizontally consecutive graphics at the correct time. boxes. It therefore takes four bytes for the S8, six These new modes optimize the memory versus bytes for the $12, and 12 bytes for the S24 mode to screen density tradeoffs for RF performance on control the entire 8*12 dot box. These two horizon- color TVs. This could make them the most versatile tally consecutive boxes have four combinations of of all the modes depending on the users creativity luminance controlled by bits BO - B3. For conven- and the software sophistication. APPENDIX B Memory Decode for "MAP TYPE = 1” MPU Vectors and Boot Load ROM

128 X 8 (or 256 X 8)

Vec = 16 Grd=8__|+80 aw 7 (O3a) it? 5 Ora) 02

5 Ora ror

#59 4 pa) > Oo ‘SN74LS156 3 ay) enc 82 +e FOr ius TO) (2 From SAM = 3 TO) NC % AY jp *50V. 80>] 0 Too) . WAM READ ° 2 4-649

FAGURE 17 — DISPLAY MODES $8, $12, S24 BitVisible Dot Correlation Left Right Address Byte s Co can COTTE sxxo0 is01) Lines Cooceee coer COT ef Tet 7 sxxz0 1s01) Het $01 is the s8 Pa eeoeeeon Vs "asc" (TTelefelefel | sxxao sor) { code for 'A’ Colette Coe COPED sxxe0 iso) COM rr) . # Alphanumeric Compatible Dots Left Right se, tines [_tee_[ ree_]sxxoo ser [ ewe | on | sxxzo saa) © Options: One of 8 colors for Lor R or both. Off = Black ana Scan [“Bive TBive_]$xxo0 (sar) Lines [“Biack | Black] $xx20 ($80) [Black | Black | $xx40 ($80) _YOG CT Tefefefoler | sxxeo ($14) —Code [1 Tel TT Tel sxxso (sia) for $24 12 COT Tel fet sxxao is18) COCs sxxco ($18) ( voc Ch Tel Tol 1 sxxeo'isia) > cove COTE TeM sxi00 isi8) ( tor x Cre TT Tol sx120 118) [Black [Black] $x140 ($80) [Green [Green ]$x160 (seF) © Underline, Overiine ‘© Mix Character Dot Rows *** Characters will always remain in standard VOG positions 4-650

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goa} * 33 zie 8 go. Lg “ve 38 1 = 2,3 3 s BP TeEEE 8 3Bao5 . 4-651

SN74LS783eMC6883 , ‘FIGURE 19 — EXAMPLE of Mt ec I mi | rm a | 2 ea ea eS eo mi cy ea ea PO ry a a cos] cofa | [| [s—] rm es eC a EC CC vomsen | 528 Po} Eo} Ee] Ed onnecton as a | mse a a | ro Po, see ee = es . “ 2s Fi @ 878 (| § fg i g : = fo} fF y*p m w= ewe] F] mT es ee Ed es fod BJ &] fo fo oo fh} fk} fa] fa—— or or oO” or 7) oO” pb "es m1 ee ee o >} fs} fa] fa] PE (OC (NC sence = = So | wile = = —— Oo S| | ver arcenitteenmee —] B 4-652

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