74LS75 SYC | Alldatasheet
Document overview
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Technical content
These latches are ideally suited for use as temporary stor- age for binary information between processing units and input/output or indicator units. Information present at a data (D) input is transferred to the Q output when the enable is HIGH, and the Q output will follow the data input as long as the enable remains HIGH. When the enable goes LOW, the information (that was present at the data input at the time the transition occurred) is retained at the Q output until the enable is permitted to go HIGH. These latches feature complementary Q and Q outputs from a 4-bit latch, and are available in 16-pin packages. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Diagram (Each Latch) Function Table (Each Latch) H = HIGH Level L = LOW Level X = Don't Care Q 0 = The Level of Q Before the HIGH-to-LOW Transition of ENABLE Connection Diagram Order Number Package Number Package Description DM74LS75M M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS75N N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Inputs Outputs D Enable Q Q LHLH HHHL XL Q 0 Q 0 www.sycelectronica.com.ar
at VCC = 5V and TA = 25°C From (Input) R L = 2 kΩ Symbol Parameter To (Output) C L = 15 pF C L = 50 pF Units M i nM a xM i nM a x tPLH Propagation Delay Time D to Q 27 30 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time D to Q 17 25 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time D to Q 20 25 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time D to Q 15 20 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Enable to Q 27 30 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Enable to Q 25 30 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Enable to Q 30 30 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Enable to Q 15 20 ns HIGH-to-LOW Level Output www.sycelectronica.com.ar
Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E www.sycelectronica.com.ar