74LS299

DM74LS299 FAIRCHILD | Alldatasheet

Document overview

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Technical content

Features

■ Common I/O for reduced pin count ■ Four operation modes: shift left, shift right, load and store ■ Separate shift right serial input and shift left serial input for easy cascading ■ 3-STATE outputs for bus oriented applications Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Logic Symbol VCC = Pin 20 GND = Pin 10 Pin Descriptions Connection Diagram Order Number Package Number Package Description DM74LS299WM M20B 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide DM74LS299N N20A 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Pin Names Description CP Clock Pulse Input (Active Rising Edge) D S0 Serial Data Input for Right Shift D S7 Serial Data Input for Left Shift S0, S1 Mode Select Inputs MR Asynchronous Master Reset Input (Active LOW) OE 1, OE2 3-STATE Output Enable Inputs (Active LOW) I/O0–I/O7 Parallel Data Inputs or 3-STATE Parallel Outputs Q0–Q7 Serial Outputs

www.fairchildsemi.com 2 DM74LS299 Functional Description The DM74LS299 contains eight edge-triggered D-type flip- flops and the interstage logic necessary to perform syn- chronous shift left, shift right, parallel load and hold opera- tions. The type of operation is determined by the S0 and S1, as shown in the Mode Select Table. All flip-flop outputs are brought out through 3-STATE buffers to separate I/O pins that also serve as data inputs in the parallel load mode. Q0 and Q7 are also brought out on other pins for expansion in serial shifting of longer words. A LOW signal on MR overrides the Select and CP inputs and resets the flip-flops. All other state changes are initi- ated by the rising edge of the clock. Inputs can change when the clock is in either state provided only that the rec- ommended setup and hold times, relative to the rising edge of CP, are observed. A HIGH signal on either OE 1 or OE2 disables the 3-STATE buffers and puts the I/O pins in the high impedance state. In this condition the shift, hold, load and reset operations can still occur. The 3-STATE buffers are also disabled by HIGH signals on both S0 and S1 in preparation for a paral- lel load operation. Mode Select Table H = HIGH Voltage Level L = LOW Voltage Level X = Immaterial /c17 = LOW-to-HIGH Clock (CP) Transition Logic Diagram Inputs Response MR S1 S0 CP LX X X Asynchronous Reset; Q0–Q7 = LOW HH H /c17 Parallel Load; I/On→ Q n HL H /c17 Shift Right; DS0→ Q0, Q0→ Q1, etc. HH L /c17 Shift Left; DS7→ Q7, Q7→ Q6, etc. H L L X Hold

3 www.fairchildsemi.com DM74LS299 Absolute Maximum Ratings(Note 1) Note 1: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current Q0, Q7 −0.4 mA I/O0–I/O7 −2.6 mA IOL LOW Level Output Current Q0, Q7 8 mA I/O0–I/O7 24 mA TA Free Air Operating Temperature 0 70 °C tS(H) Setup Time HIGH or LOW 24 nstS(L) S0 or S1 to CP 24 tH (H) Hold Time HIGH or LOW 0 nstH (L) S0 or S1 to CP 0 tS(H) Setup Time HIGH or LOW 10 nstS(L) I/O n, DS0, DS7 to CP 10 tH (H) Hold Time HIGH or LOW 0 nstH (L) I/O n, DS0, DS7 to CP 0 tW (H) CP Pulse Width HIGH or LOW 15 nstW (L) 15 tW (L) MR Pulse Width LOW 15 ns tREC Recovery Time 10 nsMR to CP

www.fairchildsemi.com 4 DM74LS299

Electrical Characteristics

Over recommended operating free air temperature range (unless otherwise noted) Note 2: All typicals are at VCC = 5V, TA = 25°C. Note 3: Not more than one output should be shorted at a time, and the duration should not exceed one second. Switching Characteristics VCC = +5.0V, TA = +25°C Symbol Parameter Conditions Min Typ Max Units (Note 2) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level V CC = Min, IOH = Max Q0, Q7 2.7 3.4 V Output Voltage V IL = Max I/O0–I/O7 2.4 VOL LOW Level V CC = Min, IOL = Max 0.35 0.5 Output Voltage V IH = Min V IOL = 4 mA, VCC = Min 0.25 0.4 II Input Current @ Max V CC = Max Inputs 0.1 mA Input Voltage V I = 7V Sn 0.2 mA IIH HIGH Level V CC = Max, VI = 2.7V Sn 40 µA Input Current Inputs 20 µA IIL LOW Level V CC = Max, VI = 0.4V Sn −0.8 mA Input Current Inputs −0.4 mA IOS Short Circuit V CC = Max Q 0, Q7 −20 −100 mA Output Current (Note 3) I/O 0–I/O7 −30 −130 ICC Supply Current V CC = Max, OE = 4.5V 60 mA IOZH 3-STATE Output Off V CC = Max 40 µA Current HIGH V O = 2.7V IOZL 3-STATE Output Off V CC = Max −400 µA Current Low V O = 0.4V Symbol Parameter R L = 2 kΩ UnitsC L = 15 pF Min Max fMAX Maximum Input Frequency 35 MHz tPLH Propagation Delay 26 ns tPHL CP to Q0 or Q7 28 tPLH Propagation Delay 25 ns tPHL CP to I/On 35 tPHL Propagation Delay 28 ns MR to Q0 or Q7 tPHL Propagation Delay 35 ns MR to I/On tPZH Output Enable Time 18 ns tPZL 25 tPHZ Output Disable Time 15 ns tPLZ 20

5 www.fairchildsemi.com DM74LS299 Physical Dimensions inches (millimeters) unless otherwise noted 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide Package Number M20B

www.fairchildsemi.com 6 DM74LS299 8-Input Universal Shift/Storage Register with Common Parallel I/O Pins Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N20A Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com