74LS112A

DM74LS112A FAIRCHILD | Alldatasheet

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© 2000 Fairchild Semiconductor Corporation DS006382 www.fairchildsemi.com August 1986 Revised March 2000 DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs General Description This device contains two independent negative-edge-trig- gered J-K flip-flops with complementary outputs. The J and K data is processed by the flip-flop on the falling edge of the clock pulse. The clock triggering occurs at a voltage level and is not directly related to the transition time of the falling edge of the clock pulse. Data on the J and K inputs may be changed while the clock is HIGH or LOW without affecting the outputs as long as the setup and hold times are not violated. A low logic level on the preset or clear inputs will set or reset the outputs regardless of the logic levels of the other inputs. Ordering Code: Devices also available in Tape and Reel. Specify by appending the suffix letter “X” to the ordering code. Connection Diagram Function Table H = HIGH Logic Level L = LOW Logic Level X = Either LOW or HIGH Logic Level ↓ = Negative Going Edge of Pulse Q 0 = The output logic level before the indicated input conditions were established. Toggle = Each output changes to the complement of its previous level on each falling edge of the clock pulse. Note 1: This configuration is nonstable; that is, it will not persist when preset and/or clear inputs return to their inactive (HIGH) level. Order Number Package Number Package Description DM74KS112AM M16A 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow DM74LS112AN N16E 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Inputs Outputs PR CLR CLK J K Q Q LHXXX H L HLXXX L H L L X X X H (Note 1) H (Note 1) HH ↓ LL Q 0 Q 0 HH ↓ HL H L HH ↓ LH L H HH ↓ HH T o g g l e HHHXX Q 0 Q 0

www.fairchildsemi.com 2 DM74LS112A Absolute Maximum Ratings(Note 2) Note 2: The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table will define the conditions for actual device operation. Recommended Operating Conditions Note 3: C L = 15 pF, RL = 2 kΩ , TA = 25°C and VCC = 5V. Note 4: The symbol (↓) indicates the falling edge of the clock pulse is used for reference. Note 5: C L = 50 pF, RL = 2 kΩ , TA = 25°C and VCC = 5V. Supply Voltage 7V Input Voltage 7V Operating Free Air Temperature Range 0°C to +70°C Storage Temperature Range −65°C to +150°C Symbol Parameter Min Nom Max Units V CC Supply Voltage 4.75 5 5.25 V VIH HIGH Level Input Voltage 2 V VIL LOW Level Input Voltage 0.8 V IOH HIGH Level Output Current −0.4 mA IOL LOW Level Output Current 8 mA fCLK Clock Frequency (Note 3) 0 30 MHz fCLK Clock Frequency (Note 5) 0 25 MHz tW Pulse Width Clock HIGH 20 (Note 3) Preset LOW 25 ns Clear LOW 25 tW Pulse Width Clock HIGH 25 (Note 5) Preset LOW 30 ns Clear LOW 30 tSU Setup Time (Note 3)(Note 4) 20 ↓ ns tSU Setup Time (Note 4)(Note 5) 25 ↓ ns tH Hold Time (Note 3)(Note 4) 0 ↓ ns tH Hold Time (Note 4)(Note 5) 5 ↓ ns TA Free Air Operating Temperature 0 70 °C

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Electrical Characteristics

over recommended operating free air temperature range (unless otherwise noted) Note 6: All typicals are at VCC = 5V, TA = 25°C. Note 7: Not more than one output should be shorted at a time, and the duration should not exceed one second. For devices, with feedback from the outputs, where shorting the outputs to ground may cause the outputs to change logic state an equivalent test may be performed where VO = 2.125V with the minimum and maximum limits reduced by one half from their stated values. This is very useful when using automatic test equipment. Note 8: With all outputs OPEN, ICC is measured with the Q and Q outputs HIGH in turn. At the time of measurement the clock is grounded. Switching Characteristics at VCC = 5V and TA = 25°C Symbol Parameter Conditions Min Typ Max Units (Note 6) VI Input Clamp Voltage V CC = Min, II = −18 mA −1.5 V VOH HIGH Level V CC = Min, IOH = Max 2.7 3.4 V Output Voltage V IL = Max, VIH = Min VOL LOW Level V CC = Min, IOL = Max 0.35 0.5 Output Voltage V IL = Max, VIH = Min V IOL = 4 mA, VCC = Min 0.25 0.4 II Input Current @ Max V CC = Max, VI = 7V J, K 0.1 Input Voltage Clear 0.3 mA Preset 0.3 Clock 0.4 IIH HIGH Level Input Current V CC = Max, VI = 2.7V J, K 20 Clear 60 µA Preset 60 Clock 80 IIL LOW Level Input Current V CC = Max, VI = 0.4V J, K −0.4 Clear −0.8 mA Preset −0.8 Clock −0.8 IOS Short Circuit Output Current VCC = Max (Note 7) −20 −100 mA ICC Supply Current V CC = Max (Note 8) 4 6 mA From (Input) R L = 2 kΩ Symbol Parameter To (Output) C L = 15 pF C L = 50 pF Units Min Max Min Max fMAX Maximum Clock Frequency 30 25 MHz tPLH Propagation Delay Time Preset to Q 20 24 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Preset to Q 20 28 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Clear to Q 20 24 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clear to Q 20 28 ns HIGH-to-LOW Level Output tPLH Propagation Delay Time Clock to Q or Q 20 24 ns LOW-to-HIGH Level Output tPHL Propagation Delay Time Clock to Q or Q 20 28 ns HIGH-to-LOW Level Output

www.fairchildsemi.com 4 DM74LS112A Physical Dimensions inches (millimeters) unless otherwise noted 16-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-012, 0.150 Narrow Package Number M16A

5 www.fairchildsemi.com DM74LS112A Dual Negative-Edge-Triggered Master-Slave J-K Flip-Flop with Preset, Clear, and Complementary Outputs Physical Dimensions inches (millimeters) unless otherwise noted (Continued) 16-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide Package Number N16E Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be rea- sonably expected to result in a significant injury to the user. 2. A critical component in any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com