74AVC16836A NEXPERIA | Alldatasheet

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latch enable (LE) and clock inputs (CP). through a pullup resistor (Live Insertion). during transient. See Fig. 5 for typical curves.

  • Wide supply voltage range from 1.2 V to 3.6 V
  • Complies with JEDEC standards:
  • JESD8-7 (1.2 V to 1.95 V)
  • JESD8-5 (1.8 V to 2.7 V)
  • JESD8-1A (2.7 V to 3.6 V)
  • CMOS low power consumption
  • Input/output tolerant up to 3.6 V
  • Dynamic Controlled Output (DCO) circuit dynamically changes output impedance, resulting in noise reduction without speed degradation
  • Low inductance multiple VCC and GND pins to minimize noise and ground bounce
  • Power off disables 74AVC16836A outputs, permitting Live Insertion
  • Integrated input diodes to minimize input overshoot and undershoot 3. Ordering information

Table 1. Ordering information

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state 4. Functional diagram aaa-026917 D OE CP LE Y1LE CP Fig. 1. Logic diagram aaa-029024

1 EN1OE

Fig. 2. Logic symbol (IEEE/IEC) 002aac725 VCC Fig. 3. Typical input (data or control) 74AVC16836A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 24 September 2018 2 / 14

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state 5. Pinning information 5.1. Pinning 74AVC16836A CP GND VCC GND A10 A11 A12 A13 GND A14 A15 A16 VCC A17 A18 GND A19 A20 LE aaa-029062 OE GND VCC GND Y10 Y11 Y12 Y13 GND Y14 Y15 Y16 VCC Y17 Y18 GND Y19 Y20 n.c. Fig. 4. Pin configuration TSSOP56 (SOT364-1) 74AVC16836A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 24 September 2018 3 / 14

Table 2. Pin description Table 3. Function selection [1] Output level before the indicated steady-state input conditions were established, provided that CP is high before LE goes low. [2] Output level before the indicated steady-state input conditions were established. Table 4. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. [2] Above 55 °C the value of Ptot derates linearly with 8 mW/K.

  1. Recommended operating conditions

Table 5. Recommended operating conditions Table 6. Static characteristics At recommended operating conditions; Tamb = −40 °C to +85 °C; Voltages are referenced to GND (ground = 0 V).

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state Symbol Parameter Conditions Min Typ[1] Max Unit VI = VIH or VIL IO = -100 μA; VCC = 1.65 V to 3.6 V VCC - 0.20 VCC - V IO = -4 mA; VCC = 1.65 V VCC - 0.45 VCC - 0.10 - V IO = -8 mA; VCC = 2.3 V VCC - 0.55 VCC - 0.28 - V VOH HIGH-level output voltage IO = -12 mA; VCC = 3.0 V VCC - 0.70 VCC - 0.32 - V VI = VIH or VIL IO = 100 μA; VCC = 1.65 V to 3.6 V - GND 0.20 V IO = 4 mA; VCC = 1.65 V - 0.10 0.45 V IO = 8 mA; VCC = 2.3 V - 0.26 0.55 V VOL LOW-level output voltage IO = 12 mA; VCC = 3.0 V - 0.36 0.70 V II input leakage current VI = VCC or GND; VCC = 3.6 V - 0.1 2.5 μA IOFF power-off leakage current VI or VO = 3.6 V; VCC = 0 V - 0.1 ±10 μA VI = VIH or VIL; VO = VCC or GND VCC = 1.65 V to 2.7 V - 0.1 5 μA IOZ OFF-state output current VCC = 3.0 V to 3.6 V - 0.1 10 μA VI = VCC or GND; IO = 0 A VCC = 1.65 V to 2.7 V - 0.1 20 μA ICC supply current VCC = 3.0 V to 3.6 V - 0.2 40 μA CI input capacitance - 3.8 - pF [1] All typical values are measured at Tamb = 25 °C. 9.1. Dynamic Controlled Output graphs A Dynamic Controlled Output (DCO) circuit is designed in. During the transition, it initially lowers the output impedance to effectively drive the load and, subsequently, raises the impedance to reduce noise. Fig. 5 shows VOL vs. IOL and VOH vs. IOH curves to illustrate the output impedance and drive capability of the circuit. At the beginning of the signal transition, the DCO circuit provides a maximum dynamic drive that is equivalent to a high drive standard output device. IOL output current (mA) 0 250200100 15050 aaa-0284293.5 VOL output voltage (V) 2.5 1.5 0.5 VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V a. LOW-level output current. IOH output current (mA) -250 0-50-150 -100-200 aaa-0284303.5 VOH output voltage (V) 2.5 1.5 0.5 VCC = 3.3 V VCC = 2.5 V VCC = 1.8 V b. HIGH-level output current. Fig. 5. Output current as a function of output voltage. 74AVC16836A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 24 September 2018 6 / 14

Table 7. Dynamic characteristics Voltages are referenced to GND (ground = 0 V). For test circuit see Fig. 12.

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state Symbol Parameter Conditions Min Typ [1] Max Unit An to CP; see Fig. 10 VCC = 1.2 V - 0.0 - ns VCC = 1.4 V to 1.6 V 0.3 - - ns VCC = 1.65 V to 1.95 V 0.2 0.0 - ns VCC = 2.3 V to 2.7 V 0.3 0.0 - ns VCC = 3.0 V to 3.6 V 0.2 0.0 - ns An to LE; see Fig. 8 VCC = 1.2 V - 1.2 - ns VCC = 1.4 V to 1.6 V 1.3 - - ns VCC = 1.65 V to 1.95 V 0.9 0.4 - ns VCC = 2.3 V to 2.7 V 0.6 0.2 - ns tsu set-up time VCC = 3.0 V to 3.6 V 0.3 0.0 - ns An to CP; see Fig. 10 VCC = 1.2 V - 0.1 - ns VCC = 1.4 V to 1.6 V 0.6 - - ns VCC = 1.65 V to 1.95 V 0.6 0.2 - ns VCC = 2.3 V to 2.7 V 0.6 0.2 - ns VCC = 3.0 V to 3.6 V 1.2 0.5 - ns An to LE; see Fig. 8 VCC = 1.2 V - -0.7 - ns VCC = 1.4 V to 1.6 V 0.2 - - ns VCC = 1.65 V to 1.95 V 0.4 0.0 - ns VCC = 2.3 V to 2.7 V 0.5 0.1 - ns th hold time VCC = 3.0 V to 3.6 V 1.0 0.5 - ns CP; see Fig. 9 VCC = 1.65 V to 1.95 V 250 - - MHz VCC = 2.3 V to 2.7 V 400 - - MHz fmax maximum frequency VCC = 3.0 V to 3.6 V 500 - - MHz per buffer; VI = GND to VCC [3] outputs enabled - 25 - pF CPD power dissipation capacitance outputs disabled - 6 - pF [2] tpd is the same as tPLH and tPHL. ten is the same as tPZL and tPZH. tdis is the same as tPLZ and tPHZ. [3] CPD is used to determine the dynamic power dissipation (PD in μW). PD = CPD x VCC 2 x fi x N + Σ(CL x VCC 2 x fo) where: fi = input frequency in MHz; fo = output frequency in MHz CL = output load capacitance in pF VCC = supply voltage in Volts N = number of inputs switching Σ(CL x VCC 2 x fo) = sum of the outputs. 74AVC16836A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 24 September 2018 8 / 14

Measurement points are given in Table 8. Measurement points are given in Table 8. Measurement points are given in Table 8. Measurement points are given in Table 8. Measurement points are given in Table 8. Measurement points are given in Table 8. Table 8. Measurement points

Test data is given in Table 9. CL = Load capacitance including jig and probe capacitance. RT = Termination resistance should be equal to output impedance Zo of the pulse generator. VEXT = External voltage for measuring switching times. Table 9. Test data

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state 11. Package outline UNIT A 1 A 2 A 3 b p c D (1) E (2) e H E L L p Q Z y w v θ REFERENCES OUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.2 0.1 o o 0.1 DIMENSIONS (mm are the original dimensions). Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. SOT364-1 99-12-27 03-02-19 w M θ A A 1 A 2 D L p Q detail X E Z e c L X (A ) 3 0.25 1 28 56 29 y pin 1 index b H 1.05 0.85 0.28 0.17 0.2 0.1 14.1 13.9 6.2 6.0 0.5 1 8.3 7.9 0.50 0.35 0.5 0.1 0.08 0.25 0.8 0.4 p E v M A A TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1 mm SOT364-1 A max. 1.2 0 2.5 5 mm scale MO-153 Fig. 13. Package outline SOT364-1 (TSSOP56) 74AVC16836A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 24 September 2018 11 / 14

Table 10. Abbreviations Table 11. Revision history

  • Legal texts have been adapted to the new company name where appropriate.
  • Type number 74AVC16836ADGV (SOT481-2) removed. 74AVC16836A v.5 20020802 Product data sheet - 74AVC16836A v.4 74AVC16836A v.4 20000803 Product specification - 74AVC16836A v.3 74AVC16836A v.3 20000502 Preliminary specification - 74AVC16836 v.2 74AVC16836 v.2 19990723 Preliminary specification - 74AVC_AVCH16836 v.1 74AVC_AVCH16836 v.1 19981207 Objective specification - - 74AVC16836A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 24 September 2018 12 / 14

20-bit registered driver with inverted register enable and Dynamic Controlled Outputs; 3-state 14. Legal information Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term 'short data sheet' is explained in section "Definitions". [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the internet at https://www.nexperia.com. Definitions Draft — The document is a draft version only. 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Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 74AVC16836A All information provided in this document is subject to legal disclaimers. © Nexperia B.V. 2018. All rights reserved Product data sheet Rev. 6 — 24 September 2018 13 / 14