7475

LC7475 SANYO | Alldatasheet

Document overview

• Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 16

Technical content

No.3885A LC7475 On-screen Display Controller for PAL-format Video Advanced Information OVERVIEW The LC7475 is a video display controller for superimposing text and low-level graphics onto a PAL-format television receiver. The LC7475 has 128 characters in internal ROM. Up to 288 characters can be displayed on a 12-line by 24-character display under microprocessor control. The LC7475 features four vertical and four horizontal character dimensions and 64 vertical and 64 horizontal screen start positions. It also features a flashing enable bit for each character position. The LC7475 operates from a 5 V supply and is available in 22-pin shrink DIPs.

FEATURES

+ Complete text and graphics video overlay circuitry * 128 characters in internal ROM * 288 character display capability * 12 X 18 dot-matrix character resolution + Approximately 0.5-or 1 s period character flashing option * Selectable flashing duty cycles of 25, 50 or 75% * Intemal or extemal synchronization ¢ Serial data control + 5 V supply * 22-pin shrink DIP MNo products described or contained herein are intended for use in surgical impiants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. M Anyone purchasing any products described or contained herein for an above-mentioned use shall: ® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO, LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. @ Information (including circuit diagrams and circuit parameters) herein is for example .only; it is not guarant- eed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN - 9021JN No. 3885—1/16

vsst [1] [22] voor xn [2 | [21] oscin xour [3] [20] oscour test [a] SEPIN ast [5] [18] serouT soix [6] C7475 sePG SIN SYNI cs [e] [15] voo1 tex [o | [14] cvin uvcHa [10] [13] vssz vooe [11] [ 12} cvour PACKAGE DIMENSIONS Unit: mm* 3059-DIP22S ze 7 ik 4 | 7 1" 02s a 3.9 max | | 4 \\ ——t vet bk thos |Loss No, 3885—2/16

; 2 é l r[ i} @ Hi 333 & Bee [| 38 a as |® (see Zacs z Eng Bo» (aan a SEs Ras i 2883| | Fs a | $33 355 A TL ELE TF ; No. 3885—3/16

a PIN DESCRIPTION a a a a a a a a a a a a a a a a a a a a a a a SPECIFICATIONS Absolute Maximum Ratings a CT ee SS TT No. 3885—4/16

Recommended Operating Conditions T, = 25°C a inaig supply vaage es Analog supply volage range 45 t0 12701

Electrical Characteristics

Vpn: = 5 V, Vonz2 = 5 V, T, = -30 to 70 °C unless otherwise noted | = Pom Le Ee | ip Sunny cet [me fo em ; = 45 V, ICS, SIN, RST and SCLK -03 02M, v LOW-level input voltage Vue | vss — 0 | - | ian ; Voor = 45 V, v SEPOUT HIGH-level input voltage Vins lox = 1 mA pa | - | - | ICS, SIN, RST and SCLK 03 v HIGHevel input voltage Vine | 9.8001 | - | Voor + ISYNI composite video input Vor voltage vm | fe | | ” CVIN composite video input Vp. voltage vine Ff fe Pe ” ICS, SIN, RST, SCLK and SEPIN pA HIGH-level input current ovour teataoe cuenta eT

twucs) S ‘sus; twascix) twiscLk) tHCS SCLK _ Isuisiny TH(SINy a word ftw SCLK 123 13 14 18 16 12 42 19 14 18 16 fawn mewn ee fm | SO Fe teins wipe | es | me | | | Sa ES a fsatwee wee Te fw | fad wieime Sw INPUT TIMING Data and address words are input in serial format on SIN. A 16-bit address word is input after the falling edge of CS followed by 16-bit data words. The address is incremented automatically after each data word. The data input timing is shown in figure 1. Only the lower eight bits of the address word are significant. Only the lower eight bits of data words at addresses 000H to OAFH, the lower 11 bits of data words at addresses 0BOH to OBBH and the lower 12 bits of data words at addresses OBCH to OBFH are significant. All non-significant bits should be set to 0. FN. 8885 6/16

Figure 1. Input timing Table 1. Memory contiguration

Table 1. Memory configuration—continued be reset to 0 by a reset pulse on RST. Table 2. Horizontal display control register (OBCH) Table 3. Horizontal dimension of characters in line 1

Table 5. Horizontal dimension of characters in lines 3 to 12 teset to O by a reset pulse on RST. Table 6. Vertical display control register (OBDH) Table 7. Vertical dimension of characters in line 1

Table 8. Vertical dimension of characters in line 2 Table 9. Vertical dimension of characters in lines 3 to 12 vertical display start positions are shown in figure 2. Figure 2. Vertical and horizontal sync pulses reset to 0 by a reset pulse on RST. Table 10. Video signal control register (OBEH) also occurs when CS goes LOW. .

Table 10. Video signal contro! register (0BEH)—continued Table 11. Phase selection Table 12. General control register

Table 12. General control register—continued should not be selected during normal operation. Table 13. Flashing duty cycle selection Table 14. Blanking area selection representative can offer advice on how to specify character ROM. Table 15. Line ROM configuration

Table 15. Line ROM configuration—continued The function of each significant bit in a line ROM word is shown in table 16. Table 16. Line ROM word data

7 ROM/RAM

The line addresses in line ROM are shown in table 17. Table 17. Line ROM addresses

Table 17. Line ROM addresses—continued reduces as character size is increased. The character screen configuration is shown in table 18. Table 18. Screen configuration RAM and ROM addresses increment.

Table 19. Example ROM and RAM configuration