LC7442 SANYO | Alldatasheet
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- Horizontal resolution: 600 TV lines*! . ; , + Three built-in D/A converter provided on-chip in the 2 The spetifications vary with the extemal memory as listed PIP memory controller block - * High image quality display provided by vertical filter Lees ero fae Pee a a + Built-in even/odd field determination circuit | Sacreens | x] a + Built-in PLL circuit (requires external LPF) [asceens | x | a] * Handles NTSC/PAL, TV/VCR, and multi-mode ‘Single-screen display consists of ap y * Sub-screen specifications ©: Both dynamic and static images can be frame — Display modes: 2-screen, 3-screen, and displayed 4-screen*2 48: Only dynamic images can be frame displayed — Display on/off and frame on/off/color x¢ Not possible switching, wipe function 3. Mulli-mode is only supported when 1M of extemal memory — Supports switching between fixed (4 corners) and is provided. arbitrary (8-bit specification of vertical and 4. See the separate “APPLICATION NOTE" document for horizontal position) display positions details. —The size of the display area can be either variable or 1/9 of the main picture area, i.e 1/3 of the vertical and 1/3 of the horizontal dimensions of the screen — Horizontal resolution of about 250 dots (Y signal) — Gradations (quantization): 64 (6 bits) SANYO Electric Co.,Ltd. Semiconductor Business Headquarters TOKYO OFFICE Tokyo Bldg.,1-10,1 Chome, Ueno, Taito-ku, TOKYO, 110 JAPAN 5179STH (OT) /73093IN No. 4412-1/22
LC7442, 7442E Package Dimensions unit: mm 3071-DIP64S (LC7442) 3159-QIP64E (LC7442E) [LC7442] [L07442E] ss 2 [newweeni res | as d E 3 57.2 ry = = i oo 9| re =
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SANYO: DIP64S, ‘SANYO: QIP64E Pin Assignments see 8 ® rise a 3 Pacis erkieblisibneree PF BP 832388 Donnan Stes Gz G1 60 SO SO 57 S658 S452 5251 50 49 40 47 <b 45 44 43 42 41 40 39 5837 55 35 34 39 » L07442 . DrIrp64s Ot 22 4.8 6 7 © © 10 41 42 49 4445 48 47 40 49 20 24 22 29 24 28 26 27 28 29 30 91 32 OUUDUDOOOCUOUUDUDUUUUODOUDOUUUDUUUOOUUNO SSESELELRSESRLILLILLILERERSSsees gerz ses sge8 8 ale” 8 8 8 8 . Topview i: 2228 a ebES oon 8. BSEREEE, Ba eB ego, 28228 bi, 83 Bee er SET ER EPR ES NoONnOMNoOOOo oOo Ga a 62 61 60 69 58 57 56 55 64 63 52 51 5049 oves (]1 fe) ae) Ree . wooa [2 47) scx woo2 []3 4s[) so woot [4 45] 50E wooo [) 5 4a) Teer aCe 4a ixoure a7v7]7 42) kouT ase vonaze 41 B manu ase QIP64E ao av aa(]io as OW aa (as se OW az(]te 27 De ade 30 f ancur nota 38 Faoeix trOjis 34.7) osw We Cis 33 [] Asw 17 19 19 20 24 22 29 24 26 26 27 28 20 30 91 2 OUOUUCOOUDUUDOUUOOUOUD BeESeseeesesesegk Top view PEPER EaTIEERE 8288828 o aoe cory a No. 4412-222
C7442, 7442E SSS Block Diagram Y Mi i H R-Y¥ —| P twDeonvener!_z i] input data Vertical filter Writedata | { By xX} | | timing controt 6 (calculation and fine memory)| ‘6 control 174 +) AD control Write address Selector - aa 1 [Dual port : i JDRAM: t H 256 kbytes| + Jor 1 Moyte| | meee | . Loop titer [1] Sub-screen PLL ' H Read data |! ; fe | control Ta ‘| Field H 1 | determination : H Output butler tome AY ] 1 |Main sereen PLL | i Loop filter |} 5 OVA converter | B-Y i 1 Kout i + KouT2 ' | Serial data Control register H 1 | controler Output control, || Mero- ‘ r WAKU processor [73 | i aoio7a No. 4412-3722 :
LC7442, 7442E SSS Component-Type PIP System Structural Diagram (using the LC7442 and LC7480) LC7480 Lc7442 Dual port RAM CLAMP A/D clamp ADCLP >= — PULSE sy |e ysw or or a-y sB-Y ash AAS >| AAS CLK AOCLK vee || Agro Aero SODI3~0O so4~4 sc sc Reset — RES Main vertical synchronization Ww ‘Main horizontal synchronization | —__ Y OH YAOUT > ‘Sub-screen vertical synchronization | __ A-Y KV RAOUT Sub-screen horizontal synchronization | —_ B-Y eo KH BAOUT OFC LJ oce L KFC [ver LT Kep Main/sub switching (blanking) KOUT > KOUT2 waku Frame os Stk ico = [ SDE aoso7a Note: See the separate “APPLICATION NOTE" document for details on applications. No. 4412-422
LC7442, 7442E Interna! Control Registers All functions are operated by inputting control register settings as serial port data. MSB ts8 Address 7 o [or [sev swe foe [vars | Worse | cor [W000 | Operainamode | Ce wvso | KOUTe_[KOUFA [AP [FHP | Daly made [eae [ver [vee [ves [vee [vee ['vre [ver vPo__ Dana ston Ce KC ST Ww Frame ely, con jose i (PLL PLUS PLUS WKS RWK3 [Rwk2 | PLL, frame color (R-Y) VvwiPe | HWIPE | DwiPE [| wemop | BWks | BWKa__ | BWK3 BWk2 Wipe, frame color (B-Y) [ear [errant cua YOR WEALD Dip agement [ear asea [oss [ese ass ese [as [eso | Daslayarea | Note: L: Enter data values of 0. Operating Modes [Mode FJ tMops) Modo _[ Number of sub-screens |Two-sereentrame ff] 9 | 2B) Has screens Aand 8 [Two-sereenied ff ot | te) iets [Has screensAanaB | | Taree-sceen tied [J 1 oT) Fei [Uses screen 8 for 3 screens as a single block Notes: Field: The dynamic image is framed. ‘A and B screen overlapped display is not allowed (including horizontal overlap). Screens A and B Screen A: The sub-screen displayed at the location of its 4 comers. (specified by FVP and FHP) Screen B: Sub-screen displayed at the location according to register data (specified by VPO to VP7 and HPO to HP7) [Function i] Screen [Screen A Display on/off jo { oOo | ©: Can be controlled independently. [Ovnamiostaie PT] Can be contlied joint. : Not supported. [Frame ovo fT oT OC rame - Notes: 4: Controlled jointly with the B screen when BSE-A = 1 Frame coiorfxedidata || | 5: Wipe and display area cannot be used at the same time. [Wes CL CTC 6: An operation evaluation must be performed i the wipe function or the Loisoteyeeas I] Tw | Cisplay area function s tobe used No, 4412-5/22
LC7442, 7442E SS Reglster Data Functions 0; On, x: Off [ata re a ee on [sev TT Stancty mace (PLL circuits stopped) [su TT Static screen tawrting stopped [wT attemode specications [vors1.vorso [| | Vertca ter coctficient selections [wooimooo [| Operating mode specication o2H [rub-8.ruo-a | [= Fieisimemory specication (in 2ccreentiedmode) | [wvsi.mvso | [= nami image specication (wie field selecion) | [wour-a.Kour-a [OT Sereeneimcispiay [rverHe | | TT Fourcomer fined positon specication © fos [verioveo TT Screen Bvericatposiiondaa CS fost | Hevtonpo | TT Screen horizontalposiiondaia 05H [wes.wea | Oo |x | DiconvenertramelorsereensBandA [wwnstovwee [TT im convereriramecoiorY data 6H [pusopus | — [= tv diviserspecifeaton aspectcorestion tuncioni= | | wkstoAwKe | — | | DiRconvenertramecoorRV daa o7H [v.Ho.wiPc {| OT x Wineyposeecion CS | Bwrstoewke | TT bik converertramecolorBY ata Lwwas.wvao PT wie vertical agusiment [wean wars [7 — [= writeherzonial agusimen Lavas Ava | — [Display vericalacjustment J amas Anas [TT isplay horizontal adjustment [ora cupaio [| AD camp postion agusiment [Yean yea | — | =| Phase acjusiment tor @(R-Y.BY)wihrespectioYe | [ weas,weago [| |= mi converter ame positon adjustments | [ee TT assing processing normaly setto Hi: see the APPLICATION NOTE)" | [esea | TT TheAscreenisinked to the B screen cisplayarea | [assieaso | _— | — | Don aeaoarting se speceaton Note: Usage notes may apply for certain setting values. See the separate “APPLICATION NOTE” document for details.
LC7442, 7442E SSS Function Descriptions This section describes the functions supported when 1 Mbyte of external memory is used. « 2-screen frame mode*?. "9 ; Main screen + 2-screen field mode*®. *9 ‘Switching between A and A’ and between B and B’ can be performed indepencenty + 3-screen field mode"8. "9 The 3 screens are handled as a single block, and the functions are the same as those for the B screen. + 4-screen field mode"8. *9. *10 The 4 screens are handied as a single block, and the functions are the same as those for the B screen. Notes: 7: Frame display 8: Frame display for dynamic images only (However, an overrun phenomenon occurs.) 9: Two sub-screens cannot be displayed so that they share a scan line. Examples: x x ro) 10: The maximum vertical direction for the display area is 75%. + Display position of the B screen Vp Vp: Data in register VPO 10 VP7 Hp Hp: Data in register HPO 10 HP7 No. 4412-7/22
LCO7442, 7442E +» Frame control Frame onvott: Registers WK-B and WK-A Sub-screen Frame color: Registers WKVR-8 and WKVR-A t : Fixed color: white YfZLZZZZZZIZIZ Arbitrary color: Specified by register data H Y [YWKS to YWK2| Y Sub-screen Y {RWKS to RWK2] Lexa (BWKS to BWK2| * Wipe function There are 4 wipe types ; ‘An operating time of about 0.5 seconds w [SI-[EE]=Gei=- "wre [Z| ft if ; ” we (E]= [gio An operating time of about 1.0 seconds. ~ (RFQ S-- 401074 Note: The wipe function can only be used on the B screen, * Display area This function allows display in an intermediate state of the wipe operation. <Application Example> — Reducing the size of the sub-screen to reduce the disruption of the main screen Becomes 1/9 or less of the screen area. . (the compression ratio is fixed at 1/9) Main screen — Aspect conversion Example: ‘Main screen Deen converter sub-screen (handles letterbox display) No. 4412-8722
C7442, 7442E * Aspect correction Horizontal direction compression or expansion is effected by changing the PLL oscillator frequency. There are limitations on the values of this setting, so be sure to refer to the separate “APPLICATION NOTE” document for details. <Application Example> — When multi-mode is used NTSC Vertical extension — 16:9 aspect ratio tube | io extension + Fine adjustment of setting values This function allows the number of external components (such as delay circuits) to be reduced. — Position of the image within the sub-screen wHag t : WVAJ: 4 steps in 1H increments Wvau---Lo- A0s078 — Display position RHAJ FF | ava: asosin2tncromens : A HAJ: 4 steps in 246 ns increments — Clamp pulse position rs Ss se CLPAY —_L— ~~ A01076 ouPAY CLPAJ: 4 steps in 800 ns increments — Phase difference between the Y and R-Y/B-Y D/A converter outputs ym) R-Y YCAJ: 4 steps in 267 ns increments Ycau 401077 No, 4412-9/22
LC7442, 7442E — Vertical frame horizontal thickness ——7, WKAJ: 4 steps in 132 as increments D/A converter output K— WAY AQLO78 Note: When (YCAJ1,0] = 00, use care when setting (WKAJ1,0] to values other than 00, since incorrect color data may appear at the right edge. Memory Map The 1 Mbyte VRAM is divided into 4 fields. 0° cou 511 ROW [eo [oo | (ARS1, ARSO} Lon [on | sit Read Selection . a Zscreen kame ‘Automatic switching 1 Automatic switching by the field determination | based on the position Girevit of the A and B screens 2-screen field ‘A screen = FLD-A As above i cece [eels ie oy ra (automatic switching) [Br | pee baa | pers |B? | [a3 | [ 82° | 1 1 * The order BO 10 Bis fixed. Write Selection Dynamic image display is controlled by setting MVSO and MVS1, ‘2-soreen frame ‘Automatic switching by the field | [MVSO) determination circuit [Em aaeontos | mwst | as No. 4412-10/22
LC7442, 7442E eeeSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsSSSsSSSSSSSSsSSSSSSsssssseEeESSS Limitations when a 256 kbit Memory Is Used + 1-screen display The following control registers have fixed values. (MoDI]=t 5 | 2.screen filed mode [MOD] =H — [FLD-B}=L (FLD-A] = KOUT-B and KOUT-A cannot be high at the same time (only 1 screen can be displayed) + Dynamic image display The following contol registers are taken as the display setting. wou KOUTA, | tev a Oe a a * Control register table Control register table for 256 kbyte systems. Bi | MSB LsB Adress soz Toe [Tos fos Ta Te To Description [om sey [sf we [tT vorss [vorso ft | | Acvemode a i ! See item “Dynamic image display” above. Registers starting at address 03H function the same as when 1 Mbit of memory is used. * Multi-mode systems The multi-mode function cannot be used with 256 kbit VRAM since V-dancing occurs in dynamic images. Notes on multl-mode (NTSC-PAL) + External memory Multi-mode can only be used when 1M of external memory is provided. * Operating mode Since vertical dancing occurs in moving images in modes other than two-screen frame mode, this can only be used with static images. When the main screen is NTSC and the subscreen is PAL, images will be expanded vertically. As a result, images may - go offscreen in the 3 and 4 scrcen ficld modes, * Vertical compression ratio Since the number of scan lines in NTSC and PAL differ, the ratios differ by 1/3 in accordance with the ratio of the number of scan lines. No. 4412-11/22
. LC7442, 7442E Pin Functions 40 | 48 | OV Main screen vertical sync signal (negative polarity) 3g | 47 | OW a LA7403 or a syne | Main screen horizontal sync signal (negative polarity) as | 46 | kV F7 separator IC Sub-screen vertical sync signal (negative polarity) a7 | 4s | RA 4 Sub-screen horizontal syne signal (negative polarity) Schmitt 47 | 55 | SCK = Serial clock 4s | sa | sD 1 Microprocessor | Serial data } Serial control 01078 45 | 53 | SDE = Enable RES Initialization circuit Reset Test Vs Test (Connect to Vgg in normal operation) p aotoao 2 | 10 [woos | 0 | Memory 3 | 11 | woo2 | 0 | Memory Memory write data output 4 | 12 | woor | 0 | Memory 5 | 13 | wooo | 0 | Memory 6 | 14 | Aa © | Memory MsB Aotoas 7 | 15 | a7 © | Memory a | 16 | As © | Memory 9 | 17 | As © | Memory Address to | 18 {aa 0 | Memory (AB is lett open when a k ‘d) | so faa © | Memory 256 Koyte memory is used) 12 | 20 [a2 © | Memory 13 | 21 Jat © | Memory 14 | 22 | Ao © | Memory Lss 15 | 23 | OT © | Memory | 16 | 24 | WE © | Memory 17 | 25 | RAS O | Memory Control signals 18 | 26 | CAS © | Memory | 19 | 27 | sc © | Memory | 20 | 28 | sonia | t | Memory 21 | 29 | sop | 1 | Memory Memory read data TTL level 22 | 30 | SoD | 1 | Memory 23 | 31 | sopio | 1 | Memory avtoae Continued on next page. No. 4412-1222
. LC7442, 7442E a Continued from preceding page. ea 26 | 3a | ADs 1 C7480 MSB 27 | 35 | aps 1 L¢7480 28 | 36 | ADs \\ Le7480 Input of A-10-D converted 29 | 37 | ap2 1 Lc7480 sigital data 30 | 3a | adr 1 Lc7480 31 | 39 | ADo \\ Lc7480 LsB 01080 32 | 40 |ysw |o Lc74g0 Y signal selection a3 | a1 |asw | 0} Lc7aso RLY signal selection } MPX switching signals i 34. | a2 |asw |o L780 B-Y signal selection —! 3s | 43 | apcu | o Lc7ago ‘Sampling clock a6 | 44 {ance | o e740 Clamp pulse Aos0es 49 | WAKU tA7403 Frame pulse output 50 | KOUT LAa7403 Main/sub switching signal (blanking) 51_| KouT2 - Control signal fis | lowe | || emerrale mmm | DVsg (tor logie circuits and the line memory) 58 | 2 | vAOUT LA7403 Y signal 87 | 1 | Raout LA7403 RLY signal } D/A output se | 64 | BAOUT La7403 B-Y signal ss | 63 | vAEF Lc7ago 1 DIA connection 54 | 62 | BIAS Capacitor 59 | 3 | AVoo 7 DIA analog power supply 60 | 4 | Avss @3 | 7 [ocp |o LPF Charge pump output ar ee all ae 6: | 5 |or - Resistor Oscillator range resistor Main screen synchronization veo 62 | 6 | OVop 5] Powe supa 1 | 9 | Ogg - si | so |Kcp | o LPF Charge pump output ~ so | 58 | KFC 1 LPF Oscittator control voltage input 53 | 61 | KR _ Resistor Oscitator range resistor Sub-sereen syperonizaton 52 | 60 | KVop J Power supply 49 | 57 | KVs5 No, 4412-13/22
LC7442, 7442E —SSSSSSSSSSSSSSSSSSSSSSSSsSSSSSSSSSSSSSSSSSSSSSSsssese Specifications Absolute Maximum Ratings at Ta = 25 +2°C, Vsg = 0 V [ Paramater Symbol Ratings Unt] Hamar supply volage Maximum input voltage 70310 Von + 0.8 Maximum output voltage Vout max 0310 Vop +03 Vv Allowable power dissipation Pdymax (DIP version) [ 500SS«|Ss mW Pdgmax (QFP version) [880m Operating temperature _______Topr . stows | Storage temperature Tstg 78510 +125 Ee Allowable Operating Ranges at Ta = -10 to +70°C, Veg = 0 V ae eee ee Power supply voliage [Vp fe s0 ss Input high level voltage Vins CMOS levels ["07Vop9 [Pv Vig TTL levels [ag Input low level voltage [Var [6MOSievels 08 vp [| TTL levels re ee eS | [Reterenesvaage [Vase | nere 08 VE Yoo J Electrical Characterlstics at Ta = 25 +2°C, Vpp = 5 V 110%, Vgg =0V Paramate ‘Symbol Conditions Unit went ™m " [min [ye Tmax | Output high level votage oH lon = =1 mA; Pins KCP and OCP | Yoo~1 re O lou = -1 MA; Pins other than KCP and OCP. Vpp-1 re Output low tevel voltage oy = 1 mA: Pins KCP and OCP ee ee | loys 2mA:Ping otmertnankcPandoce [| TT oe Tv | Operating current dissipation | Ipp0__ | RES: H The DVgs pin a ee OV, KV: 60 Hz “The AVgs pin [a] . !'p9° OH, KF: 1SikH2z |The OVss pin ee ee ee look AD data: 4010 |The KVgg pin a es | Output unloaded ee ee | input pin DC. output unloaded a ee ee Output leakage current Vi=Vpp.VggiPinsKCP andOCP ee DIA output resistance a Note: There are 4 power supply pin systems. ‘The power supplies are DVpp, AVpp, OVpp, and KVpp. and they must be identical. Descriptions are for Vpp. The grounds are DVgs, AVss. OVgs and KVgg, and they must be identical. Descriptions are for Vgg. Switching Characteristics at Ta = 25 +2°C, Vpp = 5 V 410%, Vgg = 0 V Paramate symbol [Ratings Pe ee Vertical syne signats Pulse wigth . re ee Rise time a es [_Falime [tye 50s | Horizontal sync signals [Pulse wit [wa Ts | Faiime fe 50 Ts Serial data interface Pulse width | ‘sew [200 [Ts Rise time 'soe re ee | | Daasewp | tsy to s | | Datahois te Os Ww [as | a ee ee a | [vod ty Tt POs No. 4412-14/22
LC7442, 7442E mee Serial Data sD | Fi Hi it First bit in > Frtcaae YC Seen da bit Eighth data bit Z srt data tom H tosu leon i i tSCl : ! i tscw i : Hi esca—j }t8CH | [esc oe —{ botcr ton LECH Synchonization Signals WE pti pte tHR, | tHW 1. .tHA sotoes No. 4412-15/22
LC7442, 7442E een Sub-Screen Digital Processing Specifications Freqney rr LY Our Lo HCS*d try te [as [Ninberofqanizawonbie OT SSSC~CSCSCSCSC~*S DIA comer ¥aeral ton a ‘ca Nonbor af don (roan ee oy [ewey SS Bead dslay | Nombeof dts Bonzo a a a Memory Write Range When the display fine adjustment register (WVAJ1, 0, WHAJ1, 0) is 0000. <NTSC> 63.568 v H H TL escux 512cLk aoctk! ze TM 01: H Hi 3H in one line. ‘The shaded area is the & F3 memory write-in range. gq] O a (80H) _ Fa ed. Note: CLK = 640 {, = 10.07 MHz Aos084 No, 4412-16/22
LC7442, 7442E eee <PAL> : Bans v : H wT eecux si2cex aoctx! Y 3Hin one line. F z ‘The shaded area is the Pa fs ) memory write-in range. ° (84H) Note: CLK = 640 f,; = 10.00 MHz sos00s Memory Read Range <NTSC> <PAL> ° 4 378 383 cuK ° A 378 383 cLx ° : : ° ; r e3- es ae [PT Sub-Screen Display Position (for 4 corner display) When the display fine adjustment register (RVAJ1, 0, RHAJ1, 0) is 0000. rs v i ' 443CLK i ~ aacux i Fa H H ES + : Values in parentheses are for PAL. g ~ || — a\\s : ! rary i i ce | ee | [weregiser [| Hw Tu [ae To | MuLeegister [ H | aa | aH [ 1964 | 156H |
LC7442, 7442E —_— Initial Settings + RES pin: reset This pin must be held low when power is first applicd. Powe DVy9. AVpp. OVpp. KV} fl fr supply (DVp9. AVpp. OVp0, KVpn) i v0 Ao1088 tp: Atleast a few microseconds * Internal control registers The table below lists the states of the registers following a reset. Notes: H: Vp level Es These states are set even if SBY =H. Since all system operations are stopped at this time, the data held in externa! memory cannot bo rain. Registers other than the above arc not initialized by a reset. Serlal Data Interface * Serial input format DxO'LSB 0x7 :MSB 8 aD C3 9) I 9 TD yX__987 220 XN) Yee SDE Te Data (D10 to D17) loaded into the Data (020 to 027) loaded into the Address setup (D00 to D07) address specified by DO0 to D07. address DOO to DO7 + 1, AHS setup {000 to D07) BROS specitied by D 07 es Ao1089 The first 8 bits of data following SDE going low specify an address, and the next 8 bils are register data for that address. The last 8 bits of data are transferred to the incremented address. The address can be re-specified after switching SDE from low to high to low again ( ). Since the PLL clock is not used for serial data transfer, data transfers can be performed when SBY is high. However, data cannot be transferred to registers that are initialized by a reset. Since there is no way to confirm that the transferred data was tatched correctly, we recommend refreshing this data periodically, No, 4412-18/22 : i
LC7442, 7442E Even/Odd Field Determination Circuit Since this determination is based on the phase difference between the falling edges of OV and OH, these must be input with the following timing. : i a ee a Field followin —y y A04090 Note: KV and KH are similar to the above. a= 0.02 to 0.40H b= 0.60 10 0.98 H However, if the PLL aspect correction function is used, these values will differ. See the separate “APPLICATION NOTE” document for details. The horizontal synchronization signal equalizing pulse must be removed. Synchronization Signals + The LC7442 OH and KH pin inputs are set assuming that OH (and KH) are delayed 1 pis from the video signal horizontal synchronization signal. Video signa! pt : fas tw a rt FE tW>ine OH or KH a | Aosoas + Since noise on the synchronization signal input pins (KV, KH, OV and OF) results in image distortion, care must be used in wiring these signals. + Since the sub-screen will be distorted if the synchronization signals are unstable, we recommend turning off display in such cases. Sub-Screen Output Timing kour _} i} it H io Poe (No frame data) | ¢ ; H ! : 1 7 s t , aos0g2 Notes: a: The frame data position shown here is for the timing when registers WKAJO and 1 are 00. b: Whether frame data is present or not is switched by the size of the KOUT pulse. No. 4412-19/22 i
LC7442, 7442E Clamp Pulse + A/D converter clamp Since clamp pulses are output with the timing shown in the figure below, it is sctup to fall within the pedestal range. On reset and during standby, the KH signal goes to a positive polarity, and is output as such. | AD input {| _ J #3; ita) Fa AY its beet rt | socee, fF t1=4.8ps : t= 2.4yus Reset or standby | Notes: 1: The conditions t3 > 0 us and té > 0.5 ws must be met, Aosoga 2: The value of 4.8 ys for tt is the value when registers CLPAJO and 1 are 00. + D/A converter clamp drow Wai ® Sub-screen display ® 04004 Digital data in the A region: [sg ts] Clamping is apptied by the main screen horizontat synchronization signat External Control Output Timing | + Relationship with the LC7480 A/D converter moe eg a gO es sO Oe vew a a ye ee ee ee ‘Sampling data 2 0 LD CD 7 LD 7 OTe ED OT (LC7480 output) [t_.| t= 1/640 fy (about 100 ns) A0s085 Note: Since this circuit operates at the high speeds shown in this figure, care is required to keep leads as short as possible in the wiring used in this circuit, a | : No. 4412-20722 |
LC7442, 7442E eo eeeeSSSSSssSFSsSSSSSSSSSSSSSSSSSSSSSSSSSSSSSsssSses * Video memory relationships This value of tis for situations when aspect correction is not applicd. — Data write (Write data); - : ] + . : oe (Address) XRow X_{ cou j X Ron ) cor [£] r= 17640 ty (about 100 ns) aotovs Note: Since this circuit operates at the high speeds shown in this figure, care is required to keep leads as short as possible in the wiring used in this circuit, — Refresh A CAS before RAS refresh cycle is used. oaS fl H H rh H : cc L£ J t= 17640 fy (about 100 ns) aos097 — Data transfer —> serial read sc i H ! H H i so4~1 - (Memory output XXX XX Lt | t= 1960 t, (about 67 ns) aosose Note: Since this function operates at the high speeds shown in the figure, care is required to keep the leads as short as possible in the circuit wiring. Caution: Contact your Sanyo representative before determining the memory to be used. No, 4412-21/22
LC7442, 7442E ll No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. I Anyone purchasing any products described or contained herein for an above-mentioned use shall: @® Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: @ Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. | Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provide information as of May, 1995. Specifications and information herein are subject to change without notice. No, 4412-22722