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Technical content
Features
Supply (Bias) Voltage Range 3.5 V to 30 V Operation to 800 KHz CMOS and TTL Compatible Inputs Separate logic bias and driver supply pins Optional single supply operation for moderate power
applications
High Impedance Buff ered Inputs with hysteresis Tri-State outputs 80 mA peak SINK/SOURCE current Pin Assignment DIN AIN Vcc Bias D- Vcc Drivers BIN GND C IN EN- VREG
Table 1. Absolute Maximum Ratings Table 2. Electrical Characteristics Unless otherwise specifi ed, TA = 25° C and EN- < 0.8 V.
- This is not a test parameter, but for information only.
Table 3. AC Switching Characteristics Values given at VCCB = 5 V, VCCD = 24 V, TA = 25° C, CL = 1000 pF on all outputs, and EN- < 0.8 V. TPLH - 450 630 ns See above. TPHL - 450 630 ns See above. Output Rise Time T R - 700 980 ns See above. Output Fall Time T F - 700 980 ns See above.
For product information and a complete list of distributors, please go to our web site: www.avagotech.com Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies in the United States and other countries. Data subject to change. Copyright © 2005-2012 Avago Technologies. All rights reserved. AV02-3021EN - January 12, 2012 Package Drawings (Dimensions in Inches) Notes: 1. Lead coplanarity should be o to 0.004" max. 2. Package surface fi nishing: VD1 24~27 (Dual). 3. All dimension excluding mold fl ashes. 4. The lead width, B to be determined at 0.0075" from the lead tip. Symbol
16 SOIC
A 0.054 0.068 A1 0.004 0.0098 B 0.014 0.019 D 0.386 0.393 E 0.150 0.157 H 0.229 0.244 e 0.050 BSC C 0.0075 0.0098 L 0.016 0.034 X 0.020 REF θ1 0° 8° θ2 7° BSC D X E Be PIN NO. 1 ID MARK CL CL A A1 0.010 SEATING PLANE L DETAIL “A” GAUGE PLANE ±0.004 DETAIL “A” C H