723462W

LC723461W SANYO | Alldatasheet

Document overview

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Technical content

Ordering number : ENN*7275 12503RM (OT) No. 7275-1/13 Overview The LC723461W and LC723462W are ultralow-voltage electronic tuning microcontrollers that include a PLL that operates up to 250 MHz and a 1/4 duty 1/2 bias LCD driver on chip. This IC includes an on-chip DC-DC converter that can easily create the power supply voltages needed for electronic tuning and contribute to reducing end product costs. This IC is optimal for portable audio equipment that must operate from a single battery. Function

• Program memory (ROM): — 4096 · 16 bits (8K bytes) : LC723461 — 6144 · 16 bits (12K bytes): LC723462
• Data memory (RAM): — 256 · 4 bits: LC723461 — 512 · 4 bits: LC723462
• Cycle time: 40 µs (all 1-word instructions) at 75kHz crystal oscillation
• Stack: 8 levels
• LCD driver: 48 to 80 segments (1/4 duty, 1/2 bias drive)
• Interrupts: Two external interrupts Timer interrupts (1, 5, 10, and 50 ms)
• A/D converter: Four input channels (8-bit chopper A/D converter. The reference voltage can be switched using the ADCHG instruction.)
• Input ports: 8 ports (of which three can be switched for use as A/D converter input and one can be switched for use as IF counter input.)
• Output ports: 6 ports (of which 1 can be switched for use as the beep tone output and 2 are open-drain ports)
• I/O ports: 19 ports (of which 8 can be switched for use as LCD ports and as mask options, of which 3 can be switched for use as serial I/O ports) Can be switched for CMOS output/open-drain outputs.
• Serial I/O: One system (LC723462)
• PLL: Reference frequencies: 1, 3, 3.125, 5, 6.25, 12.5, and 25 kHz
• Input frequencies: FM band: 10 to 250 MHz AM band (high): 2 to 20 MHz AM band (low): 0.5 to 10 MHz
• Input sensitivity: FM band: 35 mVrms (10 mVrms at 130 MHz), 50 mVrms (130 to 250 MHz) AM band (high, low): 35 mVrms
• IF count: HCTR input pin: 0.4 to 12 MHz (HCTR can be switched to function as a general-purpose input port.) Continued on next page. Package Dimensions unit: mm 3190A-SQFP64 10.0 10.0 12.0 12.0 0.15 0.5 (1.5)0.1 1.7max 0.18(0.5) (1.25) 11 6 3348 Preliminary SANYO: SQFP64 [LC723461W, 723462W] LC723461W, 723462W SANYO Electric Co.,Ltd. Semiconductor Company TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN Ultralow-Voltage ETR Controller with On-Chip LCD Driver CMOS IC Any and all SANYO products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft’s control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO representative nearest you before using any SANYO products described or contained herein in such applications. SANYO assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO products described or contained herein.

No. 7275-2/13 LC723461W, 723462W Continued from preceding page.

• External reset input: During CPU and PLL operations, instruction execution is started from location 0.
• Built-in power-on reset circuit: The CPU starts execution from location 0 when power is first applied.
• Halt mode: The controller-operating clock is stopped.
• Backup mode: The crystal oscillator is stopped.
• Static power-on function: Backup state is cleared with the PF port
• Beep tone: 1.5 and 3.1 kHz
• Built-in DC-DC converter: For LCD and A/D converter use (3 V) Can also be used for TU + B creation by using a secondary coil. (The DC-DC converter voltage step-up operation can be stopped with the DCDCC instruction.)
• Built-in remaining battery life verification function: Converts the V DD pin level through AD converter.
• Memory retention voltage: 0.5 V or higher
• Dedicated memory power supply: The RAM retention time has been increased by the provision of a dedicated memory power supply.
• Package: SQFP-64 (0.5-mm pitch)
• V DD power supply: 0.9 to 1.8 V Pin Assignment 61626364 585960 545556 515253 495057 48 3230 3117 18 19 20 21 22 23 24 25 26 27 28 29 S10 S11 S12 S13/PH 0 S14/PH 1 S15/PH 2 S16/PH 3 S17/PG 0 S18/PG 1 XOUT LC723461W/3462W SQFP-64 PA 3 PA 2 PA 1 PA 0 PB3 PB2 PB1 PB0 PC3 PC2 PC1 PC0 PD 3 PD 2 INT1/P D INT0/PD0 DAC/PD1 BEEP/PE0 ADI3/PF2 ADI1/PF1 ADI0/PF0 SI1/PK3 SI0/PK2 SCK1/PK1 VREF VSS VDDRAM VDC3 VDC1 S20/PG3 S19/PG2 XIN TES T1 EO VS S AM IN FM IN VDD HCTR /PM0 BR ES COMC COM1 COM2 COM3 COM4 I/O I/O I/O I/O I/O I O O I I *: The VDD pin can also function as ADI2 A/D converter input.

No. 7275-3/13 LC723461W, 723462W Parameter Symbol Conditions Ratings Unit VDD 1 max VDD –0.3 to +3.0 V Maximum supply voltage VDD 2 max VDD RAM –0.3 to +4.0 V VDD 3 max VDC3 –0.3 to +4.0 V Input voltage VIN1 FMIN, AMIN –0.3 to VDD 1 +0.3 V VIN2 PA, PC, PD, PF, PK, PG, PH, BRES –0.3 to VDD 1 +0.3 V VOUT 1 PE –0.3 to +7 V Output voltage VOUT 2 PB, PC, PD, PG, PH –0.3 to VDD 1 +0.3 V VOUT 3 VDC1, EO –0.3 to VDD 4 +0.3 V VOUT 4 COM1 to COM4, S1 to S20 –0.3 to VDD 4 +0.3 V IOUT 1 PC, PD, PG, PH, EO 0 to 3 mA IOUT 2 PB 0 to 1 mA Output current IOUT 3 PE 0 to 2 mA IOUT 4 S1 to S20 300 µA IOUT 5 COM1 to COM4 3 mA Allowable power dissipation Pdmax Ta = –10 to +60°C 100 mW Operating temperature Topr –10 to +60 °C Storage temperature Tstg –45 to +125 °C Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Ratings Unit min typ max VDD 1 Voltage applied to the VDD pin 0.9 1.3 1.8 Supply voltage VDD 2 Voltage applied to the VDD RAM pin 2.7 3.0 3.3 V VDD 3 Voltage applied to the VDC3 pin (See note.) 2.7 VDD 4 Memory retention voltage 0.5 VREF input voltage VREF 1 The voltage input to the VREF pin (See note.) 0.66 V VIH1 Ports PC, PD, PG, PH, and PK 0.7 VDD 1 VDD 1 V Input high-level voltage VIH2 Port PA 0.8 VDD 1 VDD 1 V VIH3 Port PF 0.8 VDD 1 VDD 1 V VIH4 Port BRES 0.6 VDD 1 VDD 1 V VIL1 Ports PC, PD, PG, PH, and PK 0 0.3 VDD 1 V Input low-level voltage VIL2 Port PA 0 0.2 VDD 1 V VIL3 Port PF 0 0.2 VDD 1 V VIL4 Port BRES 0 0.2 VDD 1 V VIN1 XIN 0.5 0.6 Vrms Input amplitude VIN2 FMIN, AMIN: VDD 1 = 0.9 to 1.8 V 0.035 0.35 Vrms VIN3 FMIN: VDD 1 = 0.9 to 1.8 V 0.05 0.35 Vrms VIN4 ADI0, ADI1, VDD , ADI3 0.035 0.35 Vrms Input voltage range VIN4 ADI0, ADI1, ADI3, VDD 1 0 VDD 3 V FIN1 XIN: CI ≤ 35 kΩ 70 75 80 kHz FIN2 FMIN: VIN2, VDD 1 = 0.9 to 1.8 V 10 130 MHz Input frequency FIN3 FMIN: VIN3, VDD 1 = 0.9 to 1.8 V 130 250 MHz FIN4 AMIN(L): VIN2, VDD 1 = 0.9 to 1.8 V 2 20 MHz FIN5 AMIN(H): VIN2, VDD 1 = 0.9 to 1.8 V 0.5 10 MHz FIN6 HCTR: VIN4, VDD 1 = 0.9 to 1.8 V 0.4 12 MHz Allowable Operating Ranges at Ta = –10 to +60°C, VDD = 0.9 to 1.8 V Note: VDD 3 R = 240 kΩ DZD2.0X VREF When 0.66 V

No. 7275-4/13 LC723461W, 723462W Parameter Symbol Conditions Ratings Unit min typ max IIH1 XIN: VDD 1 = 1.3 V 3 µA IIH2 FMIN, AMIN, HCTR: VDD 1 = 1.3 V 3 8 20 µA Input high-level current IIH3 Port PF: VDD 1 = 1.3 V 4 µA PA (without pull-down resistors), the PC, IIH4 PD, PG, and PH ports, and BRES, 3 µA PK: VDD 1 = 1.3 V IIL1 XIN: VDD 1 = VSS –3 µA IIL2 FMIN, AMIN, HCTR: VDD 1 = VSS –3 –8 –20 µA Input low-level current IIL3 Port PF: VDD 1 = VSS –4 µA PA (without pull-down resistors), the PC, IIL4 PD, PG, and PH ports, and BRES, –3 µA PK: VDD 1 = VSS Input floating voltage VIF PA (with pull-down resistors) 0.05 VDD 1 V R PD 1 PA (with pull-down resistors), VDD 1 = 1.3 V 75 100 200 kΩ Pull-down resistor values R PD 2 TEST1 (with pull-down resistor), 10 kΩVDD 1 = 1.3 V Hysteresis VH BRES 0.1 VDD 1 0.2 VDD 1 V VOH 1 PB: IO = 1 mA VDD 1 – VDD 1 – V0.7 VDD 0.3 VDD VOH 2 PC, PD, PG and PH: IO = 1 mA VDD 1 – V0.3 VDD 1 VOH 3 EO: IO = 500 µA VDD 3 – V0.3 VDD 3 Output high-level voltage VOH 4 XOUT: IO = 200 µA VDD 1 – V0.3 VDD 1 VOH 5 S1 to S20: IO = 20 µA VDD 3 –1 V VOH 6 COM1, COM2, COM3, COM4: VDD 3 –1 VIO = 100 µA VOH 7 VDC1: IO = 1 mA VDD 3 –1 V VOL 1 PB: IO = –50 µA 0.3 VDD 1 0.7 VDD 1 V VOL 2 PC, PD, PG, PH: IO = –1 mA 0.3 VDD 1 V VOL 3 EO: IO = –500 µA 0.3 VDD 3 V VOL 4 XOUT: IO = –200 µA 0.3 VDD 1 V Output low-level voltage VOL 5 S1 to S20: IO = –20 µA VDD 3 –2 V VOL 6 COM1, COM2, COM3, COM4: VDD 3 –2 VIO = –100 µA VOL 7 PE: IO = 2 mA 0.6 VDD 1 V VOL 8 VDC1: IO = 1 mA 1 V Output off leakage current IOFF 1 Ports PB, PC, PD, PG and EO –3 +3 µA IOFF 2 Port PE –100 +100 nA When the reference voltage is 2.7 V: –1 +1 LSBADI0, ADI1, VDD 1, ADI3. Ta = 25°C A/D converter error When the reference voltage is 2.0 V: ADI0, ADI1, VDD 1, ADI3. Ta = 25°C –1 +1 LSB Note: Linearity is maintained in the converted data. IDD 1 VDD 1 = 1.3 V: FIN2 130 MHz, Ta = 25°C 2 mA Current drain IDD 3 VDD 1 = 1.3 V: In HALT mode, Ta = 25°C *1 0.1 mA IDD 4 VDD 1 = 1.8 V, with the oscillator stopped, 1 µATa = 25°C *2 VDC3 current IDC3 1 Vdd3 = 2.7 V: Halt mode, Ta = 25°C 100 µA Electrical Characteristics within allowable operating conditions Note*: The halt mode current drain is due to 20 instructions being executed every 125 ms.

No. 7275-5/13 LC723461W, 723462W A7 pF FMIN XIN AMIN HCTR TEST1 XOUT VDD VDC3 RES VSS PA, PF7 pF 75 kHz COMC A7 pF FMIN XIN AMIN HCTR TEST1 XOUT VDD VDC3 RES VSS 7 pF 75 kHz COMC 3 V *1. Halt and PLL STOP mode current test circuit *2. Backup mode current test circuit With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. Enter halt mode by software command. The state where CPU operation is stopped with the crystal oscillator unstopped. With all ports other than those specified above left open. With output mode selected for PC and PD. With segments S13 to S20 selected. Enter backup mode by software command. The state where the crystal oscillator is stopped.

No. 7275-6/13 LC723461W, 723462W PHASE DETECTOR REFERENCE DIVIDERDIVIDER SYSTEM CLOCK GENERATOR PROGRAMMBLE DIVIDER1/16,1/17 SEG LA P-ON RESET BANK ADDRESS DECODER DATA BUS TIMER 0 JUDGE ALU CF SKIP BANK LATCH A STACK ADDRESS COUNTER ADDRESS DECODER ROM 4k×16bits (LC723461) 6K×16bits (LC723462) BUS CONTROL JMP CAL RETURN INTERRUPT RESET INSTRUCTION DECODER PLL DATA LATCH PLL CONTROL DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER BUS DRIVER XIN XOUT FMIN PC2 PC1 PC0 PC3 PA3 PA2 PA1 PA0 TEST1 COMC RES AMIN S16/PH3 S15/PH2 S13/PH0 S14/PH1 LCD PORT DRIVER LCPA/B LCDA/B EO S12 S1VSS PB2 PB1 PB0 PB3 PD2 INT1/PD1 INT0/PD0 PD3 LATCH B PE0/BEEP S20/PG3 S19/PG2 S17/PG0 S18/PG1 DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER MPX (6bits) MPX MPX MPX BEEP TONE DAC DATA LATCH BUS DRIVER DATA LATCH BUS DRIVER 7 80 PF2/ADI3 PF1/ADI1 PF0/ADI0 PE1/DAC VDC3 VADJ VDD VDC1 SO1/PK2 SCK1/PK1 SI1/PK3 SIO RAM 256×4bits (LC723461) 512×4bits (LC723462) Clock Control HCTR 1/2 UNIVERSAL COUNTER (20bits)

No. 7275-7/13 LC723461W, 723462W Pin Functions Pin No. Pin I/O Function I/O circuit 75 kHz oscillator connections XIN XOUT I O IC testing. This pin must be connected to ground. —63 TEST1 I Special-purpose ports for key return signal input designed with a low threshold voltage. When a key matrix is formed in combination with port PB, simultaneous multiple key presses with up to 3 keys can be detected. The pull-down resistors are set up for all four pins at the same time with the IOS instruction. This setting cannot be specified for individual pins. In backup mode, these pins go to the input disabled state, and the pull-down resistors are disabled after a reset. PA0 PA1 PA2 PA3 I Unbalanced CMOS outputs. Since these outputs are unbalanced, no diodes are required to prevent short circuits due to simultaneous multiple key presses. These outputs go to the high-impedance output state in backup mode. After a reset, they go to the high-impedance output state and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. PB0 PB1 PB2 PB3 O General-purpose I/O ports. Note that there is a mask option that allows these pins to be used as n-channel open drain ports. PD0, PD1 can be used as an external interrupt port. The IOS instruction (Pwn = 4, 5) is used for switching the general-purpose I/O port function, and these ports can be set to input or output in 1-bit units. (0: input, 1: output) In backup mode they go to the input disabled high-impedance state. After a reset, they switch to the general-purpose input port function. PC0 PC1 PC2 PC3 INT1/PD0 INT0/PD1 PD2 PD3 I/O O General-purpose output ports. Note that PE0 has a shared function as the BEEP output, and that PE1 has a shared function as a D/A converter output port. Since these ports are open drain ports, a resistor must be inserted between each port and VDD. At reset, they are set to the general-purpose output port function .The BEEP instruction is used to switch the BEEP/PE0 port between the general-purpose output port and the BEEP output functions. A BEEP instruction with b2 = 0 will set the BEEP/PE0 port to function as a general-purpose output port. If b2 is set to 1, the instruction will select the BEEP output function. Bits b0 and b1 switch the frequency of the BEEP output. This IC supports two BEEP frequencies. *: When the PE0 port is set to function as the BEEP output, executing an output instruction for PE0 will only change the value of the internal output latch; it will have no effect on the output. The DAC instruction is used to switch the DAC/PE1 port between the general-purpose output port and DAC output functions. These ports go to the high-impedance state in backup mode. That state is maintained until an output instruction, a BEEP instruction, or a DAC instruction is executed. BEEP/PE0 DAC/PE1 I/O Shared function pins used as either general-purpose I/O ports or a serial I/O port. Note that there is a mask option that allows these pins to be used as n-channel open drain ports. When used as general-purpose I/O ports, the I/O direction can be switched in single pin units with the IOS instruction. The IOS instruction is used to switch the function between the general-purpose I/O port and the serial I/O port function. In backup mode, these pins go to the input disabled high-impedance state. After a reset, the general-purpose input port function is selected. SCK1/PK1 SO1/PK2 SI1/PK3 Input with built-in pull-down resistor N-ch open-drain CMOS push-pull/ N-ch open-drain CMOS push-pull/ N-ch open-drain Continued on next page. Unbalanced CMOS push-pull

No. 7275-8/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O Function I/O circuit General-purpose input and A/D converter input shared function ports. The IOS instruction is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched in a units, with 0 specifying general-purpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. *: If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 8-bit successive approximation type converter, and features a conversion time of 0.64 ms. Note that the full-scale A/D converter voltage (FFH) is VDC3/2.0 V. PF0/ADI0 PF1/ADI1 PF2/ADI3 I CMOS input/analog input LCD driver segment output and general-purpose I/O shared function ports. The IOS instruction is used for switching between the segment output and general- purpose I/O functions and between input and output for the general-purpose I/O port function.

• When used as segment output ports The segment output port is selected with the IOS instruction (Pwn = 8). b0 to b3 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3) The segment output port is selected with the IOS instruction (Pwn = 9). b0 to b3 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3)
• When used as general-purpose I/O ports The IOS instruction is used to select input or output. Note that the mode can be set in a bit units. b0 = PG0 b0 = PH0 b1 = PG1 b1 = PH1 0: Input b2 = PG2 b2 = PH2 1: Output b3 = PG3 b3 = PH3 Note that there is a mask option that allows these pins to be used as n-channel open drain ports. In backup mode, these pins go to the input disabled high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose port/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function. PG3/S20 PG2/S19 PG1/S18 PG0/S17 PH3/S16 PH2/S15 PH1/S14 PH0/S13 O CMOS push-pull LCD driver segment output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. 39 to S12 to S1 O LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, these outputs are fixed at the low level. After a reset, these outputs are fixed at the low level. COM4 COM3 COM2 COM1 O CMOS push-pull Continued on next page.

No. 7275-9/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O Function I/O circuit System reset input. In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit.

56 RES I

Output for the 3 V step-up circuit clock. Outputs 1/2 the AM local oscillator frequency in AM reception mode, and 1/256 the FM local oscillator or 75 kHz in FM reception mode.

30 VDC1 O

Voltage stepped up by the DC-DC converter (3 V) May also be used to input an equivalent voltage.

29 VDC3 I

VDC3 reference voltage input. When 0.7 V is input, the VDC3 voltage will be 3 V. The VDC3 sample-to-sample variations can be held to ±3% by attaching an external metal-film resistor and a zener diode.

26 VREF I

RAM backup power supply. Connected to the VDC3 voltage through a diode.28 VDDRAMVADJ I FM VCO (local oscillator) input. This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

59 FMIN I

AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.

60 AMIN I

CW1 b1, b0 Input pins Bandwidth 1 1 FMIN (L) 0.5 to 10 MHz (MW, LW) LCD driver intermediate potential output. The COM waveform must be stabilized by attaching an external capacitor of about 0.1 µF.

55 COMC O

UCS b3, b2 Input pins Measurement mode 0 0 HCTR Frequency measurement 0 1 — 1 0 — General-purpose input and universal counter input shared-function port. The IOS instruction is used to switch between the general-purpose input port and the universal counter input functions.

• When performing frequency measurements, select the HCTR frequency measurement mode and the measurement time with the UCS instruction (b3 = 0, b2 = 0), and start the count with the UCC instruction. The CNTEND flag is set when the count completes. Since this circuit operates as an AC amplifier in this mode, the input signal must be capacitor coupled. When used as a general-purpose input, the input data is acquired with the INR instruction. Input is disabled in backup mode, halt mode, during a reset, and in PLL stop mode. Note that after a reset, the universal counter input port function will be selected.

57 HCTR I

Continued on next page. UCS b1, b0 Measurement time 0 0 1 ms 0 1 4 ms 1 0 8 ms 1 1 32 ms

No. 7275-10/13 LC723461W, 723462W Continued from preceding page. Pin No. Pin I/O Function I/O circuit Main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output,and the pin is set to the high-impedance state when the frequencies match. This output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode. 62 EO O Power supply pin.This pin must be connected to ground. This pin must be connected to ground. This pin must be connected to VDD . Supports A/D converter. V SS VSS VDD CMOS push-pull Note*: When a pin in an I/O switching port is used as an output, applications must first set up the data with an OUT, SPB, or RPB instruction and then set up output mode with an IOS instruction.

LC723461W/723462W Series Instruction Set Terminology ADDR : Program memory address b : Borrow C : Carry DH : Data memory address High (Row address) [2 bits] DL : Data memory address Low (Column address) [4 bits] I : Immediate data [4 bits] M : Data memory address N : Bit position [4 bits] Rn : Resister number [4 bits] Pn : Port number [4 bits] PW : Port control word number [4 bits] r : General register (One of the addresses from 00H to 0FH of BANK0) ( ), [ ] : Contents of register or memory M (DH, DL) : Data memory specified by DH, DL No. 7275-11/13 LC723461W, 723462W Mnemonic Operand Function Operations function Instruction format 1st 2nd AD r M Add M to r r ‹ (r) + (M) ADS r M Add M to r, then skip if carryr ‹ (r) + (M), skip if carry AC r M Add M to r with carry r ‹ (r) + (M) + C ACS r M Add M to r with carry, r ‹ (r) + (M) + C then skip if carry skip if carry AI M I Add I to M M ‹ (M) + I AIS M I Add I to M, then skip if carryM ‹ (M) + I, skip if carry AIC M I Add I to M with carry M ‹ (M) + I + C AICS M I Add I to M with carry, M ‹ (M) + I + C, then skip if carry skip if carry SU r M Subtract M from r r ‹ (r) – (M) SUS r M Subtract M from r, r ‹ (r) – (M), then skip if borrow skip if borrow SB r M Subtract M from r with borrowr ‹ (r) – (M) – b SBS r M Subtract M from r with borrow, r ‹ (r) – (M) – b, then skip if borrow skip if borrow SI M I Subtract I from M M ‹ (M) – I SIS M I Subtract I from M, M ‹ (M) – I, then skip if borrow skip if borrow SIB M I Subtract I from M with borrowM ‹ (M) – I – b SIBS M I Subtract I from M with borrow, M ‹ (M) – I – b, then skip if borrow skip if borrow SEQ r M Skip if r equal to M (r) – (M), skip if zero SEQI M I Skip if M equal to I (M) – I, skip if zero SNEI M I Skip if M not equal to I (M) – I, skip if not zero SGE r M Skip if r is greater than or (r) – (M), equal to M skip if not borrow SGEI M I Skip if M is greater than (M) – I, skip if not borrowequal to I SLEI M I Skip if M is less than I (M) – I, skip if borrow f e d c b a 9 8 7 6 5 4 3 2 1 0 0 1 0 0 0 0 DH DL r 0 1 0 0 0 1 DH DL r 0 1 0 0 1 0 DH DL r 0 1 0 0 1 1 DH DL r 0 1 0 1 0 0 DH DL I 0 1 0 1 0 1 DH DL I 0 1 0 1 1 0 DH DL I 0 1 0 1 1 1 DH DL I 0 1 1 0 0 0 DH DL r 0 1 1 0 0 1 DH DL r 0 1 1 0 1 0 DH DL r 0 1 1 0 1 1 DH DL r 0 1 1 1 0 0 DH DL I 0 1 1 1 0 1 DH DL I 0 1 1 1 1 0 DH DL I 0 1 1 1 1 1 DH DL I 0 0 0 1 0 0 DH DL r 0 0 0 1 1 0 DH DL I 0 0 0 0 0 1 DH DL I 0 0 0 1 1 0 DH DL r 0 0 0 1 1 1 DH DL I 0 0 0 0 1 1 DH DL I Instruction group Continued on next page. Addition instructionsSubtraction instructionsComparison instructions

No. 7275-12/13 LC723461W, 723462W Continued from preceding page. Mnemonic Operand Function Operations function Instruction format 1st 2nd AND r M AND M with r r ‹ (r) AND (M) ANDI M I AND I with M M ‹ (M) AND I OR r M OR M with r r ‹ (r) OR (M) ORI M I OR I with M M ‹ (M) OR I EXL r M Exclusive OR M with r r ‹ (r) XOR (M) EXLI M I Exclusive OR M with M M ‹ (M) XOR I SHR r Shift r right with carry LD r M Load M to r r ‹ (M) ST M r Store r to M M ‹ (r) MVRD r M Move M to destination M [DH, Rn] ‹ (M)referring to r in the same row MVRS M r Move source M referring to r M ‹ [DH, Rn]to M in the same row MVSR M1 M2 Move M to M in the same row [DH, DL1] ‹ [DH, DL2] MVI M I Move I to M M ‹ I TMT M N Test M bits, then skip if all bits if M (N) = all 1, then skipspecified are true TMF M N Test M bits, then skip if all bits if M (N) = all 0, then skipspecified are false JMP ADDR Jump to the address PC ‹ ADDR CAL ADDR Call subroutine PC ‹ ADDR Stack ‹ (PC) + 1 RT Return from subroutine PC ‹ Stack PC ‹ Stack, RTI Return from interrupt BANK ‹ Stack, CARRY ‹ Stack SS SWR N Set status register (Status W-reg) N ‹ 1 RS SWR N Reset status register (Status W-reg) N ‹ 0 TST SRR N Test status register true If (Status R-reg) N = all 1, then skip TSF SRR N Test status register false If (Status R-reg) N = all 0, then skip TUL N Test Unlock F/F If Unlock F/F (N) = All 0, then skip PLL M Load M to PLL register PLL reg ‹ PLL data SIO I1 SIO reg ‹ I1, I2 UCS I Set I to UCCW1 UCCW1 ‹ I UCC I Set I to UCCW2 UCCW2 ‹ I BEEP I Beep control BEEP reg ‹ I DZC I Dead zone control DZC reg ‹ I TMS I Set timer register Timer reg ‹ I IOS PWn N Set port control word IOS reg PWn ‹ N DAC I DA converter control DAC reg ‹ DAC data IN M Pn Input port data to M M ‹ (Pn) OUT M Pn Output contents of M to portP1n ‹ M INR M Pn Input register/port data to MM ‹ (Pn) SPB P1n N Set port1 bits (Pn)N ‹ 1 RPB P1n N Reset port1 bits (Pn)N ‹ 0 TPT P1n N Test port1 bits, then skip if all bits If (Pn)N = all 1, then skipspecified are true TPF P1n N Test port1 bits, then skip if all bits If (Pn)N = all 0, then skipspecified are false BANK I Select Bank BANK ‹ I f e d c b a 9 8 7 6 5 4 3 2 1 0 0 0 1 0 0 0 DH DL r 0 0 1 0 0 1 DH DL I 0 0 1 0 1 0 DH DL r 0 0 1 0 1 1 DH DL I 0 0 1 1 0 0 DH DL r 0 0 1 1 1 0 DH DL I 0 0 0 0 0 0 0 0 1 1 1 0 r 1 1 0 1 0 0 DH DL r 1 1 0 1 0 1 DH DL r 1 1 0 1 1 0 DH DL r 1 1 0 1 1 1 DH DL r 1 1 1 0 0 0 DH DL1 DL2 1 1 1 0 0 1 DH DL I 1 1 1 1 0 0 DH DL N 1 1 1 1 0 1 DH DL N 1 0 0 ADDR (13 bits) 1 0 1 ADDR (13 bits) 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 1 1 1 1 1 1 1 1 0 0 0 SWR N 1 1 1 1 1 1 1 1 0 0 1 SWR N 1 1 1 1 1 1 1 1 0 1 SRR N 1 1 1 1 1 1 1 1 1 0 SRR N 0 0 0 0 0 0 0 0 1 1 0 1 N 1 1 1 1 1 0 DH DL r 0 0 0 0 0 0 0 1 I1 I2 0 0 0 0 0 0 0 0 0 0 0 1 I 0 0 0 0 0 0 0 0 0 0 1 0 I 0 0 0 0 0 0 0 0 0 1 1 0 I 0 0 0 0 0 0 0 0 1 0 1 1 I 0 0 0 0 0 0 0 0 1 1 0 0 I 1 1 1 1 1 1 1 0 PWn N 0 0 0 0 0 0 0 0 0 0 1 1 I 1 1 1 0 1 0 DH DL Pn 1 1 1 0 1 1 DH DL Pn 0 0 1 1 1 0 DH DL Pn 0 0 0 0 0 0 1 0 Pn N 0 0 0 0 0 0 1 1 Pn N 1 1 1 1 1 1 0 0 Pn N 1 1 1 1 1 1 0 1 Pn N 0 0 0 0 0 0 0 0 0 1 1 1 I Bit test instructions Jump and subroutine call instructions carry (r) Logic operation instructionsTransfer instructions Continued on next page. Instruction groupBank switching instructions Status register instructionsI/O instructions Hardware control instructions

PS No. 7275-13/13 LC723461W, 723462W This catalog provides information as of January, 2003. Specifications and information herein are subject to change without notice. Specifications of any and all SANYO products described or contained herein stipulate the performance, characteristics,and functions of the described products in the independent state,and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer’s products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer’s products or equipment. SANYO Electric Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO products (including technical data, services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Electric Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the “Delivery Specification” for the SANYO product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. Mnemonic Operand Function Operations function Instruction format 1st 2nd LCDA M I Output segment pattern to LCD LCD (DIGIT) ‹ M LCDB M I digit direct LCPA M I Output segment pattern to LCD LCD (DIGIT) ‹ LA ‹ M LCPB M I digit through LA ADCHG I AD converter reference voltage change DCDCC I DC/DC clock control HALT I Halt mode control HALT reg ‹ I, then CPU clock stop CKSTP Clock stop Stop x’tal OSC NOP No operation No operation Continued from preceding page. f e d c b a 9 8 7 6 5 4 3 2 1 0 1 1 0 0 0 0 DH DL DIGIT 1 1 0 0 0 1 DH DL DIGIT 1 1 0 0 1 0 DH DL DIGIT 1 1 0 0 1 1 DH DL DIGIT 1 1 1 1 1 1 1 1 1 1 1 0 I 0 0 0 0 0 0 0 0 1 1 1 1 I 0 0 0 0 0 0 0 0 0 1 0 0 I 0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 LCD instructions Other instructions Instruction group