71024S RENESAS | Alldatasheet
Document overview
- Manufacturer or author: lruddell
- PDF pages: 9
Technical content
Features
◆◆◆◆◆ 128K x 8 advanced high-speed CMOS static RAM ◆◆◆◆◆ Commercial (0°C to +70°C), Industrial (–40°C to +85°C) ◆◆◆◆◆ Equal access and cycle times — Commercial and Industrial: 12/15/20ns ◆◆◆◆◆ Two Chip Selects plus one Output Enable pin ◆◆◆◆◆ Bidirectional inputs and outputs directly TTL-compatible ◆◆◆◆◆ Low power consumption via chip deselect ◆◆◆◆◆ Available in 300 and 400 mil Plastic SOJ. Functional Block Diagram
Description
The IDT71024 is a 1,048,576-bit high-speed static RAM organized as 128K x 8. It is fabricated using high-performance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative circuit design techniques, provides a cost-effective solution for high-speed memory needs. The IDT71024 has an output enable pin which operates as fast as 6ns, with address access times as fast as 12ns available. All bidirectional inputs and outputs of the IDT71024 are TTL-compat- ible, and operation is from a single 5V supply. Fully static asynchro- nous circuitry is used; no clocks or refreshes are required for operation. The IDT71024 is packaged in 32-pin 300 mil Plastic SOJ and 32- pin 400 mil Plastic SOJ. CMOS Static RAM
1 Meg (128K x 8-Bit)
◆◆◆◆◆ Industrial temperature range (–40°C to +85°C) is available for selected speeds ◆◆◆◆◆ Green parts available, see ordering information
6.422
71024 CMOS Static RAM
1 Meg (128K x 8-Bit) Commercial and Industrial Temperature Ranges
Mar.30.21 NOTE: 1. This parameter is guaranteed by device characterization, but is not production tested. Truth Table(1,3) Absolute Maximum Ratings (1)Pin Configuration(1) SOJ Top View Recommended Operating Temperature and Supply Voltage Recommended DC Operating Conditions NC A16 A14 A15 A12 CS2 A13 A11 WE A10 2964 drw 02 13 20 OE 14 19 15 18 16GND 17 I/O0 I/O1 I/O2 VCC CS1 I/O7 I/O6 I/O5 I/O4 I/O3 PJG32 PBG32 71024 NOTES: 1. H = V IH, L = VIL, X = Don't care. 2. V LC = 0.2V, VHC = VCC –0.2V. 3. Other inputs ≥VHC or ≤VLC. Inputs I/O FunctionWE CS 1 CS2 OE X H X X High-Z Deselected – Standby (I SB) XV HC(2) X X High-Z Deselected – Standby (I SB1) X X L X High-Z Deselected – Standby (I SB) XX V LC(2) X High-Z Deselected – Standby (I SB1) H L H H High-Z Outputs Disabled HLHL D A T A OUT Read Data LLH X D A T A IN Write Data 2964 tbl 01 NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. V TERM must not exceed VCC + 0.5V. Symbol Rating Value Unit VTERM(2) T erminal Voltage with Respect to GND –0.5 to +7.0 V TBIAS T emperature Under Bias –55 to +125 oC TSTG Storage Temperature –55 to +125 oC PT Power Dissipation 1.25 W IOUT DC Output Current 50 mA 2964 tbl 02 Grade Temperature GND V CC Commercial 0°C to +70°C 0V 5.0V ± 0.5V Industrial –40°C to +85°C 0V 5.0V ± 0.5V 2964 tbl 05 NOTE: 1. V IL (min.) = –1.5V for pulse width less than 10ns, once per cycle. Symbol Parameter Min. Typ. Max. Unit VCC Supply Voltage 4.5 5.0 5.5 V G N D G r o u n d 000 V VIH Input High Voltage 2.2 ____ VCC+0.5 V VIL Input Low Voltage –0.5 (1) ____ 0.8 V 2964 tbl 04 Capacitance (TA = +25°C, f = 1.0MHz, SOJ package) Symbol Parameter (1) Conditions Max. Unit CIN Input Capacitance V IN = 3dV 7 pF CI/O I/O Capacitance V OUT = 3dV 8 pF 2964 tbl 03 NOTE: 1. This text does not indicate orientation of actual part-marking.
- All values are maximum guaranteed values.
Figure 1. AC Test Load Figure 2. AC Test Load *Including jig and scope capacitance.
6.424 Mar.30.21 (VCC = 5.0V ± 10%, Commercial and Industrial Temperature Ranges) 71024S12 71024S15 71024S20 Read Cycle tRC Read Cycle Time 12 — 15 — 20 — ns tAA Address Access Time — 12 — 15 — 20 ns tACS Chip Select Access Time — 12 — 15 — 20 ns tCLZ(1) Chip Select to Output in Low-Z 3 — 3 — 3 — ns tCHZ(1) C h i p D e s e l e c t t o O u t p u t i n H i g h - Z 060708 n s tOE Output Enable to Output Valid — 6 — 7 — 8 ns tOLZ(1) Output Enable to Output in Low-Z 0 — 0 — 0 — ns tOHZ(1) O u t p u t D i s a b l e t o O u t p u t i n H i g h - Z 050507 n s tOH Output Hold from Address Change 4 — 4 — 4 — ns tPU(1) Chip Select to Power-Up Time 0 — 0 — 0 — ns tPD(1) Chip Deselect to Power-Down Time — 12 — 15 — 20 ns Wri te Cycle tWC Write Cycle T ime 12 — 15 — 20 — ns tAW Address Valid to End-of-Write 10 — 12 — 15 — ns tCW Chip Select to End-of-Write 10 — 12 — 15 — ns tAS Address Set-Up T ime 0 — 0 — 0 — ns tWP Write Pulse Width 8 — 12 — 15 — ns tWR Write Recovery Time 0 — 0 — 0 — ns tDW Data Valid to End-of-Write 7 — 8 — 9 — ns tDH D a t a H o l d T i m e 0—0—0— n s tOW(1) Output Active from End-of-Write 3 — 3 — 4 — ns tWHZ(1) W r i t e E n a b l e t o O u t p u t i n H i g h - Z 050508 n s 2964 tbl 09NOTE: 1. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
6.42 Mar.30.21 NOTES: 1. WE is HIGH for Read Cycle. 2. Device is continuously selected, CS1 is LOW, CS2 is HIGH. 3. Address must be valid prior to or coincident with the later of CS1 transition LOW and CS2 transition HIGH; otherwise tAA is the limiting parameter. 4. OE is LOW. 5. Transition is measured ±200mV from steady state. Timing Waveform of Read Cycle No. 1 (1) Timing Waveform of Read Cycle No. 2 (1,2,4)
6.426 Mar.30.21 Timing Waveform of Write Cycle No. 1 (WE Controlled Timing) (1,4,6) Timing Waveform of Write Cycle No. 2 (CS1 AND CS 2 Controlled Timing)(1,4) NOTES: 1. A write occurs during the overlap of a LOW CS1, HIGH CS2, and a LOW WE. 2. t WR is measured from the earlier of either CS1 or WE going HIGH or CS2 going LOW to the end of the write cycle. 3. During this period, I/O pins are in the output state, and input signals must not be applied. 4. If the CS 1 LOW transition or the CS2 HIGH transition occurs simultaneously with or after the WE LOW transition, the outputs remain in a high impedance state. CS1 and CS2 must both be active during the tCW write period. 5. Transition is measured ±200mV from steady state. 6. OE is continuously HIGH. During a WE controlled write cycle with OE LOW, t WP must be greater than or equal to tWHZ + tDW to allow the I/O drivers to turn off and data to be placed on the bus for the required tDW. If OE is HIGH during a WE controlled write cycle, this requirement does not apply and the minimum write pulse is the specified tWP.
6.42 Mar.30.21
Ordering Information
S Power XX Speed X Package X Process/ Temperature Range Blank I(1) Commercial (0°C to +70°C) Industrial (–40°C to +85°C) TY Y 300-mil SOJ (PJG32) 400-mil SOJ (PBG32) Device Type Speed in nanoseconds 2964 drw 09 71024 X G Green X Blank Tube Tape and Reel Orderable Part Information Speed (ns) Orderable Part ID Pkg. Code Pkg. Type Temp. Grade 12 71024S12TYG PJG32 SOJ C 71024S12TYG8 PJG32 SOJ C 71024S12TYGI PJG32 SOJ I 71024S12TYGI8 PJG32 SOJ I 71024S12YG PBG32 SOJ C 71024S12YG8 PBG32 SOJ C 71024S12YGI PBG32 SOJ I 71024S12YGI8 PBG32 SOJ I 15 71024S15TYG PJG32 SOJ C 71024S15TYG8 PJG32 SOJ C 71024S15TYGI PJG32 SOJ I 71024S15TYGI8 PJG32 SOJ I 71024S15YG PBG32 SOJ C 71024S15YG8 PBG32 SOJ C 71024S15YGI PBG32 SOJ I 71024S15YGI8 PBG32 SOJ I 20 71024S20TYG PJG32 SOJ C 71024S20TYG8 PJG32 SOJ C 71024S20TYGI PJG32 SOJ I 71024S20TYGI8 PJG32 SOJ I 71024S20YG PBG32 SOJ C 71024S20YG8 PBG32 SOJ C 71024S20YGI PBG32 SOJ I 71024S20YGI8 PBG32 SOJ I NOTE: 1. Contact your local sales office for Industrial temp range for other speeds, packages and powers.
6.428 Mar.30.21 Datasheet Document History 9/30/99 Updated to new format Pg. 1, 3, 4, 7 Added 12ns industrial speed grade offering Pg. 1–4, 7 Removed military temperature offerings Removed 17ns and 25ns speed grades Pg. 3 Revised I CC and I SB1 for 15ns and 20ns industrial speed grades Pg. 6 Removed Note 1, reordered notes and footnotes Pg. 8 Added Datasheet Document History 1/6/2000 Pg. 4 C hanged t WP(min) for 12ns speed grade from 10ns to 8ns. 2/18/00 Pg. 3 Revised Icc and I SB for Industrial Temperature offerings to meet commercial specifications 3/14/00 Pg. 3 Revised I SB to accommodate speed functionality 08/09/00 Not recommended for new designs 02/01/01 Removed "Not recommended for new designs" 01/30/04 Pg. 7 Added "Restricted hazardous substance device" to the ordering information. 05/22/06 Pg.3 Added drawing Output Capacitive Derating drawing. 02/13/07 Pg.7 Added M generation die step to data sheet ordering information. 08/13/09 Pg.2 Corrected note reference. 02/05/13 Pg.1 Removed /MS from datasheet header. Removed IDT's reference to fabrication. Pg.7 Updated ordering information by adding Tape and Reel, updated Restricted Hazardous Substance Device wording to Green and removed the Die Stepping Revision, the"M" designator. 03/30/21 Pg.1 & 7 Updated Industrial temp and green availability Pg.2 & 7 Updated package codes Pg.7 Added Orderable Part Information table
© 202 Renesas Electronics Corporation. All rights reserved. IMPORTANT NOTICE AND DISCLAIMER RENESAS ELECTRONICS CORPORATION AND ITS SUBSIDIARIES (“RENESAS”) PROVIDES TECHNICAL SPECIFICATIONS AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCE DESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS” AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS OR IMPLIED, INCLUDING, WITHOUT LIMITATION, ANY IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT OF THIRD PARTY INTELLECTUAL PROPERTY RIGHTS. These resources are intended for developers skilled in the art designing with Renesas products. You are solely responsible for (1) selecting the appropriate products for your application, (2) designing, validating, and testing your application, and (3) ensuring your application meets applicable standards, and any other safety, security, or other requirements. These resources are subject to change without notice. Renesas grants you permission to use these resources only for development of an application that uses Renesas products. Other reproduction or use of these resources is strictly prohibited. No license is granted to any other Renesas intellectual property or to any third party intellectual property. Renesas disclaims responsibility for, and you will fully indemnify Renesas and its representatives against, any claims, damages, costs, losses, or liabilities arising out of your use of these resources. Renesas' products are provided only subject to Renesas' Terms and Conditions of Sale or other applicable terms agreed to in writing. No use o any Renesas resources expands or otherwise alters any applicable warranties or warranty disclaimers for these products. ('LVFODLPHURev.1.0 Mar 2020) Corporate Headquarters Contact Information TOYOSU FORESIA, 3-2-24 Toyosu, For further information on a product, technology, the most Koto-ku, Tokyo 135-0061, Japan up-to-date version of a document, or your nearest sales www.renesas.com office, please visit: www.renesas.com/contact/ Trademarks Renesas and the Renesas logo are trademarks of Renesas Electronics Corporation. All trademarks and registered trademarks are the property of their respective owners.