69F1608 MAXWELL | Alldatasheet
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128 Megabit (16M x 8-Bit)
©2005 Maxwell Technologies All rights reserved. Flash Memory Module
01.07.05 REV 2
FEATURES:
- Single 5.0 V supply
- Organization: - Memory cell array: (4M + 128k) bit x 8bit - Data register: (512 + 16) bit x 8bit - Contains 4 (32 Megabit) Die Automatic program and erase - Page program: (512 + 16) Byte - Block erase: (8K + 256) Byte - Status register 528-Byte page read operation - Random access: 10 µ s (max) - Serial page access: 50 ns (min) Fast write cycle time - Program time: 250 µ s (typ) - Block erase time: 2 ms (typ) Command/address/data multiplexed I/O port Hardware data protection - Program/erase lockout during power transitions Reliable CMOS floating-gate technology - Endurance: 1,000,000 program/erase cycles - Data retention: 10 years Command register operation DESCRIPTION: Maxwell Technologies’ 69F1608 high-performance flash mem- ory is a 16M x 8-bit NAND Flash Memory with a spare 128K (131,072) x 8-bit. A program operation programs the 528-byte page in 250 µ s and an erase operation can be performed in 2 ms on an 8K-byte block. Data within a page can be read out at 50 ns cycle time per byte. The on-chip write controller auto- mates all program and erase functions, including pulse repeti- tion, where required, and internal verify and margining of data. Even write-intensive systems can take advantage of the 69F1608’s extended reliability of 1,000,000 program/erase cycles by providing either ECC (Error Correction Code) or real time mapping-out algorithm. These algorithms have been implemented in many mass storage applications. The spare 16 bytes of a page combined with the other 512 bytes can be utilized by system-level ECC. The 69F1608 is an optimum solution for large non-volatile storage applications such as solid state data storage, digital voice recorders, digital still cameras and other applications requiring nonvolatility. Maxwell Technologies' patented R AD-PAK® packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. Capable of surviving in space environments, the 69F1608 is ideal for satellite, spacecraft, and space probe missions. It is available with packaging and screening up to Maxwell Technologies self-defined Class K. Logic Diagram (1 of 4 Die)
128 Megabit (16M x 8-Bit) Flash Memory Module 69F1608
TABLE 1. PINOUT DESCRIPTION
2 Command Latch Enable
3 Address Latch Enable
4 Write Enable
5 Write Protect
when the WP pin is active low. during a read operation, the device is returned to standby mode. Z when the chip is deselected or when the outputs are disabled.
12 V SS Ground
13 V CCQ Output Buffer Voltage
20 Spare Area Enable (SE ) The SE input controls the spare area selection when SE is high,
tial data input and page Program.
21 Read/Busy
The R/B output indicates the status of the device operation. tion when the chip is deselected or when outputs are disabled.
22 Read Enable
23 NC No Connection
TABLE 2. 69F1608 A BSOLUTE MAXIMUM RATINGS 1,2
- Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be
conditions for extended periods may affect reliability. TABLE 3. 69F1608 RECOMMENDED OPERATING CONDITIONS TABLE 4. DELTA LIMITS TABLE 5. 69F1608 AC TEST CONDITION
TABLE 6. 69F1608 DC AND OPERATING CHARACTERISTICS
- Only one (1) CE 1-4 active at a time.
- CE1-4 Leakage Current = +/- 10uA.
TABLE 7. 69F1608 CAPACITANCE 1
- Capacitance Guarenteed by design.
TABLE 8. 69F1608 MODE SELECTION
- When SE is high, spare area is deselected.
- WP should be biased to CMOS high or CMOS low for standby.
TABLE 9. 69F1608 PROGRAM/ERASE CHARACTERISTICS TABLE 8. 69F1608 MODE SELECTION
TABLE 10. 69F1608 AC TIMING CHARACTERISTICS FOR COMMAND/ADDRESS/DATA INPUT TABLE 11. 69F1608 AC CHARACTERISTICS FOR OPERATION
table via the following suggested flow chart (Figure 1).
- If CE goes high within 30 ns after the rising edge of the last RE, R/B will not return to VOL.
- The time to Ready depends on the value of the pull-up resistor tied to R/B pin.
- To break the sequential read cycle, CE must be held high for longer than tCEH.
TABLE 12. 69F1608 VALID BLOCKS 1,2
- The device may include invalid blocks. Invalid blocks are defined as blocks that contain one or more bad bits. Do not try to
minimum number of valid blocks are guaranteed though its initial number could be reduced.
- The 1st block, which is placed on the 00h block address, is guaranteed to be a valid block.
TABLE 11. 69F1608 AC CHARACTERISTICS FOR OPERATION
FIGURE 1. FLOW CHART TO CREATE INVALID BLOCK TABLE include those reclaimed blocks.
FIGURE 2. PROGRAM FLOW CHART
FIGURE 3. ERASE FLOW CHART
FIGURE 4. READ FLOW CHART FIGURE 5. BLOCK REPLACEMENT
the destination of the pointer, and the block diagram shows the diagram of its operation. TABLE 12. DESTINATION OF POINTER TABLE FIGURE 6. BLOCK DIAGRAM OF POINTER OPERATION
FIGURE 7. EXAMPLES OF PROGRAMMING WITH SUCCESSIVE POINTER OPERATION TABLE 13. POINT STATUS AFTER EACH OPERATION System Interface Using CE don’t-care. activating CE during the data-loading and reading would provide significant savings in power consumption.
FIGURE 8. PROGRAM OPERATION WITH CE DON’T CARE FIGURE 9. READ OPERATION WITH CE DON’T CARE
FIGURE 10. COMMAND LATCH CYCLE FIGURE 11. ADDRESS LATCH CYCLE
FIGURE 12. INPUT DATA LATCH CYCLE FIGURE 13. SEQUENTIAL OUT CYCLE AFTER READ (CLE = L, WE = H, ALE = L)
FIGURE 14. STATUS READ CYCLE FIGURE 15. READ1 OPERATION (READ ONE PAGE)
FIGURE 16. READ1 OPERATION (INTERCEPTED BY CE) FIGURE 17. READ2 OPERATION (READ ONE PAGE)
FIGURE 18. SEQUENTIAL ROW READ OPERATION FIGURE 19. PAGE PROGRAM OPERATION
FIGURE 20. BLOCK ERASE OPERATION (ERASE ONE BLOCK) FIGURE 21. MANUFACTURE & DEVICE ID READ OPERATION
21All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. Upon initial device power up, the device defaults to Read1 mode. This operation is also initiated by writing 00h to the command register along with three address cycles. Once the command is latched, it does not need to be written for the following page read operation. Three types of operations are available : random read, serial page read and sequential read. The random read mode is enabled when the page address is changed. The 528 bytes of data within the selected page are transferred to the data registers in less than 10 us(t R). The CPU can detect the completion of this data transfer(tR) by analyzing the output of R/B pin. Once the data in a page is loaded into the regis- ters, they may be read out in 50 ns cycle time by sequentially pulsing RE with CE staying low. High to low transitions of the RE clock output the data starting from the selected column address up to the last column address(column 511 or 527 depending on state of SE pin). After the data of last column address is clocked out, the next page is automatically selected for sequential read. Waiting 10 µ s again allows for reading of the selected page. The sequential read operation is terminated by bringing CE high. The way the Read1 and Read2 commands work is like a pointer set to either the main area or the spare area. The spare area of bytes 512 to 527 may be selectively accessed by writing the Read2 command with SE pin low. Toggling SE during operation is prohibited. Addresses A0 to A3 set the starting address of the spare area while addresses A4 to A7 are ignored. Unless the operation is aborted, the page address is automatically incremented for sequential read as in Read1 operation and spare sixteen bytes of each page may be sequentially read. The Read1 command (00h/01h) is needed to move the pointer back to the main area. Figures 22 thru 25 show typical sequence and timings for each read opera- tion.
FIGURE 22. READ1 OPERATION
FIGURE 23. READ2 OPERATION
FIGURE 24. SEQUENTIAL ROW READ1 OPERATION FIGURE 25. SEQUENTIAL READ2 OPERATION (SE = FIXED LOW)
until another valid command is written to the command register. FIGURE 26. PROGRAM & READ STATUS OPERATION
FIGURE 27. BLOCK ERASE OPERATION
TABLE 14. READ STATUS REGISTER DEFINITION to it. Figure 28 shows the operation sequence. FIGURE 28. READ ID OPERATION
Reset command is written. Reset command is not necessary for normal operation. Refer to Figure 29 below. FIGURE 29. RESET OPERATION TABLE 15. DEVICE STATUS protection and is recommended to be kept at V IL during power-up and power-down as shown in Figure 30. The two step command sequence for program/erase provides additional software protection.
FIGURE 30. AC WAVEFORMS FOR POWER TRANSITION operation and the value may be calculated by following equation.
FIGURE 31. READY/BUSY
31All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. Note: All dimensions in inches
24 PIN RAD-PAK® FLAT PACKAGE
A 0.284 0.310 0.336 A2 0.030 0.035 0.040 b 0.013 0.016 0.018 c 0.006 0.008 0.010 D 0.810 0.820 0.830 D2 0.780 0.800 0.820 E 1.132 1.140 1.148 E1 -- -- 1.170 E2 2.020 2.240 2.464 E3 0.960 0.980 1.000 e 0.050 BSC L 0.410 0.420 0.430 Q 0.212 0.230 0.248 S1 0.000 0.038 -- N2 4
32All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. Important Notice: These data sheets are created using the chip manufacturer’s published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
33All data sheets are subject to change without notice ©2005 Maxwell Technologies All rights reserved. Feature Option Details69F1608 RP F X Screening Flow Package Radiation Feature Base Product Nomenclature MCM1 K= Maxwell Self-Defined Class K H= Maxwell Self-Defined Class H I = Industrial (testing @ -40°C, +25°C, +125°C) E = Engineering (testing @ +25°C) F = Flat Pack RP = R AD-PAK® package
128 Megabit (16M x 8-Bit) Flash
1) Products are manufactured to Maxwell Technologies self-defined Class H and Class K flows.