5962-0324601Q9A

TSC695FL ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Integer Unit Based on SPARC V7 High-performance RISC Architecture
• Optimized Integrated 32/64-bit Floating-point Unit
• On-chip Peripherals – EDAC and Parity Generator and Checker – Memory Interface Chip Select Generator Waitstate Generation Memory Protection –D M A A r b i t e r –T i m e r s General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) – Interrupt Controller With 5 External Inputs – General Purpose Interface (GPI) – Dual UART
• Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface
• IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
• Fully Static Design
• Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz
• Core Consumption: 0.3W Typ. at 12 MIPs
• Operating Range: 3.15V to 3.45V -55°C to +125°C
• Tested up to a Total Dose of 300 Krds (si) according toMIL STD 883 Method 1019
• No Single Event Latch-up Below an LET Threshold of 80 MeV/mg/cm2
• Single Event Upsets Error Rate Better than: – 2 E-7 Error/Component/Day in GEO Orbit – 5 E-5 Error/Component/Day in LEO Orbit (53°, 1000 km)
• Quality Grades: ESCC, and QMLQ or V with 5962-03246
• Package: 256 MQFPF; Bare Die

Description

The TSC695FL (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SP ARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications. The processor is manufactured using the Atmel 0.5 µm radiation tolerant ( ≥ 300 KRADs (Si)) CMOS enhanced process (RTP). It can operate at a low voltage for opti- mized power consumption (see datasheet TSC695FL). It has been specially designed for space, as it has on-chip concurrent transient and permanent error detection. The TSC695FL includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695FL offers a high security watchdog, two timers , an interrupt controller, parallel and serial interfaces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly testable with the support of an On-Chip Debugger (OCD), and a boundary scan through JTAG interface. The TSC695FL is a selection of the TSC5695F performed for a narrow 3.3V biasing voltage range (± 0.15V), as such, this s pecification can be only met by the products solds as TSC695FL. Where computing power is not the key factor, it allows for a dra- matic power consumption reduction (70%). Low-Voltage Rad-Hard 32-bit SPARC Embedded Processor TSC695FL

2 TSC695FL

Figure 1. TSC695FL Block Diagram Pin Descriptions For pin assignment, refer to package section.

4204C–AERO–05/05 Note: If not specified, the output buffer type is 150 pF, the input buffer type is TTL. OE O Low Memory output enable Output buffer: 400 pF BUFFEN O Low Data buffer enable - DDIR O High Data buffer direction - DDIR O Low Data buffer direction - IOSEL[3:0] O Low I/O chip select - IOWR O Low I/O and exchange memory write strobe - EXMCS O Low Exchange memory chip select - BUSRDY I Low Bus ready - BUSERR I Low Bus error - DMAREQ I Low DMA request - DMAGNT O Low DMA grant - DMAAS I High DMA address strobe - DRDY O Low Data ready during DMA access - IUERR O Low IU error - CPUHALT O Low Processor (IU & FPU) halt and freeze - SYSERR O Low System error - SYSHALT I Low System halt - SYSAV O High System availability - NOPAR I Low No parity - INULL O High Integer unit nullify cycle - INST O High Instruction fetch Used to check the execute stage of IU instruction pipeline FLUSH O High FPU instruction flush DIA O High Delay instruction annulled RTC O High Real Time Clock Counter output - RxA/RxB I Receive data UART ’A’ and ’B’ Input trigger TxA/TxB O Transmit data UART ’A’ and ’B’ - GPI[7:0] I/O GPI input/output Input trigger GPIINT O High GPI interrupt - EXTINT[4:0] I External interrupt Input trigger EXTINTACK O High External interrupt acknowledge - IWDE I High Internal watch dog enable - EWDINT I High External watch dog input interrupt Input trigger WDCLK I Watch dog clock - CLK2 I Double frequency clock - SYSCLK O System clock - RESET O Low Output reset - SYSRESET I Low System input reset Input trigger TMODE[1:0] I Factory test mode Functional mode=00 DEBUG I High Software debug mode - TCK I Test (JTAG) clock - TRST I Low Test (JTAG) reset pull-up ≈ 37 kΩ TMS I Test (JTAG) mode select pull-up ≈ 37 kΩ TDI I Test (JTAG) data input pull-up ≈ 37 kΩ TDO O Test (JTAG) data output - VCCI/VSSI Main internal power - VCCO/VSSO Output driver power - Signal Type Active Description

4 TSC695FL

other system support functions are provided by the core. Figure 2. System Architecture Based on TSC695FL

4204C–AERO–05/05 Product Description Integer Unit The IU is designed for hi ghly dependable space and milit ary applications, and includes support for error detection. T he RISC architecture makes the creation of a processor that can execute instructions at a rate ap proaching one instruction per processor clock possible. To achieve that rate of execution, the IU employs a four-stage instruction pipeline that permits parallel execution of multiple instructions.

• Fetch - The processor outputs the instru ction address to fetch the instruction.
• Decode - The instruction is placed in th e instruction register and is decoded. The processor reads the operands from the register file and computes the next instruction address.
• Execute - The processor executes the instruction and saves the results in temporary registers. Pending traps are prioritized and internal traps are taken during this stage.
• Write - If no trap is taken, the processor writes the result to the destination register. All four stages operate in parallel, working on up to four different instructions at a time. A basic ’single-cycle’ instruction enters the pipeline and completes in four cycles. By the time it reaches the write stage, three more instructions have entered and are moving through the pipeline behind it. So, after the first four cycles, a single-cycle instruction exits the pipeline and a single- cycle instruction enters the pipeline on every cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but they are called single cycle because with this type of instruction the processor can com- plete one instruction per cycle after the initial four-cycle delay. Floating-point Unit The FPU is designed to provide executio n of single and double-precision floating-point instructions concurrently with execution of integer instructions by the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard. The FPU is designed for highly dependable space and military applications, and includes support for concurrent error detection and testability. The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and write stages (F, D, E and W). The fetch unit captures instructions and their addresses from the data and address busses. The decode unit contains logic to decode the float- ing-point instruction opcodes. The execution unit handles all instruction execution. The execution unit includes a floating-point qu eue (FP queue), which contains stored float- ing-point operate (FPop) instructions under execution and their addresses. The execution unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon the IU to access all addresses and control signals for memory access. Floating-point loads and stores are executed in conjunction with the IU, which provides addresses and control signals while the FPU supplies or stores the data. Instruction fetch for integer and floating-point instructions is provided by the IU. The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR is a 32-bit status and control register. It keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various IEEE exception information. The floating-point queue contains the floating-point instruction currently under execution, along with its corresponding address.

6 TSC695FL

cal/shift, control transfer, read/write cont rol register, floating-po int, and miscellaneous. Please refer to SPARC V7 Instruction-set Manual. Note: The execution of IFLUSH will cause an illegal instruction trap. Table 1. Memory Mapping Table 2. System Registers Address Map

Table 2. System Registers Address Map (Continued)

8 TSC695FL

4204C–AERO–05/05 A bus time-out function of 256 system clock cycles is provided for the bus ready con- trolled memory areas, i.e. the Extended PROM, Exchange Memory, Extended RAM, Extended I/O and the Extended General areas. EDAC The TSC695FL includes a 32-bit EDAC (Err or Detection And Correction). Seven bits (CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR) is used to check and generate the odd parity over the 32-bit data bus. This means that altogether 40 bits are used when the EDAC is enabled. The TSC695FL EDAC uses a 7-bit Hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at- one and stuck-at-zero failure for any nibble in the data word as a non-correctable error. Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non- correctable error. Memory and I/O Parity The TSC695FL handles parity towards memory and I/O in a special way. The processor can be programmed to use no parity, only pari ty or parity and EDAC protection towards memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR. Memory Redundancy Programming the Memory Configuration Regist er, the TSC695FL provides chip selects for two redundant memory banks for replacement of faulty banks. Memory Access Protection • Unimplemented Areas - Access to all unimp lemented memory areas are handled by the TSC695FL and detected as illegal.

• RAM Write Access Protection - The TSC695FL can be programmed to detect and mask write accesses in any part of the RAM. The protection scheme is enabled only for data area, not for the instruction area. The programmable write access protection is based on two segments.
• Boot PROM Write Protection - The TSC695FL supports a qualified PROM write for an 8-bit wide PROM and/or for a 40-bit wide PROM. DMA DMA Interface The TSC695FL supports Direct Memory Acce ss (DMA). The DMA unit requests access to the processor bus by asserting the DMA request signal (DMAREQ ). When the DMA unit receives the DMAGNT signal in response, the processor bus is granted. In case the processor is in the power-down mode the processor is permanent tri-stated, and a DMAREQ will directly give a DMAGNT . The TSC695FL includes a DMA session time- out function. Bus Arbiter The TSC695FL always has the lowest priority on the system bus. Traps A trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. The base address of the table is established by supervisor and the displacement, within the table, is determined by the trap type. Two categories of traps can appear.

Table 3. Synchronous Traps TSC695FL enters (if not masked) in halt or reset mode. TSC695FL enters (if not masked) in halt or reset mode. Special case of non-restartable, precise error. TSC695FL enters (if not masked) in halt or reset mode. TSC695FL enters (if not masked) in halt or reset mode. TSC695FL enters (if not masked) in halt or reset mode. Severe error, cannot restart the instruction. Data bus error 9.2 Parity error on FPU data bus. Restartable error 9.3 Can be removed restarting the instruction.

10 TSC695FL

are cleared automatically when the interrupt is acknowledged. high and to define the external interrupts to be either edge or level sensitive. Table 3. Synchronous Traps (Continued) Table 4. Interrupts or Asynchronous Traps

4204C–AERO–05/05 Timers In software debug mode the timers are controlled by a system register bit and the exter- nal pin DEBUG. General Purpose Timer The General Purpose Timer (GPT) provides, in addition to a generalized counter func- tion, a mechanism for setting the step size in which actual time counts are performed. GPT is clocked by the internal system clock. They are pos sible to program to be either of single-shot type or periodical type and in both cases generate an interrupt when the delay time has elapsed. The current value of the scaler and counter of the GPT can be read. Real Time Clock Timer The only functional differences between the two timers are that the Real Time Clock Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has higher priority than the GPT interrupt. RTCT information is available on RTC output pin. Watchdog Timer Setting the external pin IWDE to Vcc enables the internal watchdog timer. Otherwise the watchdog function must be externally provided. The watchdog is supplied from a separate external input (WDCLK). After reset, the timer is enabled and starts running with the maximum range. If the timer is not refreshed (reprogrammed) before the counter reaches ze ro value, an interrupt is sent. Simulta- neously, the timer starts counting a rese t time-out period. If the timer is not acknowledged before the reset time-out period elapses, a reset is applied to TSC695FL. UARTs Two full duplex asynchronous receiver tr ansmitters (UART) are included. In software debug mode the UART’s are controlled by system register bits. The data format of the UART’s is eight bits. It is possible to choose between even or odd parity, or no parity, and between one and two stop bits. The UART’s provide double buff- ering, i.e. each UART consists of a tran smitter holding register , a receiver holding register, a transmitter shift register, and a receiver shift register. Each of these registers are 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generate an interrupt each time a byte has been received or a byte has been sent. There is another interrupt to indicate errors. The baud rate of both the UART’s is programmable. The clock is derived either from the system clock or can use the watchdog clock. General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be config- ured as an input or an output. A falling or rising edge detection is made on each selected GPI inputs. Every input tran- sition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width. Execution Modes Reset Mode Reset mode is entered when: – The SYSRES input is asserted – Software reset which is caused by the software writing to a Software Reset Register, – Watchdog reset which is caused by a Watchdog counter time-out – Error reset which is caused by a hardware parity error

12 TSC695FL

4204C–AERO–05/05 This RESET output has a minimum of 1024 SYSCLK width to allow the usage of flash memories. The error and Reset Status Register contain the source of the last processor reset. Run Mode In this mode the IU/FPU is executing, while all peripherals are running (if software enabled). System Halt Mode System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU and FPU are frozen, while the timers (i ncludeing the internal watchdog timer) and UART’s are stopped. Power Down Mode This mode is entered by writing to the Powe r Down Register. In this mode, the IU and FPU are frozen. The TSC695FL leaves the power-down mode if an external interrupt is asserted. Error Halt Mode Error Halt mode is entered under the following circumstances: – A internal hardware parity error. – The IU enters error mode. The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET Error Handler The TSC695FL has one erro r output signal (SYSERR ) which indicates that an unmasked error has occurred. Any error signalled on the error inputs from the IU and the FPU is latched and reflected in the Error and Reset Status Register. By default, an error leads to a processor halt. Parity Checking The TSC695FL includes: – Parity checking and generation (if required) on the external data bus, – Parity checking on the external address bus, – Parity checking on ASI and SIZE, – Parity checking and generation on all system registers, – Parity generation and checking on the internal control bus to the IU, All external parity checking can be disabled using the NOPAR signal. System Clock The TSC695FL uses CLK2 clock input dire ctly and creates a system clock signal by dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the appli- cation. It is highly recommended that only SYSCLK rising edge is used as reference as far as possible. System Availability The SYSAV bit in the Error and Reset Status Register can be used by software to indi- cate system availability. Test Mode The TSC695FL includes a number of software test facilities such as EDAC test, Parity test, Interrupt test, Error test and a simple Test Access Port. These test functions are controlled using the Test Control Register.

4204C–AERO–05/05 Test and Diagnostic Hardware Functions A variety of TSC695FL test and diagnosti c hardware functions, including boundary scan, internal scan, clock control and On-chip Debugger, are controlled through an IEEE 1149.1 (JTAG) standard Test Access Port (TAP). Test Access Port The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695FL chip. These pins are: – TCK (input): Test Clock – TMS (input): Test Mode Select – TDI (input): Test Data Input – TDO (output): Test Data Output –T R S T (input): Test Reset Instruction Register Five standard instructions are supported by the TSC695FL TAP. Debugging The design is highly testable with the support of an On-Chip Debugger (OCD), an inter- nal and boundary scan through JTAG interface. Binary Value Name of Instruction Data Register Scan Chain Accessed 00. 0000 EXTEST Boundary Scan Register Boundary scan chain 00. 0001 SAMPLE/PRELOAD Boundary Scan Register Boundary scan chain 00. 0011 INTEST Boundary Scan Register Boundary scan chain 11. 1111 BYPASS Bypass Register Bypass register 10. 0000 IDCODE Device ID Register ID register scan chain

14 TSC695FL

4204C–AERO–05/05

Electrical Characteristics

Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 5. DC Characteristics at VDD 3.3V ± 0.15V

Table 6. AC Characteristics (SYSCLK Freq. = 15 MHz - 3.3V ± 0.15V) Cload = 50 pF, Vref = VCC/2

1 SYSCLK+

16 TSC695FL

Table 6. AC Characteristics (SYSCLK Freq. = 15 MHz - 3.3V ± 0.15V) Cload = 50 pF, Vref = VCC/2 (Continued)

Figure 3. 150 pF Buffer Response (Data from simulation)

18 TSC695FL

Figure 4. 400 pF Buffer Response (Data from simulation)

**Figure 5. OE*/400 pF Buffer Response (Data from simulation)**

20 TSC695FL

Figure 6. RAM Fetch, RAM Load and RAM Store Sequence - n Waitstates for Read, m Waitstates for Write 1 (RAM fetch) 2 (RAM load) 3 (RAM fetch) 4 (RAM store) 5 (RAM fetch)

Figure 7. RAM “Atomic-load-store” byte Sequence - 0 Waitstate1 (RAM fetch) 2 (RAM atomic load store) 3 (RAM fetch)

22 TSC695FL

Figure 8. RAM Load-double and RAM Store-double Sequence - 0 Waitstate1 (RAM fetch) 2 (RAM double load) 3 (RAM fetch) 4 (RAM double store) 5 (RAM fetch)

Figure 9. RAM Load with Correctable Error - 0 Waitstate1 (RAM fetch) 2 (RAM load correctable data) 3 (RAM fetch) 4 (RAM fetch)

24 TSC695FL

Figure 10. RAM Load with Uncorrectable Error - 0 Waitstate1 (RAM fetch) 2 (RAM load) 3 (RAM fetch) 4 (null cycle) 5 (RAM fetch) 6 (RAM fetch)

Figure 11. RAM Load with Unimplemented Area Access - 0 Waitstate1 (RAM fetch) 2 (RAM load) 3 (RAM fetch) 4 (null cycle) 5 (RAM fetch) 6 (RAM fetch)

26 TSC695FL

**Figure 12. I/O Store Sequence with BUSRDY* and n Waitstates (Timing for 0 Waitstate = Timing for 1 Waitstates)**

**Figure 13. I/O Load Sequence with BUSRDY* and n Waitstates (Timing for 0 ws = Timing for 1 ws)**

28 TSC695FL

**Figure 14. EXCHANGE RAM Store with BUSDRY* and n Waitstates**

**Figure 15. EXCHANGE RAM Load with BUSDRY* and n Waitstates1 (RAM fetch) 2 (xchgRAM load) 3 (RAM fetch)**

30 TSC695FL

Figure 16. 8-bit BOOT PROM Fetch (or Load Word) - n Waitstates

Figure 17. 8-bit BOOT PROM 2x Store byte - n Waitstate

32 TSC695FL

Figure 18. DMA RAM load with or without Correctable Error and DMA RAM Store - 0 Waitstates1 (RAM fetch)2 (RAM fetch) 3 (DMA session) 4 (RAM fetch) 5 (RAM fetch)

Figure 19. Edge Triggered Interrupt Timing

34 TSC695FL

Figure 20. Halt Timing

Figure 21. External Error with Halt Timing

36 TSC695FL

Figure 22. Reset Timing

**Figure 23. External Error signaling with BUSERR* and BUSRDY***

4204C–AERO–05/05 TSC695FL Package Drawings 256-lead MQFP-F

4204C–AERO–05/05 TSC695FL 256-lead MQFP-F Pin Assignments Table 7. Pin Assignments Pin Signal Pin Signal Pin Signal Pin Signal

1 GPIINT 65 D[0] 129 RA[0] 193 DXFER

2 GPI[7] 66 RSIZE[1] 130 VCCO 194 MEXC

3 VCCO 67 RSIZE[0] 131 VSSO 195 VCCO

4 VSSO 68 RASI[3] 132 RAPAR 196 VSSO

5 GPI[6] 69 VCCO 133 RASPAR 197 RESET

6 GPI[5] 70 VSSO 134 DPAR 198 SYSRESET

7 GPI[4] 71 RASI[2] 135 VCCO 199 BA[1]

8 GPI[3] 72 RASI[1] 136 VSSO 200 BA[0]

9 VCCO 73 RASI[0] 137 SYSCLK 201 CB[6]

10 VSSO 74 RA[31] 138 TDO 202 CB[5]

11 GPI[2] 75 RA[30] 139 TRST

203 VCCO

12 GPI[1] 76 VCCO 140 TMS 204 VSSO

13 GPI[0] 77 VSSO 141 TDI 205 CB[4]

14 D[31] 78 RA[29] 142 TCK 206 CB[3]

15 D[30] 79 RA[28] 143 CLK2 207 CB[2]

16 VCCO 80 RA[27] 144 DRDY

208 CB[1]

17 VSSO 81 VCCO 145 DMAAS 209 VCCO

18 D[29] 82 VSSO 146 VCCO 210 VSSO

19 D[28] 83 RA[26] 147 VSSO 211 CB[0]

20 VCCI 84 RA[25] 148 DMAGNT

212 ALE

21 VSSI 85 RA[24] 149 EXMCS 213 VCCI

22 D[27] 86 VCCI 150 VCCI 214 VSSI

23 D[26] 87 VSSI 151 VSSI 215 PROM8

24 VCCO 88 VCCO 152 DMAREQ 216 ROMCS

25 VSSO 89 VSSO 153 BUSERR 217 MEMCS[9]

26 D[25] 90 RA[23] 154 BUSRDY 218 VCCO

27 D[24] 91 RA[22] 155 ROMWRT 219 VSSO

28 D[23] 92 RA[21] 156 NOPAR 220 MEMCS[8]

29 D[22] 93 VCCO 157 SYSHALT 221 MEMCS[7]

30 VCCO 94 VSSO 158 CPUHALT 222 MEMCS[6]

31 VSSO 95 RA[20] 159 VCCO 223 MEMCS[5]

32 D[21] 96 RA[19] 160 VSSO 224 MEMCS[4]

33 D[20] 97 RA[18] 161 SYSERR 225 MEMCS[3]

34 D[19] 98 VCCO 162 SYSAV 226 VCCO

35 D[18] 99 VSSO 163 EXTINT[4] 227 VSSO

36 VCCO 100 RA[17] 164 EXTINT[3] 228 MEMCS[2]

37 VSSO 101 RA[16] 165 EXTINT[2] 229 MEMCS[1]

38 D[17] 102 RA[15] 166 EXTINT[1] 230 MEMCS[0]

39 D[16] 103 VCCO 167 EXTINT[0] 231 VCCI

40 VCCI 104 VSSO 168 VCCI 232 VSSI

41 VSSI 105 RA[14] 169 VSSI 233 OE

42 D[15] 106 VCCI 170 EXTINTACK 234 VCCO

43 D[14] 107 VSSI 171 IUERR

235 VSSO

44 VCCO 108 RA[13] 172 VCCO 236 MEMWR

45 VSSO 109 RA[12] 173 VSSO 237 BUFFEN

46 D[13] 110 VCCO 174 CPAR 238 DDIR

47 D[12] 111 VSSO 175 TXA 239 VCCO

48 D[11] 112 RA[11] 176 RXA 240 VSSO

49 D[10] 113 RA[10] 177 RXB 241 DDIR

50 VCCO 114 RA[9] 178 TXB 242 MHOLD

51 VSSO 115 VCCO 179 IOWR 243 MDS

52 D[9] 116 VSSO 180 IOSEL[3] 244 WDCLK

53 D[8] 117 RA[8] 181 VCCO 245 IWDE

54 D[7] 118 RA[7] 182 VSSO 246 EWDINT

55 D[6] 119 RA[6] 183 IOSEL[2]

247 TMODE[1]

56 VCCO 120 VCCO 184 IOSEL[1] 248 TMODE[0]

57 VSSO 121 VSSO 185 IOSEL[0] 249 DEBUG

58 D[5] 122 RA[5] 186 WRT 250 INULL

59 D[4] 123 RA[4] 187 WE

251 DIA

60 D[3] 124 RA[3] 188 VCCO 252 VCCO

61 D[2] 125 VCCO 189 VSSO 253 VSSO

62 VCCO 126 VSSO 190 RD 254 FLUSH

63 VSSO 127 RA[2] 191 RLDSTO 255 INST

64 D[1] 128 RA[1] 192 LOCK 256 RTC

Table 7. Pin Assignments (Continued)

Table 8. Possible Order Entries TSC695FL-15MA 3.3V -55 to 125 15 MQFP-F256 Standard Mil.

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