T7906E_07 ATMEL | Alldatasheet
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Rev. D - 15 January, 2001 1 TS80C51U2 TS83C51U2 TS87C51U2 Double UART 8-bit CMOS Microcontroller 1. Description TS80C51U2 is high performance CMOS ROM, OTP and EPROM versions of the 80C51 CMOS single chip 8-bit microcontroller. The TS80C51U2 retains all features of the 80C51 with extended ROM/EPROM capacity (16 Kbytes), 256 bytes of internal RAM, a 7-source , 4-level interrupt system, an on-chip oscilator and three timer/counters. In addition, the TS80C51U2 has a second UART, enhanced functions on both UART, enhanced timer 2, a hardware watchdog timer, a dual data pointer, a baud rate generator and a X2 speed improvement mechanism. The fully static design of the TS80C51U2 allows to reduce system power consumption by bringing the clock frequency down to any value, even DC, without loss of data. The TS80C51U2 has 2 software-selectable modes of reduced activity for further reduction in power consumption. In the idle mode the CPU is frozen while the timers, the serial port and the interrupt system are still operating. In the power-down mode the RAM is saved and all other functions are inoperative. 2. Features
- 80C52 Compatible
- 8051 pin and instruction compatible
- Four 8-bit I/O ports
- Three 16-bit timer/counters
- 256 bytes scratchpad RAM
- High-Speed Architecture
- 40 MHz @ 5V, 30MHz @ 3V
- X2 Speed Improvement capability (6 clocks/ machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
- Second UART
- Baud Rate Generator
- Dual Data Pointer
- On-chip ROM/EPROM (16K-bytes)
- Programmable Clock Out and Up/Down Timer/ Counter 2
- Hardware Watchdog Timer (One-time enabled with Reset-Out)
- Asynchronous port reset
- Interrupt Structure with
- 7 Interrupt sources
- 4 level priority interrupt system
- Full duplex Enhanced UARTs
- Framing error detection
- Automatic address recognition
- Low EMI (inhibit ALE)
- Power Control modes
- Idle mode
- Power-down mode
- Power-off Flag
- Once mode (On-chip Emulation)
- Power supply: 4.5-5.5V, 2.7-5.5V
- Temperature ranges: Commercial (0 to 70oC) and Industrial (-40 to 85oC)
- Packages: PDIL40, PLCC44, VQFP44 1.4, CQPJ44 (window), CDIL40 (window) 3. The second UART In this document, UART_0 will make reference to the first UART (present in all Atmel Wireless & Microcontrollers C51 derivatives) and UART_1 will make reference to the second UART, only present in the TS80C51U2 part. The second UART (UART_1) can be seen as an alternate function of Port 1 (P1.2 or P1.6 for RXD1 and P1.3 or P1.7 for TXD1) or can be connected to (pin6 or pin12) and (pin28 or pin34) of 44-pin package (see Pin
2 Rev. D - 15 January, 2001 TS80C51U2 TS83C51U2 TS87C51U2 configuration). UART_1 is fully compliant with the first one allowing an internal baud rate generator to be the clock source. This common internal baud rate generator can be used independently by each UART or both as clock source allowing to program various speeds. The TS80C51U2 provides 7 sources of interrupt with four priority levels. UART_1 has a lower priority than Timer 2. The Serial Ports are full duplex meaning they can transmit and receive simultaneously. They are also receive buffered, meaning they can start reception of a second byte before a previously received byte has been read from the receive register. The Serial Port receive and transmit registers of UART_1 are both accessed at Special Function Register SBUF_1. Writing to SBUF_1 loads the transmit register and reading SBUF_1 accesses a physical separate receive register. The UART_1 port control and status is the Special Function Register SCON_1. This register contains not only the mode selection bit but also the 9th bit for transmit and receive (TB8_1 and RB8_1) and the serial port interrupt bits (TI_1 and RI_1). The automatic address recognition feature is enabled when multiprocessor communication is enabled. Implemented in hardware, automatic address recognition enhances the multiprocessor communication feature by allowing the Serial Port to examine address of each incoming frame and provides filtering capability. The UART_1 also comes with Frame error detection, similar to the UART_0.
Table 1. Memory size
- C51 core registers: ACC, B, DPH, DPL, PSW, SP, AUXR1
- I/O port registers: P0, P1, P2, P3
- Timer registers: T2CON, T2MOD, TCON, TH0, TH1, TH2, TMOD, TL0, TL1, TL2, RCAP2L, RCAP2H
- Serial I/O port registers for UART_0: SADDR_0, SADEN_0, SBUF_0, SCON_0
- Serial I/O port registers for UART_1: SADDR_1, SADEN_1, SBUF_1, SCON_1
- Baud Rate Generator registers: BRL, BDRCON, BDRCON_1
- Power and clock control registers: PCON
- HDW Watchdog Timer Reset: WDTRST, WDTPRG
- Interrupt system registers: IE, IP, IPH
- Others: AUXR, CKCON
Table 2. All SFRs with their address and their reset value
Rev. D - 15 January, 2001 5 TS80C51U2 TS83C51U2 TS87C51U2 6. Pin Configuration s 5 4 3 2 1 6 44 43 42 41 40 P1.4 P1.0/T2 P1.1/T2EX P1.3/TxD_1 P1.2/RxD_1 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA/VPP TxD_1 P2.7/A15 P2.5/A13 P2.6/A14 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 43 42 41 40 3944 38 37 36 35 34 P1.4 P1.0/T2 P1.1/T2EX P1.3/TxD_1 P1.2/RxD_1 VSS1/NIC* VCC P0.0/AD0 P0.2/AD2 P0.3/AD3 P0.1/AD1 P0.4/AD4 P0.6/AD6 P0.5/AD5 P0.7/AD7 ALE/PROG PSEN EA/VPP TxD_1 P2.7/A15 P2.5/A13 P2.6/A14 P1.5 P1.6/RxD_1 P1.7/TxD_1 RST P3.0/RxD_0 RxD_1 P3.1/TxD_0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0/A8 P2.1/A9 P2.2/A10 P2.3/A11 P2.4/A12 P1.5 P1.6/RxD_1 P1.7/TxD_1 RST P3.0/RxD_0 RxD_1 P3.1/TxD_0 P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P0.3/AD3 NIC* NIC* *NIC: No Internal Connection PLCC/CQPJ 44 VQFP44 1.4 18 19 20 21 22 23 24 25 26 27 28 12 13 14 15 16 17 18 19 20 21 22 P1.7/TxD_1 RST P3.0/RxD_0 P3.1/TxD_0 P1.3/TxD_1 P1.5 P3.2/INT0 P3.3/INT1 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS P2.0 / A8 P2.1 / A9 P2.2 / A10 P2.3 / A11 P2.4 / A12 P0.4 / A4 P0.6 / A6 P0.5 / A5 P0.7 / A7 ALE/PROG PSEN EA/VPP P2.7 / A15 P2.5 / A13 P2.6 / A14 P1.0 / T2 P1.1 / T2EX VCC P0.0 / A0 P0.1 / A1 P0.2 / A2 P0.3 / A3 PDIL/ CDIL40 P1.6/RxD_1 P1.4 P1.2/RxD_1 P3.4/T0 See “Alternate function on Port 1” on page 32 for accurate RxD_1 and TxD_1 pin location, depending on AUXR register configuration.
Table 3. Pin Description for 40/44 pin packages Vss1 1 39 I Optional Ground: Contact the Sales Office for ground connection. be polarized to Vcc or Vss in order to prevent any parasitic current consumption. which P0 outputs the code bytes. address byte during memory programming and verification. the UART_1 pins are alternate functins of P1 with two possible locations. that use 8-bit addresses (MOVX @Ri), port 2 emits the contents of the P2 SFR. features of the 80C51 family, as listed below.
programmed, EA will be internally latched on Reset. RxD_1 - 12 6 I Serial Input for UART_1. For 44-pin package only. selected. For 44-pin package only.
- TS80C51U2 Enhanced Features
- The X2 option.
- The second full duplex enhanced UART.
- The Baud Rate generator.
- The Dual Data Pointer.
- The Watchdog.
- The 4 level interrupt priority system.
- The power-off flag.
- The ONCE mode.
- The ALE disabling.
- Some enhanced features are also located in the UARTs and the timer 2.
7.1 X2 Feature
- Divide frequency crystals by 2 (cheaper crystals) while keeping same CPU power.
- Save power consumption while keeping same CPU power (oscillator power saving).
- Save power consumption by dividing dynamically operating frequency by 2 in operating and idle modes.
- Increase CPU power by 2 while keeping same crystal frequency. In order to keep the original C51 compatibility, a divider by 2 is inserted between the XTAL1 signal and the main clock input of the core (phase generator). This divider may be disabled by software.
7.1.1 Description
diagram. X2 bit is validated on XTAL1÷2 rising edge to avoid glitches when switching from X2 to STD mode. Figure 2. shows the mode switching waveforms. Figure 1. Clock Generation Diagram state machine: 6 clock cycles.
Figure 2. Mode Switching Waveforms 4800 baud rate will have 9600 baud rate.
Table 4. CKCON Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to select 12 clock periods per machine cycle (STD mode, FOSC =FXTAL /2). Set to select 6 clock periods per machine cycle (X2 mode, FOSC =FXTAL ).
7.2 Dual Data Pointer Register Ddptr
DPS = AUXR1/bit0 (See Table 5.) that allows the program code to switch between them (Refer to Figure 3). Figure 3. Use of Dual Pointer
Table 5. AUXR1: Auxiliary Register 1 value of the new bit will be 0, and its active value will be 1. The value read from a reserved bit is indeterminate. pointer and the other one as a "destination" pointer. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
0 DPS
Rev. D - 15 January, 2001 13 TS80C51U2 TS83C51U2 TS87C51U2 ASSEMBLY LANGUAGE ; Block move using dual data pointers ; Destroys DPTR0, DPTR1, A and PSW ; note: DPS exits opposite of entry state ; unless an extra INC AUXR1 is added 00A2 AUXR1 EQU 0A2H 0000 909000MOV DPTR,#SOURCE ; address of SOURCE 0003 05A2 INC AUXR1 ; switch data pointers 0005 90A000 MOV DPTR,#DEST ; address of DEST
0008 LOOP:
0008 05A2 INC AUXR1 ; switch data pointers 000A E0 MOVX A,@DPTR ; get a byte from SOURCE 000B A3 INC DPTR ; increment SOURCE address 000C 05A2 INC AUXR1 ; switch data pointers 000E F0 MOVX @DPTR,A ; write the byte to DEST 000F A3 INC DPTR ; increment DEST address 0010 70F6 JNZ LOOP ; check for 0 terminator 0012 05A2 INC AUXR1 ; (optional) restore DPS INC is a short (2 bytes) and fast (12 clocks) way to manipulate the DPS bit in the AUXR1 SFR. However, note that the INC instruction does not directly force the DPS bit to a particular state, but simply toggles it. In simple routines, such as the block move example, only the fact that DPS is toggled in the proper sequence matters, not its actual value. In other words, the block move routine works the same whether DPS is '0' or '1' on entry. Observe that without the last instruction (INC AUXR1), the routine will exit with DPS in the opposite state.
7.3 Timer 2
The timer 2 in theTS80C51U2 is compatible with the timer 2 in the 80C52. as the timer clock input. Setting TR2 allows TL2 to be incremented by the selected input. bit Microcontroller Hardware description. Capture and Baud Rate Generator Modes.
- Auto-reload mode with up or down counter
- Programmable clock-output
7.3.1 Auto-Reload Mode
Figure 4. In this mode the T2EX pin controls the direction of count. into the timer registers TH2 and TL2. does not generate any interrupt. This bit can be used to provide 17-bit resolution.
Figure 4. Auto-Reload Mode Up/Down Counter (DCEN = 1)
7.3.2 Programmable Clock-Output
input clock increments TL2 at frequency FOSC /2. The timer repeatedly counts to overflow from a loaded value. OSC /216) to 4 MHz (FOSC /4). The generated clock signal is brought out to T2 pin (P1.0).
- Set T2OE bit in T2MOD register.
- Clear C/T2 bit in T2CON register.
- Determine the 16-bit reload value from the formula and enter it in RCAP2H/RCAP2L registers.
- Enter a 16-bit initial value in timer registers TH2/TL2. It can be the same as the reload value or a different one depending on the application. (DOWN COUNTING RELOAD V ALUE) C/T2 TF2 TR2 EXF2 TH2 (8-bit) TL2 (8-bit) RCAP2H (8-bit) RCAP2L (8-bit) FFh (8-bit) FFh (8-bit) TOGGLE (UP COUNTING RELOAD V ALUE) TIMER 2 INTERRUPT XTAL1 :12 FOSCFXTAL T2CONreg T2CONreg T2CONreg T2CONreg T2EX: if DCEN=1, 1=UP if DCEN=1, 0=DOWN if DCEN = 0, up counting (:6 in X2 mode) Clock OutFrequency– F osc
- To start the timer, set TR2 run control bit in T2CON register. It is possible to use timer 2 as a baud rate generator and a clock generator simultaneously. For this configuration, the baud rates and clock frequencies are not independent since both functions use the values in the RCAP2H and RCAP2L registers.
Figure 5. Clock-Out Mode C/
Table 6. T2CON Register
7 TF2
Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0.
6 EXF2
Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled.
5 RCLK_0
Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3.
4 TCLK_0
Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3.
3 EXEN2
Clear to ignore events on T2EX pin for timer 2 operation.
2 TR2
1 C/T2#
Clear for timer operation (input from internal clock system: FOSC ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode.
0 CP/RL2#
If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.
Table 7. T2MOD Register The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
1 T2OE
Clear to program P1.0/T2 as clock input or I/O port. Set to program P1.0/T2 as clock output.
0 DCEN
Clear to disable timer 2 as up/down counter. Set to enable timer 2 as up/down counter.
7.4 TS80C51U2 Serial I/O Ports enhancements
The serial I/O ports in the TS80C51U2 are compatible with the serial I/O port in the 80C52.
- Framing error detection
- Automatic address recognition As these improvements apply to both UART, most of the time in the following lines, there won’t be any reference to UART_0 or UART_1, but only to UART, generally speaking. Idem for the bits in registers.
7.4.1 Framing Error Detection
bit error detection feature, set SMOD0 bit in PCON register (See Figure 6). Figure 6. Framing Error Block Diagram is not found, the Framing Error bit (FE) in SCON register (See Table 8.) bit is set.
RI rises on stop bit instead of the last data bit (See Figure 7. and Figure 8.). Figure 7. UART Timings in Mode 1 Figure 8. UART Timings in Modes 2 and 3
7.4.2 Automatic Address Recognition
feature is enabled (SM2 bit in SCON register is set). the CPU is not interrupted by command frames addressed to other devices. device’s address and is terminated by a valid stop bit. To support automatic address recognition, a device is identified by a given address and a broadcast address. register in mode 0 has no effect).
7.4.3 Given Address
Rev. D - 15 January, 2001 21 TS80C51U2 TS83C51U2 TS87C51U2 illustrates how a given address is formed. To address a device by its individual address, the SADEN mask byte must be1111 1111b. For example: SADDR 0101 0110b SADEN11111100b Given 0101 01XXb The following is an example of how to use given addresses to address different slaves: Slave A: SADDR 1111 0001b SADEN11111010b Given 1111 0X0Xb Slave B: SADDR 1111 0011b SADEN11111001b Given 1111 0XX1b Slave C: SADDR 1111 0010b SADEN11111101b Given 1111 00X1b The SADEN byte is selected so that each slave may be addressed separately. For slave A, bit 0 (the LSB) is a don’t-care bit; for slaves B and C, bit 0 is a 1. To communicate with slave A only, the master must send an address where bit 0 is clear (e.g.1111 0000b). For slave A, bit 1 is a 1; for slaves B and C, bit 1 is a don’t care bit. To communicate with slaves B and C, but not slave A, the master must send an address with bits 0 and 1 both set (e.g.1111 0011b). To communicate with slaves A, B and C, the master must send an address with bit 0 set, bit 1 clear, and bit 2 clear (e.g.1111 0001b).
7.4.4 Broadcast Address
A broadcast address is formed from the logical OR of the SADDR and SADEN registers with zeros defined as don’t-care bits, e.g.: SADDR 0101 0110b SADEN 1111 1100b Broadcast =SADDR OR SADEN 1111 111Xb The use of don’t-care bits provides flexibility in defining the broadcast address, however in most applications, a broadcast address is FFh. The following is an example of using broadcast addresses: Slave A: SADDR 1111 0001b SADEN11111010b Broadcast 1111 1X11b, Slave B: SADDR 1111 0011b SADEN11111001b Broadcast 1111 1X11B, Slave C: SADDR= 1111 0010b SADEN11111101b Broadcast 1111 1111b For slaves A and B, bit 2 is a don’t care bit; for slave C, bit 2 is set. To communicate with all of the slaves, the master must send an address FFh. To communicate with slaves A and B, but not slave C, the master can send and address FBh.
7.4.5 Reset Addresses
On reset, the SADDR and SADEN registers are initialized to 00h, i.e. the given and broadcast addresses areXXXX XXXXb(all don’t-care bits). This ensures that the serial port will reply to any address, and so, that it is backwards compatible with the 80C51 microcontrollers that do not support automatic address recognition.
7.4.6 Baud Rate Selection for UART0_0 for mode 1 and 3
Figure 9. Baud Rate selection
7.4.7 Baud Rate Selection for UART1_1 for mode 1 and 3
The Baud Rate Generator for transmit and receive clocks can be selected separately via the BDRCON_1 register. Figure 10. Baud Rate selection
7.4.8 Baud Rate selection table for UART_0
7.4.9 Baud Rate selection table for UART_1
7.4.10 Internal Baud Rate Generator (BRG)
Figure 11. Internal Baud Rate
0 X 0 1 Timer 1 INT_BRG_0
1 X 0 1 Timer 2 INT_BRG_0
0 X 0 1 Timer 1 INT_BRG_1
1 X 0 1 Timer 2 INT_BRG_1
24 Rev. D - 15 January, 2001 TS80C51U2 TS83C51U2 TS87C51U2
- for UART_1
- for UART_0 Example of computed value when X2=1, SMOD1=1, SPD=1 Example of computed value when X2=0, SMOD1=0, SPD=0 The baud rate generator can be used for mode 1 or 3 (refer to figures 9 and 10), but also for mode 0 for both UARTs, thanks to the bit SRC located in BDRCON register (Table 12) Baud Rates FXTAL = 16.384 MHz FXTAL = 24MHz BRL Error (%) BRL Error (%) 115200 247 1.23 243 0.16 57600 238 1.23 230 0.16 38400 229 1.23 217 0.16 28800 220 1.23 204 0.16 19200 203 0.63 178 0.16 9600 149 0.31 100 0.16 4800 43 1.23 - - Baud Rates FOSC = 16.384 MHz FOSC = 24MHz BRL Error (%) BRL Error (%) 4800 247 1.23 243 0.16 2400 238 1.23 230 0.16 1200 220 1.23 202 3.55 600 185 0.16 152 0.16 Baud_Rate = 2SMOD1_1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)] (BRL) = 256 - 2SMOD1_1 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x Baud_Rate Baud_Rate = 2SMOD1_0 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x [256 - (BRL)] (BRL) = 256 - 2SMOD1_0 x 2X2 x FXTAL 2 x 2 x 6(1-SPD) x 16 x Baud_Rate
Rev. D - 15 January, 2001 25 TS80C51U2 TS83C51U2 TS87C51U2
7.5 UARTs registers
SADEN_0 - Slave Address Mask Register for UART_0 (B9h) Reset Value = 0000 0000b SADEN_1 - Slave Address Mask Register for UART_1 (BAh) Reset Value = 0000 0000b SADDR_0 - Slave Address Register for UART_0 (A9h) Reset Value = 0000 0000b SADDR_1 - Slave Address Register for UART_1 (AAh) Reset Value = 0000 0000b SBUF_0 - Serial Buffer Register for UART_0 (99h) Reset Value = XXXX XXXXb SBUF_1 - Serial Buffer Register for UART_1 (C1h) Reset Value = XXXX XXXXb BRL - Baud Rate Reload Register for the internal baud rate generator, UART_0 and UART_1 (9Ah) Reset Value = 0000 0000b 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
Table 8. SCON Register
7 FE_0
Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection.
6 SM1_0
5 SM2_0
Clear to disable multiprocessor communication feature.
4 REN_0
Clear to disable serial reception. Set to enable serial reception.
3 TB8_0
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_0. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
2 RB8_0
Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1 TI_0
Clear to acknowledge interrupt.
0 RI_0
Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Table 9. SCON Register
7 FE_1
Clear to reset the error state, not cleared by a valid stop bit. Set by hardware when an invalid stop bit is detected. Refer to SM1 for serial port mode selection.
6 SM1_1
5 SM2_1
Clear to disable multiprocessor communication feature.
4 REN_1
Clear to disable serial reception. Set to enable serial reception.
3 TB8_1
Transmitter Bit 8 / Ninth bit to transmit in modes 2 and 3 for UART_1. Clear to transmit a logic 0 in the 9th bit. Set to transmit a logic 1 in the 9th bit.
2 RB8_1
Cleared by hardware if 9th bit received is a logic 0. Set by hardware if 9th bit received is a logic 1. In mode 1, if SM2 = 0, RB8 is the received stop bit. In mode 0 RB8 is not used.
1 TI_1
Clear to acknowledge interrupt.
0 RI_1
Clear to acknowledge interrupt. Set by hardware at the end of the 8th bit time in mode 0, see Figure 7. and Figure 8. in the other modes.
Table 10. T2CON Register Must be cleared by software. Set by hardware on timer 2 overflow, if RCLK = 0 and TCLK = 0. Set when a capture or a reload is caused by a negative transition on T2EX pin if EXEN2=1. When set, causes the CPU to vector to timer 2 interrupt routine when timer 2 interrupt is enabled. Clear to use timer 1 overflow as receive clock for serial port in mode 1 or 3. Set to use timer 2 overflow as receive clock for serial port in mode 1 or 3. Clear to use timer 1 overflow as transmit clock for serial port in mode 1 or 3. Set to use timer 2 overflow as transmit clock for serial port in mode 1 or 3. Clear to ignore events on T2EX pin for timer 2 operation. Clear for timer operation (input from internal clock system: FOSC ). Set for counter operation (input from T2 input pin, falling edge trigger). Must be 0 for clock out mode. If RCLK=1 or TCLK=1, CP/RL2# is ignored and timer is forced to auto-reload on timer 2 overflow. Clear to auto-reload on timer 2 overflows or negative transitions on T2EX pin if EXEN2=1. Set to capture on negative transitions on T2EX pin if EXEN2=1.
Table 11. PCON Register Power-off flag reset value will be 1 only after a power on (cold reset). A warm reset doesn’t affect the value of this bit.
7 SMOD1_0 Serial port Mode bit 1 for UART_0
Set to select double baud rate in mode 1, 2 or 3.
6 SMOD0_0
Clear to select SM0_0 bit in SCON_0 register. Set to to select FE_0 bit in SCON_0 register. The value read from this bit is indeterminate. Do not set this bit.
4 POF
Clear to recognize next reset type. Set by hardware when VCC rises from 0 to its nominal voltage. Can also be set by software.
3 GF1
Cleared by user for general purpose usage. Set by user for general purpose usage.
2 GF0
Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode.
0 IDL
Clear by hardware when interrupt or reset occurs.
Table 12. BDRCON Register The value read from this bit is indeterminate. Do not set this bit.
4 BRR
Clear to stop the internal Baud Rate Generator. Set to start the internal Baud Rate Generator.
3 TBCK_0
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator.
2 RBCK_0
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator. Set to select internal Baud Rate Generator.
1 SPD
Clear to select the SLOW Baud Rate Generator. Set to select the FAST Baud Rate Generator.
0 SRC
Clear to select FOSC /12 as the Baud Rate Generator (FOSC /6 in X2 mode). Set to select the internal Baud Rate Generator for UARTs in mode 0..
Table 13. BDRCON_1 Register
7 SMOD1_1 Serial port Mode bit 1 for UART_1
Set to select double baud rate, in mode 1, 2 and 3.
6 SMOD0_1
Clear to select SM0_1 bit in SCON_1 register.. Set to to select FE_1 bit in SCON_1 register.
5 RCLK_1
4 TCLK_1
Set to Select Timer 2 as the Transmit Baud Rate Generator for the UART_1.
3 TBCK_1
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator, for Tx. Set to select internal Baud Rate Generator for Tx.
2 RBCK_1
Clear to select Timer 1 or Timer 2 for the Baud Rate Generator for Rx. Set to select internal Baud Rate Generator for Rx. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit.
7.6 Alternate function on Port 1
for 44-pin package are no more valid. Table 14. AUXR Register
7 M1UA_1 Multiplex I/Os of UART_1 bit 1
This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins.
6 M0UA_1
This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins. 0 0 UART_1 pins are disabled. 0 1 UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only. 1 0 UART_1 pins are alternate functions of P1 located at P1.2 and P1.3. 1 1 UART_1 pins are alternate functions of P1 located at P1.6 and P1.7. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches.
7.7 Interrupt System
(timers 0, 1 and 2) and the two serial port interrupts. These interrupts are shown in Figure 12. Figure 12. Interrupt Control System a bit in the Interrupt Priority register (See Table 17.) and in the Interrupt Priority High register (See Table 18.). shows the bit values and priority levels associated with each combination.
Table 15. Priority Level Bit Values A low-priority interrupt can be interrupted by a high priority interrupt, but not by another low-priority interrupt. A high-priority interrupt can’t be interrupted by any other interrupt source. Table 16. IE Register Clear to disable all interrupts. Set to enable all interrupts.
6 ES_1
Clear to disable serial port interrupt. Set to enable serial port interrupt.
5 ET2
Clear to disable timer 2 overflow interrupt. Set to enable timer 2 overflow interrupt.
4 ES_0
Clear to disable serial port interrupt. Set to enable serial port interrupt.
3 ET1
Clear to disable timer 1 overflow interrupt. Set to enable timer 1 overflow interrupt.
2 EX1
Clear to disable external interrupt 1. Set to enable external interrupt 1.
1 ET0
Clear to disable timer 0 overflow interrupt. Set to enable timer 0 overflow interrupt.
0 EX0
Clear to disable external interrupt 0. Set to enable external interrupt 0.
Table 17. IP Register The value read from this bit is indeterminate. Do not set this bit.
6 PS_1 Serial port Priority bit for UART_1
Refer to PSH for priority level.
5 PT2 Timer 2 overflow interrupt Priority bit
Refer to PT2H for priority level.
4 PS_0 Serial port Priority bit for UART_0
Refer to PSH for priority level.
3 PT1 Timer 1 overflow interrupt Priority bit
Refer to PT1H for priority level.
2 PX1 External interrupt 1 Priority bit
Refer to PX1H for priority level.
1 PT0 Timer 0 overflow interrupt Priority bit
Refer to PT0H for priority level.
0 PX0 External interrupt 0 Priority bit
Refer to PX0H for priority level.
Table 18. IPH Register The value read from this bit is indeterminate. Do not set this bit.
6 PSH_1
5 PT2H
4 PSH_0
3 PT1H
2 PX1H
1 PT0H
0 PX0H
7.8 Idle mode
An instruction that sets PCON.0 causes that to be the last instruction executed before going into the Idle mode. at the time Idle was activated. ALE and PSEN hold at logic high levels. be executed will be the one following the instruction that put the device into idle. terminated by an interrupt, the interrupt service routine can examine the flag bits. the hardware reset needs to be held active for only two machine cycles (24 oscillator periods) to complete the reset.
7.9 Power-Down Mode
To save maximum power, a power-down mode can be invoked by software (Refer to 7.4.6, PCON register). instruction executed. The internal RAM and SFRs retain their value until the power-down mode is terminated. is restored to its normal operating level and must be held active long enough for the oscillator to restart and stabilize. and configured as level or edge sensitive interrupt input. Holding the pin low restarts the oscillator but bringing the pin high completes the exit as detailed in Figure 13. that put TS80C51U2 into power-down mode. Figure 13. Power-Down Exit Waveform Exit from power-down by either reset or external interrupt does not affect the internal RAM content. PD and IDL bits are cleared and idle mode is not entered.
Table 19. The state of ports during idle and power-down modes
- Port 0 can force a "zero" level. A "one" Level will leave port floating.
7.10 Hardware Watchdog Timer
WDT overflows, it will drive an output RESET HIGH pulse at the RST-pin.
7.10.1 Using the WDT
WDT is enabled, the user needs to service it by writing to 01EH and 0E1H to WDTRST to avoid WDT overflow. the time required to prevent a WDT reset. 16ms to 2s @ FOSC = 12MHz. To manage this feature, refer to WDTPRG register description, Table 21. (SFR0A7h). Table 20. WDTRST Register Write only, this SFR is used to reset/enable the WDT by writing 01EH then 0E1H in sequence.
Table 21. WDTPRG Register
7.10.2 WDT during Power Down and Idle
resetting the device while the interrupt pin is held low, the WDT is not started until the interrupt is pulled high. It is suggested that the WDT be reset during the interrupt service routine. WDT just before entering powerdown. Do not try to set or clear this bit.
2 S2 WDT Time-out select bit 2
1 S1 WDT Time-out select bit 1
0 S0 WDT Time-out select bit 0
7.11 ONCE TM Mode (ON Chip Emulation)
- Pull ALE low while the device is in reset (RST high) andPSEN is high.
- Hold ALE low as RST is deactivated. While the TS80C51U2 is in ONCE mode, an emulator or test CPU can be used to drive the circuit Table 26. shows the status of the port pins during ONCE mode. Normal operation is restored when normal reset is applied.
Table 22. External Pin Status during ONCE Mode
7.12 Power-Off Flag
The power-off flag allows the user to distinguish between a “cold start” reset and a “warm start” reset. the device and could be generated for example by an exit from power-down. Table 23. PCON Register Set to select double baud rate in mode 1, 2 or 3. Clear to select SM0_0 bit in SCON_0 register. Set to to select FE_0 bit in SCON_0 register. The value read from this bit is indeterminate. Do not set this bit. Clear to recognize next reset type. CC rises from 0 to its nominal voltage. Can also be set by software. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by user for general purpose usage. Set by user for general purpose usage. Cleared by hardware when reset occurs. Set to enter power-down mode. Clear by hardware when interrupt or reset occurs.
7.13 Reduced EMI Mode
signal can be disabled by setting AO bit. Table 24. AUXR Register This bit is used in conjunction with M0UA_1 bit to specify where are multiplexed UART_1 pins. This bit is used in conjunction with M1UA_1 bit bit to specify where are multiplexed UART_1 pins. 0 0 UART_1 pins are disabled. 0 1 UART_1 pins are located on pins (6, 28) or (12, 34) for 44-package only. 1 0 UART_1 pins are alternate functions of P1 located at P1.2 and P1.3. 1 1 UART_1 pins are alternate functions of P1 located at P1.6 and P1.7. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. The value read from this bit is indeterminate. Do not set this bit. Clear to restore ALE operation during internal fetches. Set to disable ALE operation during internal fetches.
8.1 ROM Structure
8.2 ROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
8.2.1 Encryption Array
the encryption array in the unprogrammed state, will return the code in its original, unmodified form. should be programmed with random values. This will ensure program protection.
8.2.2 Program Lock Bits
8.2.3 Signature bytes
8.2.4 Verify Algorithm
Table 25. Program Lock bits
1 U U U
2 P U U MOVC instruction executed from external program memory are disabled from fetching
code bytes from internal memory,EA is sampled and latched on reset.
9.1 EPROM Structure
9.2 EPROM Lock System
The program Lock system, when programmed, protects the on-chip program against software piracy.
9.2.1 Encryption Array
the encryption array in the unprogrammed state, will return the code in its original, unmodified form. should be programmed with random values. This will ensure program protection.
9.2.2 Program Lock Bits
WARNING: Security level 2 and 3 should only be programmed after EPROM and Core verification. Table 26. Program Lock bits
2 P U U
programming of the EPROM is disabled. 3 U P U Same as 2, also verify is disabled. 4 U U P Same as 3, also external execution is disabled.
9.2.3 Signature bytes
9.3 EPROM Programming
9.3.1 Set-up modes
set-up modes (See Figure 14.). Control and program signals must be held at the levels indicated in Table 27.
9.3.2 Definition of terms
Program Signals:ALE/ PROG, EA/VPP. Table 27. EPROM Set-Up Modes
Figure 14. Set-Up Modes Configuration
9.3.3 Programming Algorithm
applied during byte programming from 25 to 1.
- Step 1: Activate the combination of control signals.
- Step 2: Input the valid address on the address lines.
- Step 3: Input the appropriate data on the data lines.
- Step 4: RaiseEA/VPP from VCC to VPP (typical 12.75V).
- Step 5: Pulse ALE/PROG once.
- Step 6: LowerEA/VPP from VPP to VCC Repeat step 2 through 6 changing the address and data for the entire array or until the end of the object file is reached (See Figure 15.).
9.3.4 Verify algorithm
of the programmed array will ensure reliable programming of the TS87C51U2. P 2.7 is used to enable data output.
- Step 1: Activate the combination of program and control signals.
- Step 2: Input the valid address on the address lines.
- Step 3: Read data on the data lines. Repeat step 2 through 3 changing the address for the entire array verification (See Figure 15.) The encryption array cannot be directly verified. Verification of the encryption array is done by observing that the code array is well encrypted. +5V VCC P0.0-P0.7 P1.0-P1.7 P2.0-P2.5 VSS GND D0-D7 A0-A7 A8-A13 RST EA/VPP ALE/ PR OG PSEN P2.6 P2.7 P3.3 P3.7 P3.6 XTAL14 to 6 MHz CONTROL SIGNALS* PROGRAM SIGNALS* * See Table 31. for proper value on these inputs
Figure 15. Programming and Verification Signal’s Waveform
9.4 EPROM Erasure (Windowed Packages Only)
Erasure leaves all the EPROM cells in a 1’s state (FF).
9.4.1 Erasure Characteristics
of about 25 mm, should be sufficient. An exposure of 1 hour is recommended with most of standard erasers. label be placed over the window.
- shows the content of the signature byte for the TS83/87C51U2.
Table 28. Signature Bytes Content
50 Rev. D - 15 January, 2001 TS80C51U2 TS83C51U2 TS87C51U2 11. Electrical Characteristics
11.1 Absolute Maximum Ratings(1)
Ambiant Temperature Under Bias: C = commercial 0 °Ct o7 0°C I = industrial -40 °Ct o8 5°C Storage Temperature -65 °Ct o+1 5 0°C Voltage on VCC to VSS - 0 . 5Vt o+7V Voltage on VPP to VSS - 0 . 5Vt o+1 3V Voltage on Any Pin to VSS - 0 . 5Vt oVCC + 0.5 V Power Dissipation 1 W (2) NOTES 1. Stresses at or above those listed under “ Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. 2. This value is based on the maximum allowable die temperature and the thermal resistance of the package.
11.2 Power consumption measurement
Since the introduction of the first C51 devices, every manufacturer made operating Icc measurements under reset, which made sense for the designs were the CPU was running under reset. In Atmel Wireless & Microcontrollers new devices, the CPU is no more active during reset, so the power consumption is very low but is not really representative of what will happen in the customer system. That’s why, while keeping measurements under Reset, Atmel Wireless & Microcontrollers presents a new way to measure the operating Icc: Using an internal test ROM, the following code is executed: Label: SJMP Label (80 FE) Ports 1, 2, 3 are disconnected, Port 0 is tied to FFh, EA = Vcc, RST = Vss, XTAL2 is not connected and XTAL1 is driven by the clock. This is much more representative of the real operating Icc.
11.3 DC Parameters for Standard Voltage
Table 29. DC Parameters in Standard Voltage
11.4 DC Parameters for Low Voltage
Table 30. DC Parameters for Low Voltage
- I CC under reset is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns (see Figure 20.), VIL = VSS + 0.5 V ,
- Idle ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH ,TCHCL = 5 ns, VIL =V SS + 0.5 V , VIH =V CC - 0.5 V; XTAL2
N.C; Port 0 = VCC ;EA = RST = VSS (see Figure 18.).
- Power Down I CC is measured with all output pins disconnected;EA = VSS, PORT 0 = VCC ; XTAL2 NC.; RST = VSS (see Figure 19.).
- Capacitance loading on Ports 0 and 2 may cause spurious noise pulses to be superimposed on the VOL s of ALE and Ports 1 and 3. The noise is
cases (capacitive loading 100pF), the noise pulse on the ALE line may exceed 0.45V with maxi VOL peak 0.6V . A Schmitt Trigger use is not necessary.
- Typicals are based on a limited number of samples and are not guaranteed. The values listed are at room temperature and 5V .
- Under steady state (non-transient) conditions, IOL must be externally limited as follows:
If IOL exceeds the test condition, VOL may exceed the related specification. Pins are not guaranteed to sink current greater than the listed test conditions.
- For other values, please contact your sales office.
- Operating ICC is measured with all output pins disconnected; XTAL1 driven with TCLCH , TCHCL = 5 ns (see Figure 20.), VIL = VSS + 0.5 V ,
higher if a crystal oscillator is used. Measurements are made with OTP products when possible, which is the worst case. Figure 16. ICC Test Condition, under reset
0.15 Freq
All other pins are disconnected.
11.5 AC Parameters
11.5.1 Explanation of the AC Symbols
a list of all the characters and what they stand for. AVLL = Time for Address Valid to ALE Low. TLLPL = Time for ALE Low to PSEN Low. TA =0t o+ 7 0°C (commercial temperature range); VSS =0V ;V CC =5V ± 10%; -M and -V ranges. TA = -40°Ct o+ 8 5°C (industrial temperature range); VSS =0V ; V CC =5V ± 10%; -M and -V ranges. TA =0t o+ 7 0°C (commercial temperature range); VSS =0V ;2 . 7V<V CC < 5.5 V; -L range. TA = -40°Ct o+ 8 5°C (industrial temperature range); VSS =0V ;2 . 7V<V CC < 5.5 V; -L range. Table 31. gives the maximum applicable load capacitance for Port 0, Port 1, 2 and 3, and ALE andPSEN signals. Table 31. Load Capacitance versus speed range, in pF Table 33., Table 36. and Table 39. give the description of each AC symbols. Table 34., Table 37. and Table 40. give for each range the AC parameter. Table 32. Max frequency for derating formula regarding the speed grade
11.5.2 External Program Memory Characteristics
Table 34. AC Parameters for Fix Clock Table 33. Symbol Description
40 MHz
30 MHz
20 MHz
Table 35. AC Parameters for a Variable Clock: derating formula
11.5.3 External Program Memory Read Cycle
Figure 21. External Program Memory Read Cycle
12 TCLCL
11.5.4 External Data Memory Characteristics
Table 36. Symbol Description
Table 37. AC Parameters for a Fix Clock
Table 38. AC Parameters for a Variable Clock: derating formula
11.5.5 External Data Memory Write Cycle
Figure 22. External Data Memory Write Cycle
11.5.6 External Data Memory Read Cycle
Figure 23. External Data Memory Read Cycle
11.5.7 Serial Port Timing - Shift Register Mode
Table 40. AC Parameters for a Fix Clock Table 39. Symbol Description
Table 41. AC Parameters for a Variable Clock: derating formula
11.5.8 Shift Register Timing Waveforms
Figure 24. Shift Register Timing Waveforms
11.5.9 EPROM Programming and Verification Characteristics
11.5.10 EPROM Programming and Verification Waveforms
Figure 25. EPROM Programming and Verification Waveforms Table 42. EPROM Programming Parameters
11.5.11 External Clock Drive Characteristics (XTAL1)
11.5.12 External Clock Drive Waveforms
Figure 26. External Clock Drive Waveforms
11.5.13 AC Testing Input/Output Waveforms
Figure 27. AC Testing Input/Output Waveforms are made at VIH min for a logic “1” and VIL max for a logic “0”.
11.5.14 Float Waveforms
Figure 28. Float Waveforms Table 43. AC Parameters
to float when a 100 mV change from the loaded VOH /VOL level occurs. IOL /IOH ≥± 20mA.
11.5.15 Clock Waveforms
Valid in normal clock mode. In X2 mode XTAL2 signal must be changed to XTAL2 divided by two. Figure 29. Clock Waveforms are incorporated in the AC specifications.
Table 44. Maximum Clock Frequency
40 MHz, X1 mode
30 MHz, X2 mode
30 MHz, X1 mode
20 MHz, X2 mode
Ceramic packages (J, K) are available for prototyping, not for volume production.
Table 45. Possible Ordering Entries
- -Ex for samples
- Tape and Reel available for B and E packages
- Dry pack mandatory for E packages TS80C51U2 ROMless TS83C51U2zzz 16K ROM TS87C51U2 16K OTP -VIA X X X -VIB X X X -VIE X X X -LIA X X X -LIB X X X -LIE X X X -EA X X -EB X X -EE X X -EJ X -EK X