9Q512K32 AEROFLEX | Alldatasheet
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Technical content
FEATURES
q 25ns maximum (5 volt supply) address access time q Asynchronous operation for compatible with industry standard 512K x 8 SRAMs q TTL compatible inputs and output levels , three-state bidirectional data bus q Typical radiation performance - Total dose: 50krads - SEL Immune > 80 MeV-cm2/mg - LETTH(0.25) = >10 MeV-cm 2/mg - Saturated Cross Section (cm2) per bit, 5.0E-9 - <1E-8 errors/bit-day, Adams 90% geosynchronous heavy ion q Packaging options: - 68-lead dual cavity ceramic quad flatpack (CQFP) - (weight 7.37 grams) q Standard Microcircuit Drawing 5962-01511 - QML T and Q compliant part INTRODUCTION The QCOTSTM UT9Q512K32 Quantified Commercial Off-the-Shelf product is a high-performance 2M byte (16Mbit) CMOS static RAM multi-chip module (MCM), organized as four individual 524,288 x 8 bit SRAMs with a common output enable. Memory expansion is provided by an active LOW chip enable ( E n), an active LOW output enable (G), and three-state drivers. This device has a power- down feature that reduces power consumption by more than 90% when deselected . Writing to each memory is accomplished by taking chip enable (En) input LOW and write enable (Wn) inputs LOW. Data on the eight I/O pins (DQ0 through DQ7) is then written into the location specified on the address pins (A 0 through A18). Reading from the device is accomplished by taking chip enable (En) and output enable (G) LOW while forcing write enable (Wn) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The input/output pins are placed in a high impedance state when the device is deselected ( En HIGH), the outputs are disabled (G HIGH), or during a write operation ( En LOW and Wn LOW). Perform 8, 16, 24 or 32 bit accesses by making Wn along with En a common input to any combination of the discrete memory die. Figure 1. UT9Q512K32 SRAM Block Diagram
by a write terminated by Wn going high, with En still active. initiated by Wn, and by tETWH when the write is initiated by En. pins DQ(7:0) to avoid bus contention. operation in a limited radiation environment. Table 2. Radiation Hardness
- The SRAM will not latchup during radiation exposure under recommended
- 90% worst case particle environment, Geosynchronous orbit, 100 mils of
ABSOLUTE MAXIMUM RATINGS 1 (Referenced to VSS) Notes: 1. Stresses outside the listed absolute maximum ratings may cause permanent damage to the device. This is a stress rating only, and functional operation of the device at these or any other conditions beyond limits indicated in the operational sections of this specification is not recommended. E xposure to absolute maximum rating conditions for extended periods may affect device reliability and performance. 2. Maximum junction temperature may be increased to +175 °C during burn-in and steady-static life. 3. Test per MIL-STD-883, Method 1012. RECOMMENDED OPERATING CONDITIONS SYMBOL PARAMETER LIMITS VDD DC supply voltage -0.5 to 7.0V VI/O Voltage on any pin -0.5 to 7.0V TSTG Storage temperature -65 to +150 °C PD Maximum power dissipation 1.0W (per byte) TJ Maximum junction temperature 2 +150°C Θ JC Thermal resistance, junction-to-case 3 10°C/W II DC input current ±10 mA SYMBOL PARAMETER LIMITS VDD Positive supply voltage 4.5 to 5.5V TC Case temperature range -40 to +125°C VIN DC input voltage 0V to VDD
DC ELECTRICAL CHARACTERISTICS (Pre/Post-Radiation)* Notes: * Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019 . 1. Measured only for initial qualification and after process or design changes that could affect input/output capacitance. 2. Supplied as a design limit but not guaranteed or tested. 3. Not more than one output may be shorted at a time for maximum duration of one second . SYMBOL PARAMETER CONDITION MIN MAX UNIT VIH High-level input voltage 2.0 V VIL Low-level input voltage 0.8 V VOL1 Low-level output voltage IOL = 8mA, VDD =4.5V 0.4 V VOL2 Low-level output voltage IOL = 200µA,VDD =4.5V 0.08 V VOH 1 High-level output voltage IOH = -4mA,V DD =4.5V 2.4 V VOH 2 High-level output voltage IOH = 200µA,VDD =4.5V 3.0 V CIN
1 Input capacitance ƒ = 1MHz @ 0V 32 pF
CIO1 Bidirectional I/O capacitance ƒ = 1MHz @ 0V 16 pF IIN Input leakage current VIN = VDD and VSS, VDD = VDD (max) -2 2 µA IOZ Three-state output leakage current VO = VDD and VSS VDD = VDD (max) G = VDD (max) -2 2 µA IOS2, 3 Short-circuit output current VDD = VDD (max), VO = VDD VDD = VDD (max), VO = 0V -90 90 mA IDD (OP) Supply current operating @ 1MHz (per byte) Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) 125 mA IDD1(OP) Supply current operating @40MHz (per byte) Inputs: VIL = 0.8V, VIH = 2.0V IOUT = 0mA VDD = VDD (max) 180 mA IDD2(SB) Supply current standb y @0MHz (per byte) Inputs: VIL = VSS IOUT = 0mA E1 = VDD - 0.5, VDD = VDD (max) VIH = VDD - 0.5V mA mA -40°C and 25°C 125°C
Notes: * Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019.
- Three-state is defined as a 500mV change from steady-state output voltage.
- The ET (enable true) notation refers to the falling edge of En. SEU immunity does not affect the read parameters.
- The EF (enable false) notation refers to the rising edge of En. SEU immunity does not affect the read parameters.
1 Read cycle time 25 ns
2 Output hold time 3 ns
3 En-controlled access time 25 ns
Figure 3. 5-Volt SRAM Loading
AC CHARACTERISTICS WRITE CYCLE ( Pre/Post-Radiation)* Notes: * Post-radiation performance guaranteed at 25 °C per MIL-STD-883 Method 1019. 1. Functional test performed with outputs disabled ( G high). 2. Three-state is defined as 500mV change from steady-state output voltage. SYMBOL PARAMETER MIN MAX UNIT tAVAV
1 Write cycle time 25 ns
tETWH Device Enable t o end of write 20 ns tAVET Address setup time for write ( En - controlled) 1 ns tAVWL Address setup time for write ( Wn - controlled) 0 ns tWLWH Write pulse width 20 ns tWHAX Address hold time for write ( Wn - controlled) 0 ns tEFAX Address hold time for Device Enable ( En - controlled) 0 ns tWLQZ
2 Wn - controlled three-state time 10 ns
2 Wn - controlled Output Enable t ime 5 ns
tETEF Device Enable p ulse width (En - controlled) 20 ns tDVWH Data setup time 15 ns tWHDX Data hold time 0 ns tWLEF Device Enable c ontrolled write pulse width 20 ns tDVEF Data setup time 15 ns tEFDX Data hold time 0 ns tAVWH Address valid to end of write 20 ns tWHWL 1 Write disable time 5 ns
Assumptions: 1. G < V IL (max). If G > V IH (min) then Q n(7:0) will be in three-state for the entire cycle. 2. G high for t AVAV cycle. Wn tAVWL Figure 5a. SRAM Write Cycle 1: Write Enable - C ontrolled Access A(18:0) Qn(7:0) En tAVAV2 Dn(7:0) APPLIED DATA tDVWH tWHDX tETWH tWLWH tWHAX tWHQX tWLQZ tAVWH tWHWL
- En = VDD - .2V, all other inputs = V DR or V SS .
- Data retention current (I DDR ) Tc = 25 oC.
- Not guaranteed or tested.
- Performed at V DD (min) and V DD (max).
- En = VSS, all other inputs = V DR or V SS .
- Not guaranteed or tested.
Figure 7. Low VDD Data Retention Waveform
Figure 8. 68-pin Ceramic FLATPACK
- Package shipped with non-conductive
strip (NCS). Leads are not trimmed.
- Total weight approx. 7.37g.
ORDERING INFORMATION
512K32 16Megabit SRAM MCM: Device Type: - =25ns access time, 5.0V operation Package Type: (S) = 68-lead dual cavity CQFP Screening: (P) = Prototype flow (W) = Extended Industrial Temperature Range Flow (-40 o C to +125 o C) Lead Finish: (C) = Gold Notes: 1. Prototype flow per UTMC Manufacturing Flows Document. Devices are tested at 25 oC. Gold lead finish only. 2. Extended Industrial Temperature Range flow per UTMC Manufacturing Flows Document. Devices are tested at -40 °C to +125 °C. Radiation neither tested nor guaranteed. Gold Lead Finish Only. UT9Q512K32 - * * * * Aeroflex UTMC Core Part Number
512K32 16Megabit SRAM MCM: SMD Notes: 1. Total dose radiation must be specified when ordering. Gold finish only. 2. Only Extended Industrial temperature -40C to +125C. No military temp. test available. Federal Stock Class Designator: No Options Total Dose (-) = none (D) = 1E4 (10krad(Si)) (P) = 3E4 (30krad(Si)) (contact factory) (L) = 5E4 (50krad(Si)) (contact factory) Drawing Number: 01511 Device Type 01 = 25 ns access time, 5.0V operation , Extended Industrial Temp (-40 oC to +125 oC) Class Designator: (T) = QML Class T (Q) = QML Class Q Case Outline: (X) = 68-lead dual cavity CQFP Lead Finish: (C) = Gold