5962-0054001QXC

TSC695F ATMEL | Alldatasheet

Document overview

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Technical content

Features

• Integer Unit Based on SPARC V7 High-performance RISC Architecture
• Optimized Integrated 32/64-bit Floating-point Unit
• On-chip Peripherals – EDAC and Parity Generator and Checker – Memory Interface Chip Select Generator Waitstate Generation Memory Protection – DMA Arbiter – Timers General Purpose Timer (GPT) Real-time Clock Timer (RTCT) Watchdog Timer (WDT) – Interrupt Controller with 5 External Inputs – General Purpose Interface (GPI) – Dual UART
• Speed Optimized Code RAM Interface 8- or 40-bit boot-PROM (Flash) Interface
• IEEE 1149.1 Test Access Port (TAP) for Debugging and Test Purposes
• Fully Static Design
• Performance: 12 MIPs/3 MFlops (Double Precision) at SYSCLK = 15 MHz
• Core Consumption: 1.0W Typ. at 20 MIPs/0.7W typ. at 10 MIPs
• Operating Range: 4.5V to 5.5V(1) -55°C to +125°C
• Total Dose Radiation Capability (Parametric and Functional): 300 KRADs (Si)
• SEU Event Rate Better than 3 E-8 Error/Component/Day (Worst Case)
• Latch-up Immunity Better than (LET) 100 MeV-cm2/mg
• Quality Grades: ESA SCC, QML Q or V
• Package: 256 MQFPF; Bare Die Note: 1. For 3.3V capability see the TSC695FL datasheet on the Atmel site.

Description

The TSC695F (ERC32 Single-Chip) is a highly integrated, high-performance 32-bit RISC embedded processor implementing the SPARC architecture V7 specification. It has been developed with the support of the ESA (European Space Agency), and offers a full development environment for embedded space applications. The processor is manufactured using the Atmel 0.5 µm radiation tolerant (≥ 300 KRADs (Si)) CMOS enhanced process (RTP). It has been specially designed for space, as it has on-chip concurrent transient and permanent error detection. The TSC695F includes an on-chip Integer Unit (IU), a Floating Point Unit (FPU), a Memory Controller and a DMA arbiter. For real-time applications, the TSC695F offers a high security watchdog, two timers, an interrupt controller, parallel and serial inter- faces. Fault tolerance is supported using parity on internal/external buses and an EDAC on the external data bus. The design is highly testable with the support of an On-Chip Debugger (OCD), and a boundary scan through JTAG interface. Rad-Hard 32-bit SPARC Embedded Processor TSC695F

4118H–AERO–06/03 Block Diagram Figure 1. TSC695F Block Diagram For pin assignment, refer to package section. Table 1. Pin Descriptions RA[31:0] I/O, 32-bit registered address bus Output buffer: 400 pF RAPAR I/O High Registered address bus parity RASI[3:0] I/O 4-bit registered address space identifier RSIZE[1:0] I/O 2-bit registered bus transaction size RASPAR I/O High Registered ASI and SIZE parity CPAR I/O High Control bus parity D[31:0] I/O 32-bit data bus CB[6:0] I/O 7-bit check-bit bus DPAR I/O High Data bus parity RLDSTO I/O High Registered atomic load-store ALE O Low Address latch enable DXFER I/O High Data transfer LOCK I/O High Bus lock RD I/O High Read access WE I/O Low Write enable WRT I/O High Advanced write MHOLD O Low Memory bus hold MHOLD+FHOLD +BHOLD+FCCV MDS O Low Memory data strobe MEXC O Low Memory exception PROM8 I Low Select 8-bit wide PROM BA[1:0] O Latched address used for 8-bit wide boot PROM ROMCS O Low PROM chip select ROMWRT I Low ROM write enable MEMCS[9:0] O Low Memory chip select Output buffer: 400 pF MEMWR O Low Memory write strobe Output buffer: 400 pF

4118H–AERO–06/03 Note: If not specified, the output buffer type is 150 pF, the input buffer type is TTL. OE O Low Memory output enable Output buffer: 400 pF BUFFEN O Low Data buffer enable DDIR O High Data buffer direction DDIR O Low Data buffer direction IOSEL[3:0] O Low I/O chip select IOWR O Low I/O and exchange memory write strobe EXMCS O Low Exchange memory chip select BUSRDY I Low Bus ready BUSERR I Low Bus error DMAREQ I Low DMA request DMAGNT O Low DMA grant DMAAS I High DMA address strobe DRDY O Low Data ready during DMA access IUERR O Low IU error CPUHALT O Low Processor (IU & FPU) halt and freeze SYSERR O Low System error SYSHALT I Low System halt SYSAV O High System availability NOPAR I Low No parity INULL O High Integer unit nullify cycle INST O High Instruction fetch Used to check the execute stage of IU instruction pipeline FLUSH O High FPU instruction flush DIA O High Delay instruction annulled RTC O High Real Time Clock Counter output RxA/RxB I Receive data UART ’A’ and ’B’ Input trigger TxA/TxB O Transmit data UART ’A’ and ’B’ GPI[7:0] I/O GPI input/output Input trigger GPIINT O High GPI interrupt EXTINT[4:0] I External interrupt Input trigger EXTINTACK O High External interrupt acknowledge IWDE I High Internal watch dog enable EWDINT I High External watch dog input interrupt Input trigger WDCLK I Watch dog clock CLK2 I Double frequency clock SYSCLK O System clock RESET O Low Output reset SYSRESET I Low System input reset Input trigger TMODE[1:0] I Factory test mode Functional mode=00 DEBUG I High Software debug mode TCK I Test (JTAG) clock TRST I Low Test (JTAG) reset pull-up ≈ 37 kΩ TMS I Test (JTAG) mode select pull-up ≈ 37 kΩ TDI I Test (JTAG) data input pull-up ≈ 37 kΩ TDO O Test (JTAG) data output VCCI/VSSI Main internal power VCCO/VSSO Output driver power Table 1. Pin Descriptions (Continued)

other system support functions are provided by the core. Figure 2. System Architecture Based on TSC695F

4118H–AERO–06/03 Product Description Integer Unit The Integer Unit (IU) is designed for highly dependable space and military applications, and includes support for error detection. The RISC architecture makes the creation of a processor that can execute instructions at a rate approaching one instruction per pro- cessor clock possible. To achieve that rate of execution, the IU employs a four-stage instruction pipeline that permits parallel execution of multiple instructions. Fetch - The processor outputs the instruction address to fetch the instruction. Decode - The instruction is placed in the instruction register and is decoded. The processor reads the operands from the register file and computes the next instruction address. Execute - The processor executes the instruction and saves the results in temporary registers. Pending traps are prioritized and internal traps are taken during this stage. Write - If no trap is taken, the processor writes the result to the destination register. All four stages operate in parallel, working on up to four different instructions at a time. A basic ‘single-cycle’ instruction enters the pipeline and completes infour cycles. By the time it reaches the write stage, three more instructions have entered and are moving through the pipeline behind it. So, after the first four cycles, a single-cycle instruction exits the pipeline and a single-cycle instruction enters the pipeline on every cycle. Of course, a ’single-cycle’ instruction actually takes four cycles to complete, but they are called single cycle because with this type of instruction the processor can com- plete one instruction per cycle after the initial four-cycle delay. Floating-point Unit The FLoating Point Unit (FPU) is designed to provide execution of single and double- precision floating-point instructions concurrently with execution of integer instructions by the IU. The FPU is compliant to the ANSI/IEEE-754 (1985) floating-point standard. The FPU is designed for highly dependable space and military applications, and includes support for concurrent error detection and testability. The FPU uses a four stage instruction pipeline consisting of fetch, decode, execute and write stages (F, D, E and W). The fetch unit captures instructions and their addresses from the data and address buses. The decode unit contains logic to decode the floating- point instruction opcodes. The execution unit handles all instruction execution. The exe- cution unit includes a floating-point queue (FP queue), which contains stored floating- point operate (FPop) instructions under execution and their addresses. The execution unit controls the load unit, the store unit, and the datapath unit. The FPU depends upon the IU to access all addresses and control signals for memory access. Floating-point loads and stores are executed in conjunction with the IU, which provides addresses and control signals while the FPU supplies or stores the data. Instruction fetch for integer and floating-point instructions is provided by the IU. The FPU provides three types of registers: f registers, FSR, and the FP queue. The FSR is a 32-bit status and control register. It keeps track of rounding modes, floating-point trap types, queue status, condition codes, and various IEEE exception information. The floating-point queue contains the floating-point instruction currently under execution, along with its corresponding address.

cal/shift, control transfer, read/write control register, floating-point, and miscellaneous. Please refer to SPARC V7 Instruction-set Manual. The execution of IFLUSH will cause an illegal instruction trap. Table 2. Memory Mapping Table 3. System Registers Address Map

Table 3. System Registers Address Map (Continued)

4118H–AERO–06/03 Extended I/O and the Extended General areas. EDAC The TSC695F includes a 32-bit EDAC (Error Detection And Correction). Seven bits (CB[6:0]) are used as check bits over the data bus. The Data Bus Parity signal (DPAR) is used to check and generate the odd parity over the 32-bit data bus. This means that altogether 40 bits are used when the EDAC is enabled. The TSC695F EDAC uses a 7-bit Hamming code which detects any double bit error on the 40-bit bus as a non-correctable error. In addition, the EDAC detects all bits stuck-at- one and stuck-at-zero failure for any nibble in the data word as a non-correctable error. Stuck-at-one and stuck-at-zero for all 32 bits of the data word is also detected as a non- correctable error. Memory and I/O Parity The TSC695F handles parity towards memory and I/O in a special way. The processor can be programmed to use no parity, only parity or parity and EDAC protection towards memory and to use parity or no towards I/O. The signal used for the parity bit is DPAR. Memory Redundancy Programming the Memory Configuration Register, the TSC695F provides chip selects for two redundant memory banks for replacement of faulty banks. Memory Access Protection Unimplemented Areas - Access to all unimplemented memory areas are handled by the TSC695F and detected as illegal. RAM Write Access Protection - The TSC695F can be programmed to detect and mask write accesses in any part of the RAM. The protection scheme is enabled only for data area, not for the instruction area. The programmable write access protection is based on two segments. Boot PROM Write Protection - The TSC695F supports a qualified PROM write for an 8-bit wide PROM and/or for a 40-bit wide PROM. DMA DMA Interface The TSC695F supports Direct Memory Access (DMA). The DMA unit requests access to the processor bus by asserting the DMA request signal (DMAREQ). When the DMA unit receives the DMAGNT signal in response, the processor bus is granted. In case the processor is in the power-down mode the processor is permanent tri-stated, and a DMAREQ will directly give a DMAGNT. The TSC695F includes a DMA session time-out function. Bus Arbiter The TSC695F always has the lowest priority on the system bus. Traps A trap is a vectored transfer of control to the supervisor through a special trap table that contains the first four instructions of each trap handler. The base address of the table is established by supervisor and the displacement, within the table, is determined by the trap type. Two categories of traps can appear.

Table 4. Synchronous Traps Special case of non-restartable, precise error.

are cleared automatically when the interrupt is acknowledged. high and to define the external interrupts to either be edge or level sensitive. Table 4. Synchronous Traps (Continued) Table 5. Interrupts or Asynchronous Traps

4118H–AERO–06/03 Timers In software debug mode the timers are controlled by a system register bit and the exter- nal pin DEBUG. General Purpose Timer The General Purpose Timer (GPT) provides, in addition to a generalized counter func- tion, a mechanism for setting the step size in which actual time counts are performed. GPT is clocked by the internal system clock. They are possible to program to be either of single-shot type or periodical type and in both cases generate an interrupt when the delay time has elapsed. The current value of the scaler and counter of the GPT can be read. Real Time Clock Timer The only functional differences between the two timers are that the Real Time Clock Timer (RTCT) has an 8-bit scaler (16-bit scaler for GPT) and that the RTCT interrupt has higher priority than the GPT interrupt. RTCT information is available on RTC output pin. Watchdog Timer Setting the external pin IWDE to VCC enables the internal watchdog timer. Otherwise the watchdog function must be externally provided. The watchdog is supplied from a separate external input (WDCLK). After reset, the timer is enabled and starts running with the maximum range. If the timer is not refreshed (reprogrammed) before the counter reaches zero value, an interrupt is sent. Simulta- neously, the timer starts counting a reset time-out period. If the timer is not acknowledged before the reset time-out period elapses, a reset is applied to TSC695F. UARTs Two full duplex asynchronous receiver transmitters (UART) are included. In software debug mode the UART’s are controlled by system register bits. The data format of the UART’s is eight bits. It is possible to choose between even or odd parity, or no parity, and between one and two stop bits. The UART’s provide double buff- ering, i.e. each UART consists of a transmitter holding register, a receiver holding register, a transmitter shift register, and a receiver shift register. Each of these registers are 8-bit wide. For each UART a RX and TX Register is provided. The UART’s generate an interrupt each time a byte has been received or a byte has been sent. There is another interrupt to indicate errors. The baud rate of both the UART’s is programmable. The clock is derived either from the system clock or can use the watchdog clock. General Purpose Interface The General Purpose Interface (GPI) is an 8-bit parallel I/O port. Each pin can be config- ured as an input or an output. A falling or rising edge detection is made on each selected GPI inputs. Every input tran- sition on GPI generates an external positive pulse on GPIINT pin of two SYSCLK width. Execution Modes Reset Mode Reset mode is entered when: The SYSRES input is asserted Software reset which is caused by the software writing to a Software Reset Register Watchdog reset which is caused by a Watchdog counter time-out Error reset which is caused by a hardware parity error

4118H–AERO–06/03 This RESET output has a minimum of 1024 SYSCLK width to allow the usage of Flash memories. The error and Reset Status Register contain the source of the last processor reset. Run Mode In this mode the IU/FPU is executing, while all peripherals are running (if software enabled). System Halt Mode System Halt mode is entered when the SYSHALT input is asserted. In this mode, the IU and FPU are frozen, while the timers (includeing the internal watchdog timer) and UART’s are stopped. Power Down Mode This mode is entered by writing to the Power-down Register. In this mode, the IU and FPU are frozen. The TSC695F leaves the power-down mode if an external interrupt is asserted. Error Halt Mode Error Halt mode is entered under the following circumstances: A internal hardware parity error. The IU enters error mode. The only way to exit Error Halt Mode is through Cold Reset by asserting SYSRESET. Error Handler The TSC695F has one error output signal (SYSERR) which indicates that an unmasked error has occurred. Any error signalled on the error inputs from the IU and the FPU is latched and reflected in the Error and Reset Status Register. By default, an error leads to a processor halt. Parity Checking The TSC695F includes: Parity checking and generation (if required) on the external data bus Parity checking on the external address bus Parity checking on ASI and SIZE Parity checking and generation on all system registers Parity generation and checking on the internal control bus to the IU All external parity checking can be disabled using the NOPAR signal. System Clock The TSC695F uses CLK2 clock input directly and creates a system clock signal by dividing CLK2 by two. It drives SYSCLK pin with a nominal 50% duty cycle for the appli- cation. It is highly recommended that only SYSCLK rising edge is used as reference as far as possible. System Availability The SYSAV bit in the Error and Reset Status Register can be used by software to indi- cate system availability. Test Mode The TSC695F includes a number of software test facilities such as EDAC test, Parity test, Interrupt test, Error test and a simple Test Access Port. These test functions are controlled using the Test Control Register.

4118H–AERO–06/03 Test and Diagnostic Hardware Functions A variety of TSC695F test and diagnostic hardware functions, including boundary scan, internal scan, clock control and On-chip Debugger, are controlled through an IEEE 1149.1 (JTAG) standard Test Access Port (TAP). Test Access Port The TAP interfaces to the JTAG bus via 5 dedicated pins on the TSC695F chip. These pins are: TCK (input): Test Clock TMS (input): Test Mode Select TDI (input): Test Data Input TDO (output): Test Data Output TRST (input): Test Reset Instruction Register Five standard instructions are supported by the TSC695F TAP. Debugging The design is highly testable with the support of an On-Chip Debugger (OCD), an inter- nal and boundary scan through JTAG interface. Binary Value Name of Instruction Data Register Scan Chain Accessed 00. 0000 EXTEST Boundary Scan Register Boundary scan chain 00. 0001 SAMPLE/PRELOAD Boundary Scan Register Boundary scan chain 00. 0011 INTEST Boundary Scan Register Boundary scan chain 11. 1111 BYPASS Bypass Register Bypass register 10. 0000 IDCODE Device ID Register ID register scan chain

4118H–AERO–06/03

Electrical Characteristics

Note: Stresses at or above those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions may affect device reliability. Table 6. DC Characteristics at VDD 5V ± 10%

4118H–AERO–06/03 Capacitance Ratings AC Characteristics Parameter Table 7. AC Characteristics (SYSCLK Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V

Table 7. AC Characteristics (SYSCLK Freq. = 25 MHz − 5V ±10%) Cload = 50 pF, Vref = 2.5V (Continued)

Figure 3. 150 pF Buffer Response (Data from simulation)

Figure 4. 400 pF Buffer Response (Data from simulation)

**Figure 5. OE*/400 pF Buffer Response (Data from simulation)**

Figure 6. RAM Fetch, RAM Load and RAM Store Sequence - n Waitstates for Read, m Waitstates for Write

Figure 7. RAM Atomic-load-store byte Sequence - 0 Waitstate

Figure 8. RAM Load-double and RAM Store-double Sequence - 0 Waitstate

Figure 9. RAM Load with Correctable Error - 0 Waitstate

Figure 10. RAM Load with Uncorrectable Error - 0 Waitstate

Figure 11. RAM Load with Unimplemented Area Access - 0 Waitstate

**Figure 12. I/O Store Sequence with BUSRDY* and n Waitstates (Timing for 0 Waitstate = Timing for 1 Waitstates)**

**Figure 13. I/O Load Sequence with BUSRDY* and n Waitstates (Timing for 0 ws = Timing for 1 ws)**

**Figure 14. EXCHANGE RAM Store with BUSDRY* and n Waitstates**

**Figure 15. EXCHANGE RAM Load with BUSDRY* and n Waitstates**

Figure 16. 8-bit BOOT PROM Fetch (or Load Word) - n Waitstates

Figure 17. 8-bit BOOT PROM 2x Store byte - n Waitstate

Figure 18. DMA RAM load with or without Correctable Error and DMA RAM Store - 0 Waitstates

Figure 19. Edge Triggered Interrupt Timing

Figure 20. Halt Timing

Figure 21. External Error with Halt Timing

Figure 22. Reset Timing

age to the surface and then transferred when there is surrounding air by convection. to case) and Rθca (case to ambient). Figure 23. Thermal Model Table 8. Thermal Characteristics

4118H–AERO–06/03 256-lead MQFP-F Package

Table 9. Pin Assignments

Table 9. Pin Assignments (Continued)

4118H–AERO–06/03

Ordering Information

Table 10. Possible Order Entries

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