4514

Mitsubishi Electric Sem...

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Rev.1.0

Manufacturer: Mitsubishi Electric Sem...

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4513 MITSUBISHI | Alldatasheet

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DESCRIPTION

The 4513/4514 Group is a 4-bit single-chip microcomputer de- signed with CMOS technology. Its CPU is that of the 4500 series using a simple, high-speed instruction set. The computer is equipped with serial I/O, four 8-bit timers (each timer has a reload register), and 10-bit A-D converter. The various microcomputers in the 4513/4514 Group include varia- tions of the built-in memory type and package as shown in the table below.

FEATURES

(at 4.0 MHz oscillation frequency, in high-speed mode, VDD = 4.0 V to 5.5 V) l Supply voltage

Middle-speed mode ROM version and One Time PROM version) ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V)
High-speed mode ROM version and One Time PROM version) ROM version and One Time PROM version) ROM version) (Operation voltage of A-D conversion: 2.7 V to 5.5 V) l Timers l Voltage drop detection circuit l Clock generating circuit (ceramic resonator) l LED drive directly enabled (port D) APPLICATION Microwave oven, rice cooker, audio, telephone, office equipment Note: shipped in blank * : Under development **: Under planning Product M34513M2-XXXSP/FP * M34513M4-XXXSP/FP * M34513E4SP/FP * (Note) M34513M6-XXXFP M34513M8-XXXFP M34513E8FP ** (Note) M34514M6-XXXFP * M34514M8-XXXFP * M34514E8FP * (Note) ROM type Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM Mask ROM Mask ROM One Time PROM Package SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A SP: 32P4B FP: 32P6B-A 32P6B-A 32P6B-A 32P6B-A 42P2R-A 42P2R-A 42P2R-A RAM size (5 4 bits) 128 words 256 words 256 words 384 words 384 words 384 words 384 words 384 words 384 words ROM (PROM) size (5 10 bits) 2048 words 4096 words 4096 words 6144 words 8192 words 8192 words 6144 words 8192 words 8192 words 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PIN CONFIGURATION (TOP VIEW) 4513 Group M34513Mx-XXXSPM34513E4SP P13 P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1- AIN1/CMP0+ AIN0/CMP0- P31/INT1 P30/INT0 VDCE VDD D 0 D 1 D 2 D 3 D 4 D 5 D 6/CNTR0 D 7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNV SS XOUT XIN VSS Outline 32P4B 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 M34513Mx-XXXFP M34513ExFP D D D RESETCNV SS X OUT X IN V SS V DD VDCE 0/INT0 Outline 32P6B-A D 3 D 4 D 5 D 6/CNTR 0 D 7/CNTR 1 P20/SCK P21/SOUT P22/SIN P02 P01 P00 AIN3/CMP1+ AIN2/CMP1- AIN1/CMP0+ AIN0/CMP0- P31/INT1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PIN CONFIGURATION (TOP VIEW) 4514 Group P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1- AIN1/CMP0+ AIN0/CMP0- P31/INT1 P30/INT0 VDCE VDD M34514Mx-XXXFP M34514E8FP Outline 42P2R-A P13 D 1 D 2 D 3 D 4 D 5 D 6/CNTR0 D 7/CNTR1 P21/SOUT P20/SCK P22/SIN CNV SS XOUT XIN VSS RESET P43/AIN7 P32 P33 P42/AIN6 P41/AIN5 P40/AIN432 D 0 P50 P51 P52 P53

4500 Series

ALU (4 bits) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) Timer 1 (8 bits) Timer 2 (8 bits) Timer 3 (8 bits) Timer 4 (8 bits) A-D converter (10 bits 5 4 ch) Port DPort P3Port P2Port P1Port P0 3 2 8

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. BLOCK DIAGRAM (4514 Group) Voltage drop detection circuit Serial I/O (8 bits 5 1) Voltage comparator (2 circuits) XIN—X OUT I/O port Internal peripheral functions Timer System clock generating circuit Watchdog timer (16 bits) Memory ROM 6144, 8192 words × 10 bits RAM 384 words × 4 bits ALU (4 bits) Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) Stack register SK (8 levels) Interrupt stack register SDP (1 level) Timer 1 (8 bits) Timer 2 (8 bits) Timer 3 (8 bits) Timer 4 (8 bits) A-D converter (10 bits 5 8 ch) Port DPort P3Port P2Port P1Port P0 Port P5 Port P4 4 4 4 4 83

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PERFORMANCE OVERVIEW Function 123 128 0.75 µs (at 4.0 MHz oscillation frequency, in high-speed mode) 2048 words 5 10 bits 4096 words 5 10 bits 6144 words 5 10 bits 8192 words 5 10 bits 6144 words 5 10 bits 8192 words 5 10 bits 128 words 5 4 bits 256 words 5 4 bits 384 words 5 4 bits 384 words 5 4 bits 384 words 5 4 bits 384 words 5 4 bits Eight independent I/O ports; ports D6 and D7 are also used as CNTR0 and CNTR1, respectively. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 4-bit I/O port; each pin is equipped with a pull-up function and a key-on wakeup function. Both functions can be switched by software. 3-bit input port; ports P20, P21 and P22 are also used as SCK , SOUT and SIN, respectively. 4-bit I/O port (2-bit I/O port for the 4513 Group); ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. 4-bit I/O port; The 4513 Group does not have this port. 4-bit I/O port with a direction register; The 4513 Group does not have this port. 1-bit I/O; CNTR0 pin is also used as port D 1-bit I/O; CNTR1 pin is also used as port D7. 1-bit input; INT0 pin is also used as port P30 and equipped with a key-on wakeup function. 1-bit input; INT1 pin is also used as port P31 and equipped with a key-on wakeup function. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 8-bit programmable timer with a reload register. 8-bit programmable timer with a reload register is also used as an event counter. 10-bit wide, This is equipped with an 8-bit comparator function. 2 circuits (CMP0, CMP1) 8-bit 5 1 8 (two for external, four for timer, one for A-D, and one for serial I/O) 1 level 8 levels CMOS silicon gate 32-pin plastic molded SDIP (32P4B)/LQFP(32P6B-A) 42-pin plastic molded SSOP (42P2R-A) –20 °C to 85 °C 2.0 V to 5.5 V for Mask ROM version, 2.5 V to 5.5 V for One Time PROM version (Refer to the electrical characteristics because the supply voltage depends on the oscillation frequency.) 1.8 mA (at V DD = 5.0 V, 4.0 MHz oscillation frequency, in middle- speed mode, output transis- tors in the cut-off state) 3.0 mA (at VDD = 5.0 V, 4.0 MHz oscillation frequency, in high-speed mode, output transistors in the cut-off state) 0.1 µA (at room temperature, VDD = 5 V, output transistors in the cut-off state) Parameter Number of basic instructions Minimum instruction execution time Memory sizes Input/Output ports Timers A-D converter Voltage comparator Serial I/O Interrupt Subroutine nesting Device structure Package Operating temperature range Supply voltage Power dissipation (typical value) ROM RAM D 0–D 7 P00–P0 3 P10–P1 3 P20–P2 2 P30–P3 3 P40–P4 3 P50–P5 3 CNTR0 CNTR1 INT0 INT1 Timer 1 Timer 2 Timer 3 Timer 4 Sources Nesting

4513 Group

4514 Group

I/O (Input is examined by skip decision) I/O I/O Input I/O I/O I/O I/O I/O Input Input

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PIN DESCRIPTION Name Power supply Ground Voltage drop detec- tion circuit enable CNV SS Reset input System clock input System clock output I/O port D (Input is examined by skip decision.) I/O port P0 I/O port P1 Input port P2 I/O port P3 I/O port P4 I/O port P5 Analog input Timer input/output Timer input/output Interrupt input Serial data input Serial data output Serial I/O clock input/output Voltage comparator input Voltage comparator input Pin V DD VSS VDCE CNV SS RESET X IN XOUT D 0–D 7 P00–P0 3 P10–P1 3 P20–P2 2 P30–P3 3 P40–P4 3 P50–P5 3 AIN0–AIN7 CNTR0 CNTR1 INT0, INT1 S IN SOUT SCK CMP0- CMP0+ CMP1- CMP1+ Input/Output Input I/O Input Output I/O I/O I/O Input I/O I/O I/O Input I/O I/O Input Input Output I/O Input Input Function Connected to a plus power supply. Connected to a 0 V power supply. VDCE pin is used to control the operation/stop of the voltage drop detection circuit. When “H” level is input to this pin, the circuit is operating. When “L” level is inpu to this pin, the circuit is stopped. Connect CNV SS to VSS and apply “L” (0V) to CNVSS certainly. An N-channel open-drain I/O pin for a system reset. When the watchdog timer causes the system to be reset or system reset is performed by the voltage drop de- tection circuit, the RESET pin outputs “L” level. I/O pins of the system clock generating circuit. X IN and XOUT can be connected to ceramic resonator. A feedback resistor is built-in between them. Each pin of port D has an independent 1-bit wide I/O function. Each pin has an out- put latch. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports D 6 and D7 are also used as CNTR0 and CNTR1, respectively. Each of ports P0 and P1 serves as a 4-bit I/O port, and it can be used as inputs when the output latch is set to “1.” The output structure is N-channel open-drain. Every pin of the ports has a key-on wakeup function and a pull-up function. Both functions can be switched by software. 3-bit input port. Ports P2 0, P21 and P22 are also used as SCK , SOUT and SIN, re- spectively. 4-bit I/O port (2-bit I/O port for the 4513 Group). For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports P30 and P31 are also used as INT0 and INT1, respectively. The 4513 Group does not have ports P32, P33. 4-bit I/O port. For input use, set the latch of the specified bit to “1.” The output structure is N-channel open-drain. Ports P40–P4 3 are also used as analog input pins AIN4–AIN7, respectively. The 4513 Group does not have port P4. 4-bit I/O port. Each pin has a direction register and an independent 1-bit wide I/O function. For input use, set the direction register to “0.” For output use, set the di- rection regiser to “1.” The output structure is CMOS. The 4513 Group does not have port P5. Analog input pins for A-D converter. A IN0–AIN3 are also used as comparator input pins and AIN4–AIN7 are also used as port P4. The 4513 Group does not have AIN4–AIN7. CNTR0 pin has the function to input the clock for the timer 2 event counter, and to output the timer 1 underflow signal divided by 2. CNTR0 pin is also used as port D CNTR1 pin has the function to input the clock for the timer 4 event counter, and to output the timer 3 underflow signal divided by 2. CNTR1 pin is also used as port D INT0, INT1 pins accept external interrupts. They also accept the input signal to re- turn the system from the RAM back-up state. INT0, INT1 pins are also used as ports P3 0 and P31, respectively. SIN pin is used to input serial data signals by software. SIN pin is also used as port P22. SOUT pin is used to output serial data signals by software. SOUT pin is also used as port P21. SCK pin is used to input and output synchronous clock signals for serial data trans- fer by software. S CK pin is also used as port P20. CMP0-, CMP0+ pins are used as the voltage comparator input pin when the volt- age comparator function is selected by software. CMP0-, CMP0+ pins are also used as A IN0 and AIN1. CMP1-, CMP1+ pins are used as the voltage comparator input pin when the volt- age comparator function is selected by software. CMP1-, CMP1+ pins are also used as A IN2 and AIN3.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Notes 1: Pins except above have just single function. 2: The input of D6, D7, P20–P2 2, CMP0-, CMP0+, CMP1-, CMP1+ and the input/output of P30, P31, P40–P4 3 can be used even when CNTR0, CNTR1, SCK , SOUT , SIN, INT0, INT1, and AIN0–A IN7 are selected. 3: The 4513 Group does not have P40/AIN4–P4 3/AIN7. Notes 1: After system is released from reset, port P5 is in a input mode (di- rection register FR0 = 00002) 2: When the P00–P0 3 and P10–P1 3 are connected to VSS , turn off their pull-up transistors (register PU0i=“0”) and also invalidate the key-on wakeup functions (register K0i=“0”) by software. When these pins are connected to V SS while the key-on wakeup func- tions are left valid, the system fails to return from RAM back-up state. When these pins are open, turn on their pull-up transistors (register PU0i=“1”) by software, or set the output latch to “0.” Be sure to select the key-on wakeup functions and the pull-up functions with every two pins. If only one of the two pins for the key-on wakeup function is used, turn on their pull-up transistors by software and also disconnect the other pin. (i = 0, 1, 2, or 3.) (Note when the output latch is set to “0” and pins are open) l After system is released from reset, port is in a high-impedance state un- til it is set the output latch to “0” by software. Accordingly, the voltage level of pins is undefined and the excess of the supply current may occur while the port is in a high-impedance state. l To set the output latch periodically by software is recommended because value of output latch may change by noise or a program run away (caused by noise). (Note when connecting to V SS and VDD ) l Connect the unused pins to VSS and VDD using the thickest wire at the shortest distance against noise. Pin D 6 D 7 P20 P21 P22 P30 P31 Multifunction CNTR0 CNTR1 S CK SOUT SIN INT0 INT1 MULTIFUNCTION Multifunction CMP0- CMP0+ CMP1- CMP1+ A IN4 AIN5 AIN6 AIN7 Pin AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 CONNECTIONS OF UNUSED PINS Connection Open (when using an external clock). Connect to VSS . Connect to VSS , or set the output latch to “0” and open. Connect to VSS . Connect to VSS , or set the output latch to “0” and open. Connect to VSS , or set the output latch to “0” and open. When the input mode is selected by soft- ware, pull-up to VDD through a resistor or pull-down to VDD . When selecting the output mode, open. Connect to VSS . Open or connect to VSS (Note 2) Open or connect to VSS (Note 2) Pin XOUT VDCE D 0–D 5 D 6/CNTR0 D 7/CNTR1 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4–P4 3/AIN7 P50–P5 3 (Note 1) AIN0/CMP0- AIN1/CMP0+ AIN2/CMP1- AIN3/CMP1+ P00–P0 3 P10–P1 3 Pin CNTR0 CNTR1 S CK SOUT SIN INT0 INT1 Multifunction D D 7 P20 P21 P22 P30 P31 Multifunction AIN0 AIN1 AIN2 AIN3 P40 P41 P42 P43 Pin CMP0- CMP0+ CMP1- CMP1+ A IN4 AIN5 AIN6 AIN7

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Notes 1: The 4513 Group does not have P32 and P33. 2: The 4513 Group does not have these ports. DEFINITION OF CLOCK AND CYCLE l System clock The system clock is the basic clock for controlling this product. The system clock is selected by the bit 3 of the clock control reg- ister MR. PORT FUNCTION Port Port D Port P0 Port P1 Port P2 Port P3 (Note 1) Port P4 (Note 2) Port P5 (Note 2) I/O unit Control instructions SD, RD SZD CLD OP0A IAP0 OP1A IAP1 IAP2 OP3A IAP3 OP4A IAP4 OP5A IAP5 Control registers PU0, K0 PU0, K0 I1, I2 FR0 Output structure N-channel open-drain N-channel open-drain N-channel open-drain N-channel open-drain N-channel open-drain CMOS Input Output I/O (8) I/O (4) I/O (4) Input (3) I/O (4) I/O (4) I/O (4) Remark Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in programmable pull-up functions Key-on wakeup functions (programmable) Built-in key-on wakeup function (P3 0/INT0, P31/INT1) Pin D 0–D 5 D 6/CNTR0 D 7/CNTR1 P00–P0 3 P10–P1 3 P20/SCK P21/SOUT P22/SIN P30/INT0 P31/INT1 P32, P33 P40/AIN4 –P43/AIN7 P50–P5 3 Register MR MR 3 System clock f(XIN) f(XIN)/2 Note: f(XIN)/2 is selected after system is released from reset. l Instruction clock The instruction clock is a signal derived by dividing the system clock by 3. The one instruction clock cycle generates the one machine cycle. l Machine cycle The machine cycle is the standard cycle required to execute the instruction. Table Selection of system clock

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PORT BLOCK DIAGRAMS D T QAi P00,P01 K00 PU0 0 D T QAi P02,P03 K01 PU0 1 D T QAi P10,P11 K02 PU0 2 D T QAi P12,P13 K03 PU0 3 Key-on wakeup input Pull-up transistor OP0A instruction IAP0 instruction Key-on wakeup input Pull-up transistor OP0A instruction IAP0 instruction Key-on wakeup input Pull-up transistor OP1A instruction IAP1 instruction Key-on wakeup input Pull-up transistor Register A OP1A instruction IAP1 instruction This symbol represents a parasitic diode on the port. i represents 0, 1, 2, or 3. Register A Register A Register A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PORT BLOCK DIAGRAMS (continued) Synchronous clock input for serial transfer Register A IAP2 instruction P20/SCK J10 Synchronous clock output for serial transfer P30/INT0,P31/INT1 D T Q External interrupt circuit Register A Ai IAP3 instruction OP3A instruction J11 P21/SOUT Register A IAP2 instruction Serial data output J11 P22/SINRegister A IAP2 instruction Serial data input P32,P33 D T Q Register A Ai IAP3 instruction OP3A instruction Key-on wakeup input This symbol represents a parasitic diode on the port.

Applied potential to ports P20—P2 2 must be VDD .
i represents 0, 1, 2, or 3.
The 4513 Group does not have ports P3 2, P33.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PORT BLOCK DIAGRAMS (continued) AIN0/CMP0- Q3 0 AIN1/CMP0+ Q3 2 AIN2/CMP1- Q3 1 AIN3/CMP1+ Q3 3 OP4A instruction IAP4 instruction P40/AIN4–P43/AIN7 DQ T Register A Ai Decoder Analog input Decoder Analog input Analog input Analog input Analog input This symbol represents a parasitic diode on the port.

i represents 0, 1, 2, or 3.
The 4513 Group does not have port P4. Decoder Decoder Decoder CMP0 CMP1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PORT BLOCK DIAGRAMS (continued) P50–P53D T Q OP5A instruction Ai Register A IAP5 instruction D 0–D 5 SD instruction S R Q Decoder Skip decision (SZD instruction) Register Y RD instruction D 6/CNTR0S R Q Skip decision(SZD instruction) SD instruction DecoderRegister Y RD instruction 0 W6 0 Timer 1 underflow signal output Clock input for timer 2 event count D 7/CNTR1S R Q 0 W6 2 Direction register FR0i Skip decision(SZD instruction) SD instruction DecoderRegister Y RD instruction Timer 3 underflow signal output Clock input for timer 4 event count This symbol represents a parasitic diode on the port.

Applied potential to ports D0–D 7 must be 12 V.
i represents 0, 1, 2, or 3.
The 4513 Group does not have port P5.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. External interrupt circuit structure I22 EXF1 I21 SNZI1 P31/INT1 I12 Wakeup Skip EXF0 I11 SNZI0 P30/INT0 Rising Falling One-sided edge detection circuit Both edges detection circuit External 0 interrupt External 1 interrupt Wakeup Skip Rising Falling One-sided edge detection circuit Both edges detection circuit

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. FUNCTION BLOCK OPERATIONS CPU (1) Arithmetic logic unit (ALU) The arithmetic logic unit ALU performs 4-bit arithmetic such as 4- bit data addition, comparison, AND operation, OR operation, and bit manipulation. (2) Register A and carry flag Register A is a 4-bit register used for arithmetic, transfer, ex- change, and I/O operation. Carry flag CY is a 1-bit flag that is set to “1” when there is a carry with the AMC instruction (Figure 1). It is unchanged with both A n instruction and AM instruction. The value of A 0 is stored in carry flag CY with the RAR instruction (Fig- ure 2). Carry flag CY can be set to “1” with the SC instruction and cleared to “0” with the RC instruction. (3) Registers B and E Register B is a 4-bit register used for temporary storage of 4-bit data, and for 8-bit data transfer together with register A. Register E is an 8-bit register. It can be used for 8-bit data transfer with register B used as the high-order 4 bits and register A as the low-order 4 bits (Figure 3). (4) Register D Register D is a 3-bit register. It is used to store a 7-bit ROM address together with register A and is used as a pointer within the specified page when the TABP p, BLA p, or BMLA p instruction is executed (Figure 4). Fig. 1 AMC instruction execution example Fig. 2 RAR instruction execution example Fig. 3 Registers A, B and register E Fig. 4 TABP p instruction execution example (CY) (M(DP)) (A) Addition ALU <Carry> <Result> CY A 3 A2 A1 A0 A0 CY A 3 A2 A1 <Rotation> RAR instruction <Set> SC instruction <Clear> RC instruction A3 A 2 A1 A0B3 B2 B1 B0 E 7 E6 E5 E4 E3 E2 E 1 E0 A3 A2 A1 A0B3 B2 B1 B0 TAB instruction TEAB instruction TABE instruction TBA instruction Register B Register A Register B Register A Register E Specifying address TABP p instruction p6 p5 p4 p3 p2 p1 p0 PC H DR 2 DR 1DR 0 A3 A2 A1 A0 PC L Immediate field value p The contents of register D ROM 840 Middle-order 4 bits Low-order 4bits Register A (4) Register B (4) The contents of register A

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (5) Stack registers (SKS) and stack pointer (SP) Stack registers (SKs) are used to temporarily store the contents of program counter (PC) just before branching until returning to the original routine when;

branching to an interrupt service routine (referred to as an inter- rupt service routine),
performing a subroutine call, or
executing the table reference instruction (TABP p). Stack registers (SKs) are eight identical registers, so that subrou- tines can be nested up to 8 levels. However, one of stack registers is used respectively when using an interrupt service routine and when executing a table reference instruction. Accordingly, be care- ful not to over the stack when performing these operations together. The contents of registers SKs are destroyed when 8 lev- els are exceeded. The register SK nesting level is pointed automatically by 3-bit stack pointer (SP). The contents of the stack pointer (SP) can be transferred to register A with the TASP instruction. Figure 5 shows the stack registers (SKs) structure. Figure 6 shows the example of operation at subroutine call. (6) Interrupt stack register (SDP) Interrupt stack register (SDP) is a 1-stage register. When an inter- rupt occurs, this register (SDP) is used to temporarily store the contents of data pointer, carry flag, skip flag, register A, and regis- ter B just before an interrupt until returning to the original routine. Unlike the stack registers (SKs), this register (SDP) is not used when executing the subroutine call instruction and the table refer- ence instruction. (7) Skip flag Skip flag controls skip decision for the conditional skip instructions and continuous described skip instructions. When an interrupt oc- curs, the contents of skip flag is stored automatically in the interrupt stack register (SDP) and the skip condition is retained. Fig. 5 Stack registers (SKs) structure Fig. 6 Example of operation at subroutine call Returning to the BM instruction execution address with the RT instruction, and the B M instruction becomes the NOP instruction. (SP) ← 0 (SK0) ← 000116 (PC) ← SUB1 Main program

000216 NOP

000016 NOP

000116 BM SUB1

SUB1 : NOP RT (PC) ← (SK0) (SP) ← 7 Note : SK 0 SK 1 SK 2 SK 3 SK 4 SK 5 SK 6 SK 7 (SP) = 0 (SP) = 1 (SP) = 2 (SP) = 3 (SP) = 4 (SP) = 5 (SP) = 6 (SP) = 7 Program counter (PC) Executing RT instruction Executing BM instruction Stack pointer (SP) points “7” at reset or returning from RAM back-up mode. It points “0” by executing the first BM instruction, and the contents of program counter is stored in SK When the BM instruction is executed after eight stack registers are used ((SP) = 7), (SP) = 0 and the contents of SK 0 is destroyed.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (8) Program counter (PC) Program counter (PC) is used to specify a ROM address (page and address). It determines a sequence in which instructions stored in ROM are read. It is a binary counter that increments the number of instruction bytes each time an instruction is executed. However, the value changes to a specified address when branch instructions, subroutine call instructions, return instructions, or the table refer- ence instruction (TABP p) is executed. Program counter consists of PC H (most significant bit to bit 7) which specifies to a ROM page and PCL (bits 6 to 0) which speci- fies an address within a page. After it reaches the last address (address 127) of a page, it specifies address 0 of the next page (Figure 7). Make sure that the PC H does not specify after the last page of the built-in ROM. (9) Data pointer (DP) Data pointer (DP) is used to specify a RAM address and consists of registers Z, X, and Y . Register Z specifies a RAM file group, reg- ister X specifies a file, and register Y specifies a RAM digit (Figure 8). Register Y is also used to specify the port D bit position. When using port D, set the port D bit position to register Y certainly and execute the SD, RD, or SZD instruction (Figure 9). Fig. 7 Program counter (PC) structure Fig. 8 Data pointer (DP) structure Fig. 9 SD instruction execution example Z1 Z0 X3 X2 X1 X0 Y3 Y2 Y1 Y0 Data pointer (DP) Register Z (2) Register X (4) Register Y (4)Specifying RAM digit Specifying RAM file Specifying RAM file group 01 01 1 D 7 Set Specifying bit position Port D output latchRegister Y (4) D 5D 6 D 4 D 0 p5 p4 p3 p2 p1 p0 a6 a5 a4 a3 a2 a1 a0 Program counter PC H Specifying page PC L Specifying address

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. PROGRAM MEMORY (ROM) The program memory is a mask ROM. 1 word of ROM is composed of 10 bits. ROM is separated every 128 words by the unit of page (addresses 0 to 127). Table 1 shows the ROM size and pages. Fig- ure 10 shows the ROM map of M34514M8/E8. Table 1 ROM size and pages Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 ROM size (5 10 bits) 2048 words 4096 words 6144 words 8192 words 6144 words 8192 words Pages 16 (0 to 15) 32 (0 to 31) 48 (0 to 47) 64 (0 to 63) 48 (0 to 47) 64 (0 to 63) A part of page 1 (addresses 008016 to 00FF16) is reserved for in- terrupt addresses (Figure 11). When an interrupt occurs, the address (interrupt address) corresponding to each interrupt is set in the program counter, and the instruction at the interrupt address is executed. When using an interrupt service routine, write the in- struction generating the branch to that routine at an interrupt address. Page 2 (addresses 010016 to 017F16) is the special page for sub- routine calls. Subroutines written in this page can be called from any page with the 1-word instruction (BM). Subroutines extending from page 2 to another page can also be called with the BM in- struction when it starts on page 2. ROM pattern (bits 7 to 0) of all addresses can be used as data ar- eas with the TABP p instruction. Fig. 10 ROM map of M34514M8/E8 Fig. 11 Page 1 (addresses 008016 to 00FF16) structure 90 8765 4321 External 0 interrupt address External 1 interrupt address 008016 008216 Timer 1 interrupt address008416 Timer 2 interrupt address008616 Timer 3 interrupt address008816 008A16 00FF16 Timer 4 interrupt address A-D interrupt address Serial I/O interrupt address 008C 16 008E16 0876 54321 000016 008016 017F16 Subroutine special page 007F16 00FF16 010016 1FFF 16 018016 Page 1 Page 2 Page 0 Page 3 Page 310FFF 16 Interrupt address page Page 63

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. DATA MEMORY (RAM) 1 word of RAM is composed of 4 bits, but 1-bit manipulation (with the SB j, RB j, and SZB j instructions) is enabled for the entire memory area. A RAM address is specified by a data pointer. The data pointer consists of registers Z, X, and Y. Set a value to the data pointer certainly when executing an instruction to access RAM. Table 2 shows the RAM size. Figure 12 shows the RAM map. Fig. 12 RAM map Table 2 RAM size Product M34513M2 M34513M4/E4 M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 RAM size 128 words 5 4 bits (512 bits) 256 words 5 4 bits (1024 bits) 384 words 5 4 bits (1536 bits) 384 words 5 4 bits (1536 bits) 384 words 5 4 bits (1536 bits) 384 words 5 4 bits (1536 bits) M34513M6 M34513M8/E8 M34514M6 M34514M8/E8 M34513M4/E4 M34513M2 Z=0, X=0 to 15 Z=0, X=0 to 7 Z=0, X=0 to 15 Z=1, X=0 to 7 Register Y Register Z Register X 01 7 RAM 384 words 5 4 bits (1536 bits) 23 6 015 384 words 256 words 128 words 45 17 23 645

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. INTERRUPT FUNCTION The interrupt type is a vectored interrupt branching to an individual address (interrupt address) according to each interrupt source. An interrupt occurs when the following 3 conditions are satisfied.

An interrupt activated condition is satisfied (request flag = “1”)
Interrupt enable bit is enabled (“1”)
Interrupt enable flag is enabled (INTE = “1”) Table 3 shows interrupt sources. (Refer to each interrupt request flag for details of activated conditions.) (1) Interrupt enable flag (INTE) The interrupt enable flag (INTE) controls whether the every inter- rupt enable/disable. Interrupts are enabled when INTE flag is set to “1” with the EI instruction and disabled when INTE flag is cleared to “0” with the DI instruction. When any interrupt occurs, the INTE flag is automatically cleared to “0,” so that other interrupts are disabled until the EI instruction is executed. (2) Interrupt enable bit Use an interrupt enable bit of interrupt control registers V1 and V2 to select the corresponding interrupt or skip instruction. Table 4 shows the interrupt request flag, interrupt enable bit and skip instruction. Table 5 shows the interrupt enable bit function. (3) Interrupt request flag When the activated condition for each interrupt is satisfied, the cor- responding interrupt request flag is set to “1.” Each interrupt request flag is cleared to “0” when either;
an interrupt occurs, or
the next instruction is skipped with a skip instruction. Each interrupt request flag is set when the activated condition is satisfied even if the interrupt is disabled by the INTE flag or its in- terrupt enable bit. Once set, the interrupt request flag retains set until a clear condition is satisfied. Accordingly, an interrupt occurs when the interrupt disable state is released while the interrupt request flag is set. If more than one interrupt request flag is set when the interrupt dis- able state is released, the interrupt priority level is as follows shown in Table 3. Table 3 Interrupt sources Activated condition Level change of INT0 pin Level change of INT1 pin Timer 1 underflow Timer 2 underflow Timer 3 underflow Timer 4 underflow Completion of A-D conversion Completion of serial I/O transfer Priority level Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A-D interrupt Serial I/O interrupt Request flag EXF0 EXF1 T1F T2F T3F T4F ADF SIOF Interrupt name External 0 interrupt External 1 interrupt Timer 1 interrupt Timer 2 interrupt Timer 3 interrupt Timer 4 interrupt A-D interrupt Serial I/O interrupt Table 5 Interrupt enable bit function Occurrence of interrupt Enabled Disabled Skip instruction Invalid Valid Interrupt enable bit Interrupt address Address 0 in page 1 Address 2 in page 1 Address 4 in page 1 Address 6 in page 1 Address 8 in page 1 Address A in page 1 Address C in page 1 Address E in page 1 Table 4 Interrupt request flag, interrupt enable bit and skip in- struction Skip instruction SNZ0 SNZ1 SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI Enable bit V10 V11 V12 V13 V20 V21 V22 V23

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (4) Internal state during an interrupt The internal state of the microcomputer during an interrupt is as fol- lows (Figure 14).

Program counter (PC) An interrupt address is set in program counter. The address to be executed when returning to the main routine is automatically stored in the stack register (SK).
Interrupt enable flag (INTE) INTE flag is cleared to “0” so that interrupts are disabled.
Interrupt request flag Only the request flag for the current interrupt source is cleared to “0.”
Data pointer, carry flag, skip flag, registers A and B The contents of these registers and flags are stored automatically in the interrupt stack register (SDP). (5) Interrupt processing When an interrupt occurs, a program at an interrupt address is ex- ecuted after branching a data store sequence to stack register. Write the branch instruction to an interrupt service routine at an in- terrupt address. Use the RTI instruction to return from an interrupt service routine. Interrupt enabled by executing the EI instruction is performed after executing 1 instruction (just after the next instruction is executed). Accordingly, when the EI instruction is executed just before the RTI instruction, interrupts are enabled after returning the main routine. (Refer to Figure 13) Fig. 13 Program example of interrupt processing
Program counter (PC)
Stack register (SK)
Interrupt enable flag (INTE)
Interrupt request flag (only the flag for the current interrupt
Data pointer, carry flag, registers A and B, skip flag The address of main routine to be executed when returning Fig. 15 Interrupt system diagram Fig. 14 Internal state when interrupt occurs EI RTI Interrupt service routine Interrupt occurs Interrupt is enabled Main rouine : Interrupt enabled state : Interrupt disabled state T1F V1 2 EXF1 V1 1 EXF0 V10 Address 2 in page 1 Address 4 in page 1 Address 0 in page 1 T4F V2 1 T3F V2 0 T2F V1 3 Address 8 in page 1 Address A in page 1 Address 6 in page 1 SIOF V2 3 ADF V2 2 Completion of serial I/O transfer Timer 1 underflow Timer 4 underflow Timer 3 underflow Timer 2 underflow Completion of A-D conversion Address E in page 1 Address C in page 1 Request flag (state retained) Enable bit Enable flag INTE Activated condition INT0 pin (L→ H or H→ L input) INT1 pin (L→ H or H→ L input)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (6) Interrupt control registers

Interrupt control register V1 Interrupt enable bits of external 0, external 1, timer 1 and timer 2 are assigned to register V1. Set the contents of this register through register A with the TV1A instruction. The TAV1 instruction can be used to transfer the contents of register V1 to register A.
Interrupt control register V2 Interrupt enable bits of timer 3, timer 4, A-D and serial I/O are as- signed to register V2. Set the contents of this register through register A with the TV2A instruction. The TAV2 instruction can be used to transfer the contents of register V2 to register A. Table 6 Interrupt control registers V12 V11 V10 V23 V22 V21 V20 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Note: “R” represents read enabled, and “W” represents write enabled. Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) R/Wat RAM back-up : 0000 2at reset : 00002 R/Wat RAM back-up : 00002at reset : 00002 Interrupt control register V2 R/Wat RAM back-up : 00002at reset : 00002

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (7) Interrupt sequence Interrupts only occur when the respective INTE flag, interrupt en- able bits (V10–V1 3 and V20–V2 3), and interrupt request flag are “1.” The interrupt actually occurs 2 to 3 machine cycles after the cycle in which all three conditions are satisfied. The interrupt oc- curs after 3 machine cycles only when the three interrupt condi- tions are satisfied on execution of other than one-cycle instructions (Refer to Figure 16). Fig. 16 Interrupt sequence T1 T2 T3 T1 T2 T3 T1 T2 T3 System clock T1 T2 T3 EXF0, EXF1 T1F, T2F, T3F, T4F, ADF,SIOF INT0, INT1 T1 T2 T3 2 to 3 machine cycles (Notes 2, 3) The program starts from the interrupt address. Flag cleared Interrupt enabled state When an interrupt request flag is set after its interrupt is enabled (Note 1) 1 machine cycle EI instruction execution cycleInterrupt enable flag (INTE) Retaining level of system clock for 4 periods or more is necessary. Interrupt disabled state External interrupt Timer 1, Timer 2, Timer 3, Timer 4, A-D, and Serial I/O interrupts Interrupt activated condition is satisfied. 2: The address is stacked to the last cycle. 3: This interval of cycles depends on the executed instruction at the time when each interrupt activated condition is satisfied. Notes 1: The 4513/4514 Group operates in the middle-speed mode after system is released from reset. f (XIN) (middle-speed mode) f (XIN) (high-speed mode)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Table 7 External interrupt activated conditions Name External 0 interrupt External 1 interrupt Input pin P30/INT0 P31/INT1 Activated condition When the next waveform is input to P30/INT0 pin

Both rising and falling waveforms When the next waveform is input to P3 1/INT1 pin
Both rising and falling waveforms Valid waveform selection bit I11 I12 I21 I22 Fig. 17 External interrupt circuit structure EXTERNAL INTERRUPTS The 4513/4514 Group has two external interrupts (external 0 and external 1). An external interrupt request occurs when a valid waveform is input to an interrupt input pin (edge detection). The external interrupts can be controlled with the interrupt control registers I1 and I2. I22 EXF1 I21 SNZI1 P31/INT1 I12 Wakeup Skip EXF0 I11 SNZI0 P30/INT0 Rising Falling One-sided edge detection circuit Both edges detection circuit External 0 interrupt External 1 interrupt Wakeup Skip Rising Falling One-sided edge detection circuit Both edges detection circuit

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (1) External 0 interrupt request flag (EXF0) External 0 interrupt request flag (EXF0) is set to “1” when a valid waveform is input to P30/INT0 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF0 flag can be examined with the skip instruction (SNZ0). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF0 flag is cleared to “0” when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. The P3 0/INT0 pin need not be selected the external interrupt input INT0 function or the normal I/O port P30 function. However, the EXF0 flag is set to “1” when a valid waveform is input even if it is used as an I/O port P3

External 0 interrupt activated condition External 0 interrupt activated condition is satisfied when a valid waveform is input to P30/INT0 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 0 interrupt is as follows. À Select the valid waveform with the bits 1 and 2 of register I1. \` Clear the EXF0 flag to “0” with the SNZ0 instruction. ´ Set the NOP instruction for the case when a skip is performed with the SNZ0 instruction. ˆ Set both the external 0 interrupt enable bit (V1 0) and the INTE flag to “1.” The external 0 interrupt is now enabled. Now when a valid wave- form is input to the P30/INT0 pin, the EXF0 flag is set to “1” and the external 0 interrupt occurs. (2) External 1 interrupt request flag (EXF1) External 1 interrupt request flag (EXF1) is set to “1” when a valid waveform is input to P3 1/INT1 pin. The valid waveforms causing the interrupt must be retained at their level for 4 clock cycles or more of the system clock (Refer to Figure 16). The state of EXF1 flag can be examined with the skip instruction (SNZ1). Use the interrupt control register V1 to select the interrupt or the skip instruction. The EXF1 flag is cleared to “0” when an in- terrupt occurs or when the next instruction is skipped with the skip instruction. The P3 1/INT1 pin need not be selected the external interrupt input INT1 function or the normal I/O port P31 function. However, the EXF1 flag is set to “1” when a valid waveform is input even if it is used as an I/O port P3
External 1 interrupt activated condition External 1 interrupt activated condition is satisfied when a valid waveform is input to P31/INT1 pin. The valid waveform can be selected from rising waveform, falling waveform or both rising and falling waveforms. An example of how to use the external 1 interrupt is as follows. À Select the valid waveform with the bits 1 and 2 of register I2. \` Clear the EXF1 flag to “0” with the SNZ1 instruction. ´ Set the NOP instruction for the case when a skip is performed with the SNZ1 instruction. ˆ Set both the external 1 interrupt enable bit (V1 1) and the INTE flag to “1.” The external 1 interrupt is now enabled. Now when a valid wave- form is input to the P31/INT1 pin, the EXF1 flag is set to “1” and the external 1 interrupt occurs.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (3) External interrupt control registers

Interrupt control register I1 Register I1 controls the valid waveform for the external 0 inter- rupt. Set the contents of this register through register A with the TI1A instruction. The TAI1 instruction can be used to transfer the contents of register I1 to register A.
Interrupt control register I2 Register I2 controls the valid waveform for the external 1 inter- rupt. Set the contents of this register through register A with the TI2A instruction. The TAI2 instruction can be used to transfer the contents of register I2 to register A. Table 8 External interrupt control registers I12 I11 I10 I23 I22 I21 I20 Not used Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Not used Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. Interrupt control register I1 R/Wat RAM back-up : state retainedat reset : 00002 This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Interrupt control register I2 R/Wat RAM back-up : state retainedat reset : 0000

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. TIMERS The 4513/4514 Group has the programmable timers.

Programmable timer The programmable timer has a reload register and enables the frequency dividing ratio to be set. It is decremented from a setting value n. When it underflows (count to n + 1), a timer interrupt re- quest flag is set to “1,” new data is loaded from the reload register, and count continues (auto-reload function).
Fixed dividing frequency timer The fixed dividing frequency timer has the fixed frequency divid- ing ratio (n). An interrupt request flag is set to “1” after every n count of a count pulse. Fig. 18 Auto-reload function FF16 n 0016 n : Counter initial value Count starts Reload Reload 1st underflow 2nd underflow n+1 count n+1 count Time An interrupt occurs or a skip instruction is executed. Timer interrupt request flag The contents of counter “1” “0”

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Count source

Instruction clock
Prescaler output (ORCLK)
Timer 1 underflow
Prescaler output (ORCLK)
CNTR0 input
16-bit counter underflow
Timer 2 underflow
Prescaler output (ORCLK)
Timer 3 underflow
Prescaler output (ORCLK)
CNTR1 input
Instruction clock Structure Frequency divider 8-bit programmable binary down counter (link to EXF0) 8-bit programmable binary down counter 8-bit programmable binary down counter (link to EXF1) 8-bit programmable binary down counter 16-bit fixed dividing frequency Circuit Prescaler Timer 1 Timer 2 Timer 3 Timer 4 16-bit timer Use of output signal
Timer 1, 2, 3 and 4 count sources
Timer 2 count source
CNTR0 output
Timer 1 interrupt
Timer 3 count source
Timer 2 interrupt
CNTR0 output
Timer 4 count source
Timer 3 interrupt
CNTR1 output
Timer 4 interrupt
CNTR1 output
Watchdog timer (The 15th bit is counted twice)
Timer 2 count source (16-bit counter underflow) Frequency dividing ratio 4, 16 1 to 256 1 to 256 1 to 256 1 to 256 65536 Control register The 4513/4514 Group timer consists of the following circuits.
Prescaler : frequency divider
Timer 1 : 8-bit programmable timer
Timer 2 : 8-bit programmable timer
Timer 3 : 8-bit programmable timer
Timer 4 : 8-bit programmable timer (Timers 1 to 4 have the interrupt function, respectively)
16-bit timer Prescaler and timers 1 to 4 can be controlled with the timer control registers W1 to W6. The 16-bit timer is a free counter which is not controlled with the control register. Each function is described below. Table 9 Function related timers

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 19 Timers structure D 6/CNTR0 D 6 output T4F Timer 4 interrupt T3F Timer 3 interrupt W6 0 W3 1,W30 W3 3(Note) W4 3(Note) Not available

11 Not available

W4 1,W40 Not available ORCLK T1F (T2AB) T2F (TAB2) W2 3(Note) W2 1,W20 QR SWRST instruction WDF1 WDF2WEF 1/16 1 W1 2 W1 3 MR 3 0XIN D 7/CNTR1 D 7 output0 W6 2 Q R S W1 0 (Note)W1 1 (TR1AB)T1AB T1AB (TAB1) (T4AB) (TAB4) (TR3AB)T3AB T3AB (TAB3) W3 2 Q R S I20 I10 W6 1 Timer 2 underflow signal W6 3 Timer 4 underflow signal1/2 Division circuit (divided by 2) Internal clock generation circuit (divided by 3) Instruction clock Prescaler Timer 1 (8) Timer 1 interrupt Reload register R1 (8) Register BRegister A Timer 1 underflow signal Timer 2 (8) Reload register R2 (8) Register BRegister A Timer 2 underflow signal Timer 3 (8) Reload register R3 (8) Register BRegister A Timer 3 underflow signal Timer 4 (8) Reload register R4 (8) Register BRegister A Instruction clock 16-bit timer (WDT) System reset Reset signal Timer 2 interrupt Data is set automatically from each reload register when timer 1, 2, 3, or 4 underflows (auto- reload function) Note: Count source is stopped by clearing to “0.” P30/INT0 I12 P31/INT1 I22

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Table 10 Timer control registers Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 1 underflow signal Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal Timer 2 control bit Not used Timer 2 count source selection bits W1 3 W1 2 W1 1 W1 0 W2 3 W2 2 W2 1 W2 0 W3 3 W3 2 W3 1 W3 0 W4 3 W4 2 W4 1 W4 0 W6 3 W6 2 W6 1 W6 0 Timer control register W1 R/Wat RAM back-up : 00002at reset : 00002 R/Wat RAM back-up : 00002at reset : 00002 Timer control register W2 R/Wat RAM back-up : state retainedat reset : 00002 W3 1 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Count source Timer 2 underflow signal Prescaler output Not available Not available Timer 3 control bit Timer 3 count start synchronous circuit control bit Timer 3 count source selection bits Timer control register W3 R/Wat RAM back-up : state retainedat reset : 00002 W4 1 Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available Timer 4 control bit Not used Timer 4 count source selection bits Timer control register W4 R/Wat RAM back-up : state retainedat reset : 00002 Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D 7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D 6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input) CNTR1 output control bit D 7/CNTR1 function selection bit CNTR0 output control bit D 6/CNTR0 output control bit Timer control register W6 R/Wat RAM back-up : state retainedat reset : 00002 Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (1) Timer control registers

Timer control register W1 Register W1 controls the count operation of timer 1, the selection of count start synchronous circuit, and the frequency dividing ra- tio and count operation of prescaler. Set the contents of this register through register A with the TW1A instruction. The TAW1 instruction can be used to transfer the contents of register W1 to register A.
Timer control register W2 Register W2 controls the count operation and count source of timer 2. Set the contents of this register through register A with the TW2A instruction. The TAW2 instruction can be used to trans- fer the contents of register W2 to register A.
Timer control register W3 Register W3 controls the count operation and count source of timer 3 and the selection of count start synchronous circuit. Set the contents of this register through register A with the TW3A in- struction. The TAW3 instruction can be used to transfer the contents of register W3 to register A.
Timer control register W4 Register W4 controls the count operation and count source of timer 4. Set the contents of this register through register A with the TW4A instruction. The TAW4 instruction can be used to trans- fer the contents of register W4 to register A.
Timer control register W6 Register W6 controls the D 6/CNTR0 pin and D7/CNTR1 func- tions, the selection and operation of the CNTR0 and CNTR1 output. Set the contents of this register through register A with the TW6A instruction. The TAW6 instruction can be used to trans- fer the contents of register W6 to register A. (2) Precautions Note the following for the use of timers.
Prescaler Stop the prescaler operation to change its frequency dividing ra- tio.
Count source Stop timer 1, 2, 3, or 4 counting to change its count source.
Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data.
Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. (3) Prescaler Prescaler is a frequency divider. Its frequency dividing ratio can be selected. The count source of prescaler is the instruction clock. Use the bit 2 of register W1 to select the prescaler dividing ratio and the bit 3 to start and stop its operation. Prescaler is initialized, and the output signal (ORCLK) stops when the bit 3 of register W1 is cleared to “0.” (4) Timer 1 (interrupt function) Timer 1 is an 8-bit binary down counter with the timer 1 reload reg- ister (R1). Data can be set simultaneously in timer 1 and the reload register (R1) with the T1AB instruction. Data can be written to re- load register (R1) with the TR1AB instruction. When writing data to reload register R1 with the TR1AB instruction, the downcount after the underflow is started from the setting value of reload register R1. Timer 1 starts counting after the following process; À set data in timer 1, and \ set the bit 1 of register W1 to “1.” However, P3 0/INT0 pin input can be used as the start trigger for timer 1 count operation by setting the bit 0 of register W1 to “1.” Once count is started, when timer 1 underflows (the next count pulse is input after the contents of timer 1 becomes “0”), the timer 1 interrupt request flag (T1F) is set to “1,” new data is loaded from reload register R1, and count continues (auto-reload function). When a value set in reload register R1 is n, timer 1 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 1 with the TAB1 instruction. When reading the data, stop the counter and then execute the TAB1 in- struction. Timer 1 underflow signal divided by 2 can be output from D 6/CNTR0 pin. (5) Timer 2 (interrupt function) Timer 2 is an 8-bit binary down counter with the timer 2 reload reg- ister (R2). Data can be set simultaneously in timer 2 and the reload register (R2) with the T2AB instruction. Timer 2 starts counting after the following process; À set data in timer 2, \ select the count source with the bits 0 and 1 of register W2, and ´ set the bit 3 of register W2 to “1.” Once count is started, when timer 2 underflows (the next count pulse is input after the contents of timer 2 becomes “0”), the timer 2 interrupt request flag (T2F) is set to “1,” new data is loaded from reload register R2, and count continues (auto-reload function). When a value set in reload register R2 is n, timer 2 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 2 with the TAB2 instruction. When reading the data, stop the counter and then execute the TAB2 in- struction. The output from D 6/CNTR0 pin by timer 2 underflow signal divided by 2 can be controlled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (6) Timer 3 (interrupt function) Timer 3 is an 8-bit binary down counter with the timer 3 reload reg- ister (R3). Data can be set simultaneously in timer 3 and the reload register (R3) with the T3AB instruction. Data can be written to re- load register (R3) with the TR3AB instruction. When writing data to reload register R3 with the TR3AB instruction, the downcount after the underflow is started from the setting value of reload register R3. Timer 3 starts counting after the following process; À set data in timer 3, \ select the count source with the bits 0 and 1 of register W3, and ´ set the bit 3 of register W3 to “1.” However, P3 1/INT1 pin input can be used as the start trigger for timer 3 count operation by setting the bit 2 of register W3 to “1.” Once count is started, when timer 3 underflows (the next count pulse is input after the contents of timer 3 becomes “0”), the timer 3 interrupt request flag (T3F) is set to “1,” new data is loaded from reload register R3, and count continues (auto-reload function). When a value set in reload register R3 is n, timer 3 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 3 with the TAB3 instruction. When reading the data, stop the counter and then execute the TAB3 in- struction. Timer 3 underflow signal divided by 2 can be output from D 7/CNTR1 pin. (7) Timer 4 (interrupt function) Timer 4 is an 8-bit binary down counter with the timer 4 reload reg- ister (R4). Data can be set simultaneously in timer 4 and the reload register (R4) with the T4AB instruction. Timer 4 starts counting after the following process; À set data in timer 4, \ select the count source with the bits 0 and 1 of register W4, and ´ set the bit 3 of register W4 to “1.” Once count is started, when timer 4 underflows (the next count pulse is input after the contents of timer 4 becomes “0”), the timer 4 interrupt request flag (T4F) is set to “1,” new data is loaded from reload register R4, and count continues (auto-reload function). When a value set in reload register R4 is n, timer 4 divides the count source signal by n + 1 (n = 0 to 255). Data can be read from timer 4 with the TAB4 instruction. When reading the data, stop the counter and then execute the TAB4 in- struction. The output from D 7/CNTR1 pin by timer 4 underflow signal divided by 2 can be controlled. (8) Timer I/O pin (D6/CNTR0, D7/CNTR1) D 6/CNTR0 pin has functions to input the timer 2 count source, and to output the timer 1 and timer 2 underflow signals divided by 2. D 7/CNTR1 pin has functions to input the timer 4 count source, and to output the timer 3 and timer 4 underflow signals divided by 2. The selection of D6/CNTR0 pin function can be controlled with the bit 0 of register W6. The selection of D7/CNTR1 pin function can be controlled with the bit 2 of register W6. The following signals can be selected for the CNTR0 output signal with the bit 1 of register W6.

timer 1 underflow signal divided by 2
the signal of AND operation between timer 1 underflow signal di- vided by 2 and timer 2 underflow signal divide by 2 The following signals can be selected for the CNTR1 output signal with the bit 3 of register W6.
timer 3 underflow signal divided by 2
the signal of AND operation between timer 3 underflow signal di- vided by 2 and timer 4 underflow signal divide by 2 Timer 2 counts the rising waveform of CNTR0 input when the CNTR0 input is selected as the count source. Timer 4 counts the rising waveform of CNTR1 input when the CNTR1 input is selected as the count source. (9) Timer interrupt request flags (T1F, T2F, T3F, and T4F) Each timer interrupt request flag is set to “1” when each timer underflows. The state of these flags can be examined with the skip instructions (SNZT1, SNZT2, SNZT3, and SNZT4). Use the interrupt control registers V1, V2 to select an interrupt or a skip instruction. An interrupt request flag is cleared to “0” when an interrupt occurs or when the next instruction is skipped with a skip instruction. (10) Count start synchronization circuit (timer 1, timer 3) Each timer 1 and timer 3 has the count start synchronization circuit which synchronize P30/INT0 pin and P31/INT1 pin, respectively, and can start the timer count operation. Timer 1 count start synchronization circuit function is selected by setting the bit 0 of register W1 to “1.” The control by P3 0/INT0 pin input can be performed by setting the bit 0 of register I1 to “1.” P3 0/INT0 pin input level can be selected by the bit 2 of register I1 as follows;
I1 2 = “0”: The count start synchronizes the “L” level of P30/INT0 pin
I12 = “1”: The count start synchronizes the “H” level of P30/INT0 pin Timer 3 count start synchronization circuit function is selected by setting the bit 2 of register W3 to “1.” The control by P3 1/INT1 pin input can be performed by setting the bit 0 of register I2 to “1.” P3 1/INT1 pin input level can be selected by the bit 2 of register I2 as follows;
I2 2 = “0”: The count start synchronizes the “L” level of P31/INT1 pin
I22 = “1”: The count start synchronizes the “H” level of P31/INT1 pin When timer 1 and timer 3 count start synchronization circuits are used, the count start synchronization circuits are set, the count source is input to each timer by inputting valid levels to P30/INT0 pin and P31/INT1 pin. Once set, the count start synchronization cir- cuit is cleared by clearing the bit I10 or I20 to “0” or reset.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. WATCHDOG TIMER Watchdog timer provides a method to reset the system when a pro- gram runs wild. Watchdog timer consists of a 16-bit timer (WDT), watchdog timer enable flag (WEF), and watchdog timer flags (WDF1, WDF2). The timer WDT downcounts the instruction clocks as the count source. The underflow signal is generated when the count value reaches “0000 16.” This underflow signal can be used as the timer 2 count source. When the WRST instruction is executed after system is released from reset, the WEF flag is set to “1”. At this time, the watchdog timer starts operating. When the count value of timer WDT reaches “BFFF 16” or “3FFF16,” the WDF1 flag is set to “1.” If the WRST instruction is never ex- ecuted while timer WDT counts 32767, WDF2 flag is set to “1,” and the RESET pin outputs “L” level to reset the microcomputer. Ex- ecute the WRST instruction at each period of 32766 machine cycle or less by software when using watchdog timer to keep the micro- computer operating normally. To prevent the WDT stopping in the event of misoperation, WEF flag is designed not to initialize once the WRST instruction has been executed. Note also that, if the WRST instruction is never ex- ecuted, the watchdog timer does not start. Fig. 20 Watchdog timer function The contents of WEF, WDF1 and WDF2 flags and timer WDT are initialized at the RAM back-up mode. If WDF2 flag is set to “1” at the same time that the microcomputer enters the RAM back-up state, system reset may be performed. When using the watchdog timer and the RAM back-up mode, ini- tialize the WDF1 flag with the WRST instruction just before the microcomputer enters the RAM back-up state (refer to Figure 21) Fig. 21 Program example to enter the RAM back-up mode when using the watchdog timer WRST ; WDF1 flag reset POF EPOF ; POF instruction enabled (RAM back-up state) Oscillation stop FFFF 16 0000 16 3FFF 16 BFFF 16 The value of timer (WDT) WDF1 flag WDF2 flag WRST instruction executed RESET pin output System reset WRST instruction executed WEF flag

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. SERIAL I/O The 4513/4514 Group has a built-in clock synchronous serial I/O which can serially transmit or receive 8-bit data. Serial I/O consists of;

serial I/O register SI
serial I/O mode register J1
serial I/O transmission/reception completion flag (SIOF)
serial I/O counter Registers A and B are used to perform data transfer with internal CPU, and the serial I/O pins are used for external data transfer. The pin functions of the serial I/O pins can be set with the register J1. Table 11 Serial I/O pins Pin P20/SCK P21/SOUT P22/SIN Pin function when selecting serial I/O Clock I/O (SCK ) Serial data output (SOUT ) Serial data input (SIN) Note: Input ports P20–P2 2 can be used regardless of register J1. Fig. 22 Serial I/O structure Table 12 Serial I/O mode register J13 J12 J11 J10 Serial I/O mode register J1 This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P2 0, P21, P22 selected Serial I/O ports SCK , SOUT , SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8) Not used Serial I/O internal clock dividing ratio selection bit Serial I/O port selection bit Serial I/O synchronous clock selection bit at reset : 00002 at RAM back-up : state retained Note: “R” represents read enabled, and “W” represents write enabled. R/W J12 SIOF J12 J11 J10 J11 J10 MSB P21/SOUT P22/SIN P20/SCK TSIAB TABSI SOUT SIN SCK J13 MR 3 0XIN Division circuit (divided by 2) Internal clock generation circuit (divided by 3) Instruction clock Serial I/O mode register J1 Serial I/O interruptSerial I/O counter (3) Synchronous circuit Register B (4) Register A (4) Serial I/O register SI (8)LSB Note: The output structure of S CK and SOUT pins is N-channel open-drain.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 23 Serial I/O register state when transferring (1) Serial I/O register SI Serial I/O register SI is the 8-bit data transfer serial/parallel conver- sion register. Data can be set to register SI through registers A and B with the TSIAB instruction. The contents of register A is transmit- ted to the low-order 4 bits of register SI, and the contents of register B is transmitted to the high-order 4 bits of register SI. During transmission, each bit data is transmitted LSB first from the lowermost bit (bit 0) of register SI, and during reception, each bit data is received LSB first to register SI starting from the topmost bit (bit 7). When register SI is used as a work register without using serial I/O, pull up the S CK pin or set the pin function to an input port P20. (2) Serial I/O transmission/reception completion flag (SIOF) Serial I/O transmission/reception completion flag (SIOF) is set to “1” when serial data transmission or reception completes. The state of SIOF flag can be examined with the skip instruction (SNZSI). Use the interrupt control register V2 to select the inter- rupt or the skip instruction. The SIOF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. When transmitting (D7–D 0 : transfer data) When receiving D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 SIN pin SOUT pin SOUT pin SIN pin Serial I/O register (SI)Serial I/O register (SI) D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 D 1 D 0 Transfer data to be set Transfer started Transfer completed D 7 D 6 D 5 D 4 D 3 D 2∗∗ D 7 D 6 D 5 D 4 D 3 D 2 D 1∗ D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 (3) Serial I/O start instruction (SST) When the SST instruction is executed, the SIOF flag is cleared to “0” and then serial I/O transmission/reception is started. (4) Serial I/O mode register J1 Register J1 controls the synchronous clock, P20/SCK , P21/SOUT and P22/SIN pin function. Set the contents of this register through register A with the TJ1A instruction. The TAJ1 instruction can be used to transfer the contents of register J1 to register A.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (5) How to use serial I/O Figure 24 shows the serial I/O connection example. Serial I/O inter- rupt is not used in this example. In the actual wiring, pull up the wiring between each pin with a resistor. Figure 25 shows the data transfer timing and Table 13 shows the data transfer sequence. Fig. 24 Serial I/O connection example SOUT SRDY signal SCK SIN D 5 SCK SOUT SIN D 5 Master (clock control) Serial I/O interrupt enable bit (SNZSI instruction is valid) Interrupt control register V2 Serial I/O mode register J1 Serial I/O port SCK,SOUT, SIN Instruction clock divided by 8 or 4 selected as a transfer clock Internal clock selected as a synchronous clock Slave (external clock) (Bit 3) (Bit 0) 155 01 This bit is not valid when J10=“0” 5 : Set an arbitrary value. (Bit 3) (Bit 0) (Bit 3) (Bit 0) (Bit 3) (Bit 0) 0 555 Serial I/O interrupt enable bit (SNZSI instruction is valid) Interrupt control register V2 Serial I/O port SCK,SOUT, SIN External clock selected as a synchronous clock Serial I/O mode register J1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 25 Timing of serial I/O data transfer SIN SOUT SCK SOUT SIN S0S7’S 1 S2 S3 S4 S5 S6 S7 S0S7’ S1 S3 S4 S5 S6 S7 M 0M 7’ M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 0M 7’M 1 M 2 M 3 M 4 M 5 M 6 M 7 M 0–M 7 : the contents of master serial I/O S0–S7 : the contents of slave serial I/O register Rising of SCK : serial input Falling of SCK : serial output Master Slave SST instruction SST instruction SRDY signal

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Table 13 Processing sequence of data transfer from master to slave 1-byte data is serially transferred on this process. Subsequently, data can be transferred continuously by repeating the process from *. When an external clock is selected as a synchronous clock, the clock is not controlled internally. Control the clock externally be- cause serial transfer is performed as long as clock is externally input. (Unlike an internal clock, an external clock is not stopped when serial transfer is completed.) However, the SIOF flag is set to “1” when the clock is counted 8 times after executing the SST in- struction. Be sure to set the initial level of the external clock to “H.” Master (transmission) [Initial setting]

Setting the serial I/O mode register J1 and inter- rupt control register V2 shown in Figure 24. TJ1A and TV2A instructions
Setting the port received the reception enable signal (S RDY ) to the input mode. (Port D5 is used in this example) SD instruction * [Transmission enable state]
Storing transmission data to serial I/O register SI. TSIAB instruction [Transmission]
Check port D 5 is “L” level. SZD instruction
Serial transfer starts. SST instruction
Check transmission completes. SNZSI instruction
Wait (timing when continuously transferring) Slave (reception) [Initial setting]
Setting serial I/O mode register J1, and interrupt control register V2 shown in Figure 24. TJ1A and TV2A instructions
Setting the port received the reception enable signal (S RDY ) and outputting “H” level (reception impossible). (Port D5 is used in this example) SD instruction *[Reception enable state]
The SIOF flag is cleared to “0.” SST instruction
“L” level (reception possible) is output from port D5. RD instruction [Reception]
Check reception completes. SNZSI instruction
“H” level is output from port D5. SD instruction [Data processing]

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. A-D CONVERTER The 4513/4514 Group has a built-in A-D conversion circuit that performs conversion by 10-bit successive comparison method. Table 14 shows the characteristics of this A-D converter. This A- D converter can also be used as an 8-bit comparator to compare analog voltages input from the analog input pin with preset val- ues. Table 14 A-D converter characteristics Characteristics Successive comparison method 10 bits Linearity error: ±2LSB Non-linearity error: ±0.9LSB 46.5 µs (High-speed mode at 4.0 MHz oscillation frequency) 4 for 4513 Group 8 for 4514 Group Parameter Conversion format Resolution Absolute accuracy Conversion speed Analog input pin Fig. 26 A-D conversion circuit structure Register A (4) VSS VDD IAP4 (P40— P43) TABAD Q2 3 Register B (4) Q1 1 Q1 0Q1 2 TADABQ2 2 Q2 1 Q2 0 8 8 01 1 Q2 3 Q2 3 DAC operation signal Q2 3 TALAQ2 3 Q1 3 TAQ1 TQ1A TAQ2 TQ2A ADF (1)AIN0/CMP0- AIN1/CMP0+ AIN2/CMP1- AIN3/CMP1+ P40/AIN8 P41/AIN9 P42/AIN10 P43/AIN11 Comparator 8-channel multi-plexed analog switch Instruction clock A-D control circuit Successive comparison register (AD) (10) A-D interrupt DA converter (Note 1) Comparator register (8) (Note 2) Notes 1: This switch is turned ON only when A-D converter is operating and generates the comparison voltage. 2: Writing/reading data to the comparator register is possible only in the comparator mode (Q23=1). The value of the comparator register is retained even when the mode is switched to the A-D conversion mode (Q2 3=0) because it is separated from the successive comparison register (AD). Also, the resolution in the comparator mode is 8 bits because the comparator register consists of 8 bits. 3: The 4513 Group does not have ports P40/AIN4–P43/AIN7 and the IAP4 and OP4A instructions. (Note 3) OP4A (P40— P43)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Q1 3 Q1 2 Q1 1 Q1 0 A-D control register Q1 Not used Analog input pin selection bits (Note 2) at reset : 00002 at RAM back-up : state retained Q12 This bit has no function, but read/write is enabled. Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) at reset : 00002 Q2 3 Q2 2 Q2 1 Q2 0 A-D control register Q2 A-D conversion mode Comparator mode P43, P42 (read/write enabled for the 4513 Group) AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 (read/write enabled for the 4513 Group) AIN5/P41 (read/write enabled for the 4513 Group) P40 (read/write enabled for the 4513 Group) AIN4/P40 (read/write enabled for the 4513 Group) A-D operation mode selection bit P4 3/AIN7 and P42/AIN6 pin function selec- tion bit (Not used for the 4513 Group) P41/AIN5 pin function selection bit (Not used for the 4513 Group) P40/AIN4 pin function selection bit (Not used for the 4513 Group) at RAM back-up : state retained Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Select AIN4–A IN7 with register Q1 after setting register Q2. Q10 (1) Operating at A-D conversion mode The A-D conversion mode is set by setting the bit 3 of register Q2 to “0.” (2) Successive comparison register AD Register AD stores the A-D conversion result of an analog input in 10-bit digital data format. The contents of the high-order 8 bits of this register can be stored in register B and register A with the TABAD instruction. The contents of the low-order 2 bits of this reg- ister can be stored into the high-order 2 bits of register A with the TALA instruction. However, do not execute this instruction during A- D conversion. When the contents of register AD is n, the logic value of the com- parison voltage V ref generated from the built-in DA converter can be obtained with the reference voltage VDD by the following for- mula: Logic value of comparison voltage Vref Vref = 5 n n: The value of register AD (n = 0 to 1023) V DD 1024 (4) A-D conversion start instruction (ADST) A-D conversion starts when the ADST instruction is executed. The conversion result is automatically stored in the register AD. (5) A-D control register Q1 Register Q1 is used to select one of analog input pins. The 4513 Group does not have A IN4–A IN7. Accordingly, do not select these pins with register Q1. (6) A-D control register Q2 Register Q2 is used to select the pin function of P40/AIN4, P41/ AIN5, P42/AIN6, and P43/AIN7. The A-D conversion mode is se- lected when the bit 3 of register Q2 is “0,” and the comparator mode is selected when the bit 3 of register Q2 is “1.” After set this register, select the analog input with register Q1. Even when register Q2 is used to set the pins for analog input, 0/AIN4–P4 3/AIN7 continue to function as P40–P4 3 I/O. Accord- ingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, for the port input, the port input function of the pin functions as analog input is undefined. R/W R/W Table 15 A-D control registers (3) A-D conversion completion flag (ADF) A-D conversion completion flag (ADF) is set to “1” when A-D con- version completes. The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the interrupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Table 16 Change of successive comparison register AD during A-D conversion Comparison voltage (Vref) valueChange of successive comparison register ADAt starting conversion (7) Operation description A-D conversion is started with the A-D conversion start instruction (ADST). The internal operation during A-D conversion is as follows: À When A-D conversion starts, the register AD is cleared to “00016.” \` Next, the topmost bit of the register AD is set to “1,” and the comparison voltage Vref is compared with the analog input volt- age VIN. ´ When the comparison result is Vref < VIN, the topmost bit of the register AD remains set to “1.” When the comparison result is Vref > VIN, it is cleared to “0.” The 4513/4514 Group repeats this operation to the lowermost bit of the register AD to convert an analog value to a digital value. A-D conversion stops after 62 machine cycles (46.5 µs when f(XIN) =

4.0 MHz in high-speed mode) from the start, and the conversion re-

sult is stored in the register AD. An A-D interrupt activated condition is satisfied and the ADF flag is set to “1” as soon as A-D conversion completes (Figure 27). \\ 1: 1st comparison result \\ 3: 3rd comparison result \\ 9: 9th comparison result \\ 2: 2nd comparison result \\ 8: 8th comparison result \\ A: Ath comparison result 1st comparison 2nd comparison 3rd comparison After 10th comparison completes \\ 1 \\ 1 \\ 1 ----- ----- ----- ----- \\ 2 \\ 2 \\ 3 \\ 8 \\ 9 \\ A A-D conversion result V DD VDD VDD VDD VDD VDD VDD VDD 1024 ○○○ ○

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 28 Setting registers 0 55 1 (Bit 3) (Bit 0) A-D control register Q2 A IN4 function selected A-D conversion mode A-D control register Q1 A IN4 pin selected 5 100 (Bit 3) (Bit 0) 5 : Set an arbitrary value (8) A-D conversion timing chart Figure 27 shows the A-D conversion timing chart. Fig. 27 A-D conversion timing chart (9) How to use A-D conversion How to use A-D conversion is explained using as example in which the analog input from P40/AIN4 pin is A-D converted, and the high- order 4 bits of the converted data are stored in address M(Z, X, Y) = (0, 0, 0), the middle-order 4 bits in address M(Z, X, Y) = (0, 0, 1), and the low-order 2 bits in address M(Z, X, Y) = (0, 0, 2) of RAM. The A-D interrupt is not used in this example. À After selecting the A IN4 pin function with the bit 0 of the register Q2, select AIN4 pin and A-D conversion mode with the register Q1 (refer to Figure 28). \` Execute the ADST instruction and start A-D conversion. ´ Examine the state of ADF flag with the SNZAD instruction to de- termine the end of A-D conversion. ˆ Transfer the low-order 2 bits of converted data to the high-order 2 bits of register A (TALA instruction). ˜ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 2). ¯ Transfer the high-order 8 bits of converted data to registers A and B (TABAD instruction). ˘ Transfer the contents of register A to M (Z, X, Y) = (0, 0, 1). ˙ Transfer the contents of register B to register A, and then, store into M(Z, X, Y) = (0, 0, 0). ADST instruction A-D conversion completion flag (ADF) 62 machine cycles DAC operation signal

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (10) Operation at comparator mode The A-D converter is set to comparator mode by setting bit 3 of the register Q2 to “1.” Below, the operation at comparator mode is described. (11) Comparator register In comparator mode, the built-in DA comparator is connected to the comparator register as a register for setting comparison voltages. The contents of register B is stored in the high-order 4 bits of the comparator register and the contents of register A is stored in the low-order 4 bits of the comparator register with the TADAB instruc- tion. When changing from A-D conversion mode to comparator mode, the result of A-D conversion (register AD) is undefined. However, because the comparator register is separated from regis- ter AD, the value is retained even when changing from comparator mode to A-D conversion mode. Note that the comparator register can be written and read at only comparator mode. If the value in the comparator register is n, the logic value of com- parison voltage V ref generated by the built-in DA converter can be determined from the following formula: (12) Comparison result store flag (ADF) In comparator mode, the ADF flag, which shows completion of A-D conversion, stores the results of comparing the analog input volt- age with the comparison voltage. When the analog input voltage is lower than the comparison voltage, the ADF flag is set to “1.” The state of ADF flag can be examined with the skip instruction (SNZAD). Use the interrupt control register V2 to select the inter- rupt or the skip instruction. The ADF flag is cleared to “0” when the interrupt occurs or when the next instruction is skipped with the skip instruction. (13) Comparator operation start instruction (ADST instruction) In comparator mode, executing ADST starts the comparator oper- ating. The comparator stops 8 machine cycles after it has started (6 µs at f(XIN) = 4.0 MHz in high-speed mode). When the analog input volt- age is lower than the comparison voltage, the ADF flag is set to “1.” (14) Notes for the use of A-D conversion 1 Note the following when using the analog input pins also for I/O port P4 functions:

Even when P40/AIN4–P4 3/AIN7 are set to pins for analog input, they continue to function as P40–P4 3 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function of the pin func- tions as an analog input is undefined.
TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, si- multaneously, the low-order 2 bits of register A is “0.” Logic value of comparison voltage Vref Vref = 5 n n: The value of register AD (n = 0 to 255) Fig. 29 Comparator operation timing chart VDD 256 ADST instruction Comparison result store flag(ADF) 8 machine cycles DAC operation signal Comparator operation completed. (The value of ADF is determined)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (15) Notes for the use of A-D conversion 2 Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with bit 3 of register Q2 while A-D converter is operating. When the operating mode of A-D converter is changed from the comparator mode to A-D conversion mode with the bit 3 of register Q2, note the following;

Clear bit 2 of register V2 to “0” to change the operating mode of the A-D converter from the comparator mode to A-D conversion mode with the bit 3 of register Q2.
The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the com- parator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. (16) Definition of A-D converter accuracy The A-D conversion accuracy is defined below (refer to Figure 30).
Relative accuracy À Zero transition voltage (V0T) This means an analog input voltage when the actual A-D con- version output data changes from “0” to “1.” \` Full-scale transition voltage (V FST ) This means an analog input voltage when the actual A-D con- version output data changes from “1023” to ”1022.” ´ Linearity error This means a deviation from the line between V 0T and VFST of a converted value between V0T and VFST . ˆ Differential non-linearity error This means a deviation from the input potential difference re- quired to change a converter value between V 0T and VFST by 1 LSB at the relative accuracy.
Absolute accuracy This means a deviation from the ideal characteristics between 0 to V DD of actual A-D conversion characteristics. Fig. 30 Definition of A-D conversion accuracy Vn: Analog input voltage when the output data changes from “n” to “n+1” (n = 0 to 1022)
1LSB at relative accuracy → (V)
1LSB at absolute accuracy → (V) VFST –V0T 1022 VDD 1024 VDDV1022VnV1V0 Vn+1 n+1 n 1022 1023 b a c Output data Differential non-linearity error = Linearity error = [LSB] c a b–a a [LSB] Actual A-D conversion characteristics a: 1LSB by relative accuracy b: Vn+1–Vn c: Difference between ideal Vn and actual Vn Zero transition voltage (V0T) Analog voltage Full-scale transition voltage (VFST ) Ideal line of A-D conversion between V0–V1022

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. VOLTAGE COMPARATOR The 4513/4514 Group has 2 voltage comparator circuits that perform comparison of voltage between 2 pins. Table 17 shows the characteristics of this voltage comparison. Table 17 Voltage comparator characteristics Characteristics 2 circuits (CMP0, CMP1) CMP0-, CMP0+ (also used as A IN0, AIN1) CMP1-, CMP1+ (also used as A IN2, AIN3) 3.0 V to 5.5 V 0.3 VDD to 0.7 VDD Typ. 20 mV, Max.100 mV Max. 20 µs Parameter Voltage comparator function Input pin Supply voltage Input voltage Comparison check error Response time Fig. 31 Voltage comparator structure CMP0–/A IN0 CMP0+/A IN1 CMP0 CMP1–/A IN2 CMP1+/A IN3 CMP1 Q3 3 Q3 2 Q3 1 Q3 0 Register A (4) TQ3A TAQ3 Voltage comparator control register Q3 (4) Note: Bits 0 and 1 of register Q3 can be only read.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Voltage comparator control register Q3 (Note 2) at reset : 00002 at RAM back-up : state retained Q3 3 Q3 2 Q3 1 Q3 0 Voltage comparator (CMP1) invalid Voltage comparator (CMP1) valid Voltage comparator (CMP0) invalid Voltage comparator (CMP0) valid CMP1- > CMP1+ CMP1- < CMP1+ CMP0- > CMP0+ CMP0- < CMP0+ Voltage comparator (CMP1) control bit Voltage comparator (CMP0) control bit CMP1 comparison result store bit CMP0 comparison result store bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: Bits 0 and 1 of register Q3 can be only read. (1) Voltage comparator control register Q3 Register Q3 controls the function of the voltage comparator. The function of the voltage comparator CMP0 becomes valid by setting bit 2 of register Q3 to “1,” and becomes invalid by setting bit 2 of register Q3 to ”0.” The comparison result of the voltage com- parator CMP0 is stored into bit 0 of register Q3. The function of the voltage comparator CMP1 becomes valid by setting bit 3 of register Q3 to “1,” and becomes invalid by setting bit 3 of register Q3 to ”0.” The comparison result of the voltage com- parator CMP1 is stored into bit 1 of register Q3. (2) Operation description of voltage comparator The voltage comparator function becomes valid by setting each control bit of register Q3 to “1” and compares the voltage of the in- put pin. The comparison result is stored into each comparison result store bit of register Q3. The comparison result is as follows;

When CMP0- > CMP0+, Q3 0 = “0” When CMP0- < CMP0+, Q3 0 = “1”
When CMP1- > CMP1+, Q3 1 = “0” When CMP1- < CMP1+, Q3 1 = “1” (3) Precautions When the voltage comparator is used, note the following;
Voltage comparator function When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM back- up mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage comparator function by software before the POF instruction is executed. Also, while the voltage comparator function is valid, current is al- ways consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator by software when it is unused.
Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they can- not be written.
Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 µs) is passed from the voltage comparator function becomes valid. R/W Table 18 Voltage comparator control register Q3

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. RESET FUNCTION System reset is performed by applying “L” level to RESET pin for 1 machine cycle or more when the following condition is satisfied; the value of supply voltage is the minimum value or more of the recommended operating conditions. Then when “H” level is applied to RESET pin, software starts from address 0 in page 0. Fig. 32 Reset release timing Fig. 33 RESET pin input waveform and reset operation RESET 0.3VDD 0.85VDD Software starts (address 0 in page 0) f(XIN) is counted 16892 to 16895 times. (Note) Note: Keep the value of supply voltage to the minimum value or more of the recommended operating conditions. Reset input 1 machine cycle or more f(XIN) RESET Software starts (address 0 in page 0) f(XIN) is counted 16892 to 16895 times. (Note) Note: It depends on the internal state of the microcomputer when reset is performed.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (1) Power-on reset Reset can be performed automatically at power on (power-on re- set) by connecting resistors, a diode, and a capacitor to RESET pin. Connect RESET pin and the external circuit at the shortest dis- tance. Fig. 34 Power-on reset circuit example (2) Internal state at reset Table 19 shows port state at reset, and Figure 35 shows internal state at reset (they are the same after system is released from re- set). The contents of timers, registers, flags and RAM except shown in Figure 35 are undefined, so set the initial value to them. Table 19 Port state at reset Name D 0–D 5 D 6/CNTR0, D7/CNTR1 P00–P0 3 P10–P1 3 P20/SCK , P21/SOUT , P22/SIN P30/INT0, P31/INT1 P32, P33 (Note 4) P40/AIN4–P43/AIN7 (Note 4) P50–P5 3 (Note 4) Notes 1: Output latch is set to “1.” 2: Pull-up transistor is turned OFF. 3: After system is released from reset, port P5 is in the input mode. (Direction register FR0 = 0000 4: The 4513 Group does not have these ports. Function D 0–D 5 D 6, D7 P00–P0 3 P10–P1 3 P20–P2 2 P30, P31 P32, P33 P40–P43 P50–P5 3 State High impedance (Note) High impedance (Notes 1, 2) High impedance High impedance (Note 1) High impedance (Note 1) High impedance (Note 3) VDD RESET pin WEF (Note) Internal reset signal Voltage drop detection circuit Watchdog timer output VDD RESET pin voltage Power-on Reset released Internal reset signal Reset state Note: This symbol represents a parasitic diode. Applied potential to RESET pin must be VDD or less.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Address 0 in page 0 is set to program counter. “5 ” represents undefined. Fig. 35 Internal state at reset 00000000000000 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0 0 0 0 (Interrupt disabled) 0000 0000 0 0 0 0 (Prescaler and timer 1 stopped) 0 0 0 0 (Timer 2 stopped) 0 0 0 0 (Timer 3 stopped) 0 0 0 0 (Timer 4 stopped) 0000 1000 0000 555555 0000 0000 0000 555555 555555 0000 0000 0 0 0 0 (Port P5: input mode) 0000 0000 555 555555 0000 0000 111 5555 (External clock selected and serial I/O port not selected)

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. VOLTAGE DROP DETECTION CIRCUIT The built-in voltage drop detection circuit is designed to detect a drop in voltage and to reset the microcomputer if the supply voltage drops below a set value. Fig. 37 Voltage drop detection circuit operation waveform Fig. 36 Voltage drop detection reset circuit Voltage drop detection circuit Internal reset signalRESET pin Watchdog timer output WEF Note: The output structure of RESET pin is N-channel open-drain. VDD VRST (detection voltage) Voltage drop detection circuit output The microcomputer starts operation after f(XIN) is counted 16892 to 16895 times. RESET pin Notes 1: Pull-up RESET pin externally. 2: Refer to the voltage drop detection circuit in the electrical characteristics for the rating value of VRST (detection voltage).

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. RAM BACK-UP MODE The 4513/4514 Group has the RAM back-up mode. When the EPOF and POF instructions are executed continuously, system enters the RAM back-up state. The POF instruction is equal to the NOP instruction when the EPOF instruction is not ex- ecuted before the POF instruction. As oscillation stops retaining RAM, the function of reset circuit and states at RAM back-up mode, current dissipation can be reduced without losing the contents of RAM. Table 20 shows the function and states retained at RAM back-up. Figure 38 shows the state transition. (1) Identification of the start condition Warm start (return from the RAM back-up state) or cold start (re- turn from the normal reset state) can be identified by examining the state of the power down flag (P) with the SNZP instruction. (2) Warm start condition When the external wakeup signal is input after the system enters the RAM back-up state by executing the EPOF and POF instruc- tions continuously, the CPU starts executing the program from address 0 in page 0. In this case, the P flag is “1.” (3) Cold start condition The CPU starts executing the program from address 0 in page 0 when;

reset pulse is input to RESET pin, or
reset by watchdog timer is performed, or
voltage drop detection circuit detects the voltage drop. In this case, the P flag is “0.” Table 20 Functions and states retained at RAM back-up Function Program counter (PC), registers A, B, carry flag (CY), stack pointer (SP) (Note 2) Contents of RAM Port level Timer control register W1 Timer control registers W2 to W4, W6 Clock control register MR Interrupt control registers V1, V2 Interrupt control registers I1, I2 Timer 1 function Timer 2 function Timer 3 function Timer 4 function A-D conversion function A-D control registers Q1, Q2 Voltage comparator function Voltage comparator control register Q3 Serial I/O function Serial I/O mode register J1 Pull-up control register PU0 Key-on wakeup control register K0 Direction register FR0 External 0 interrupt request flag (EXF0) External 1 interrupt request flag (EXF1) Timer 1 interrupt request flag (T1F) Timer 2 interrupt request flag (T2F) Timer 3 interrupt request flag (T3F) Timer 4 interrupt request flag (T4F) Watchdog timer flags (WDF1, WDF2) Watchdog timer enable flag (WEF) 16-bit timer (WDT) A-D conversion completion flag (ADF) Serial I/O transmission/reception completion flag (SIOF) Interrupt enable flag (INTE) RAM back-up O O O O (Note 3) (Note 3) (Note 3) O O (Note 5) O O O O O (Note 3) (Note 3) (Note 3) 5 (Note 4) 5 (Note 4) 5 (Note 4) Notes 1:“O” represents that the function can be retained, and “5 ” repre- sents that the function is initialized. Registers and flags other than the above are undefined at RAM back-up, and set an initial value after returning. 2: The stack pointer (SP) points the level of the stack register and is initialized to “7” at RAM back-up. 3: The state of the timer is undefined. 4: Initialize the watchdog timer with the WRST instruction, and then execute the POF instruction. 5: The state is retained when the voltage comparator function is se- lected with the voltage comparator control register Q3.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (4) Return signal An external wakeup signal is used to return from the RAM back-up mode because the oscillation is stopped. Table 21 shows the return condition for each return source. (5) Ports P0 and P1 control registers

Key-on wakeup control register K0 Register K0 controls the ports P0 and P1 key-on wakeup func- tion. Set the contents of this register through register A with the TK0A instruction. In addition, the TAK0 instruction can be used to transfer the contents of register K0 to register A.
Pull-up control register PU0 Register PU0 controls the ON/OFF of the ports P0 and P1 pull-up transistor. Set the contents of this register through register A with the TPU0A instruction. In addition, the TAPU0 instruction can be used to transfer the contents of register PU0 to register A. Table 21 Return source and return condition Remarks Set the port using the key-on wakeup function selected with register K0 to “H” level before going into the RAM back-up state because the port P0 shares the falling edge detection circuit with port P1. Select the return level (“L” level or “H” level) with the bit 2 of register I1 ac- cording to the external state before going into the RAM back-up state. Select the return level (“L” level or “H” level) with the bit 2 of register I2 ac- cording to the external state before going into the RAM back-up state. Return condition Return by an external falling Return by an external “H” level or “L” level input. The EXF0 flag is not set. Return by an external “H” level or “L” level input. The EXF1 flag is not set. External wakeup signal Return source Ports P0, P1 Port P30/INT0 Port P31/INT1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 38 State transition Fig. 39 Set source and clear source of the P flag Fig. 40 Start condition identified example using the SNZP in- struction S R Q Power down flag P POF instruction Reset input or voltage drop detection circuit output l Set source POF instruction is executed l Clear source Reset input Software start P = “1” Yes Warm startCold start No : Time required to stabilize the f(XIN) oscillation is automatically generated by hardware.Stabilizing time a POF instruction is executed A f(XIN) oscillationReturn input (Stabilizing time a ) B (RAM back-up mode) f(XIN) stop Reset (Stabilizing time a )

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Table 22 Key-on wakeup control register, pull-up control register, and interrupt control register K03 K02 K01 K00 Key-on wakeup control register K0 PU0 3 PU0 2 PU0 1 PU0 0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Pins P1 2 and P13 key-on wakeup control bit Pins P1 0 and P11 key-on wakeup control bit Pins P0 2 and P03 key-on wakeup control bit Pins P00 and P01 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pins P1 2 and P13 pull-up transistor control bit Pins P1 0 and P11 pull-up transistor control bit Pins P02 and P03 pull-up transistor control bit Pins P0 0 and P01 pull-up transistor control bit R/W Pull-up control register PU0 at reset : 00002 at RAM back-up : state retained R/W I13 I12 I11 I10 I23 I22 I21 I20 Not used Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Not used Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. Interrupt control register I1 R/Wat RAM back-up : state retainedat reset : 00002 This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Interrupt control register I2 R/Wat RAM back-up : state retainedat reset : 0000

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. CLOCK CONTROL The clock control circuit consists of the following circuits.

System clock generating circuit
Control circuit to stop the clock oscillation Fig. 41 Clock control circuit structure Table 23 Clock control register MR Note : “R” represents read enabled, and “W” represents write enabled.
Control circuit to switch the middle-speed mode and high-speed mode
Control circuit to return from the RAM back-up state MR 3 MR 2 MR 1 MR 0 Clock control register MR f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. System clock selection bit Not used Not used Not used at reset : 10002 at RAM back-up : 10002 R/W Instruction clock MR 3 RESET Falling detected Ports P00, P01 Ports P02, P03 Ports P10, P11 Ports P12, P13 Multi- plexer K00,K01,K02,K03 Counter Wait time (Note) control circuit Software start signal R S Q POF instruction XIN XOUT I12 “L” level P30/INT0 Key-on wake up control register I22 P31/INT1 Oscillation circuit Division circuit (divided by 2) Internal clock generation circuit (divided by 3) “H” level “L” level “H” level Note: The wait time control circuit is used to generate the time required to stabilize the f(XIN) oscillation. System clock

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Clock signal f(XIN) is obtained by externally connecting a ceramic resonator. Connect this external circuit to pins X IN and XOUT at the shortest distance. A feedback resistor is built in between pins XIN and XOUT . When an external clock signal is input, connect the clock source to XIN and leave XOUT open. When using an external clock, the maxi- mum value of external clock oscillating frequency is shown in Table 24. Table 24 Maximum value of external clock oscillation frequency Supply voltage VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V Oscillation frequency (duty ratio)

3.0 MHz (40 % to 60 %)

1.0 MHz (40 % to 60 %)

0.8 MHz (40 % to 60 %)

Please submit the information described below when ordering Mask ROM. (three sets containing the identical data) Fig. 42 Ceramic resonator external circuit Fig. 43 External clock input circuit Note: Externally connect a damping resistor Rd de- pending on the oscillation frequency. (A feedback resistor is built-in.) Use the resonator manu- facturer’s recommended value because constants such as capacitance de- pend on the resonator. Mask ROM version One Time PROM version XIN XOUT Rd C IN C OUT XIN XOUT External oscillation circuit VDD VSS Middle-speed mode High-speed mode Middle-speed mode High-speed mode

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. LIST OF PRECAUTIONS À Noise and latch-up prevention Connect a capacitor on the following condition to prevent noise and latch-up;

connect a bypass capacitor (approx. 0.1 µF) between pins VDD and VSS at the shortest distance,
equalize its wiring in width and length, and
use relatively thick wire. In the One Time PROM version, CNV SS pin is also used as VPP pin. Accordingly, when using this pin, connect this pin to VSS through a resistor about 5 kΩ in series at the shortest distance. \` Prescaler Stop the prescaler operation to change its frequency dividing ra- tio. ´ Timer count source Stop timer 1, 2, 3, or 4 counting to change its count source. ˆ Reading the count value Stop timer 1, 2, 3, or 4 counting and then execute the TAB1, TAB2, TAB3, or TAB4 instruction to read its data. ˜ Writing to reload registers R1 and R3 When writing data to reload registers R1 or R3 while timer 1 or timer 3 is operating, avoid a timing when timer 1 or timer 3 underflows. ¯ P3 0/INT0 pin When the interrupt valid waveform of the P30/INT0 pin is changed with the bit 2 of register I1 in software, be careful about the following notes.
Clear the bit 0 of register V1 to “0” before the interrupt valid wave- form of P3 0/INT0 pin is changed with the bit 2 of register I1 (refer to Figure 44À ).
Depending on the input state of the P30/INT0 pin, the external 0 interrupt request flag (EXF0) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I1, and execute the SNZ0 instruction to clear the EXF0 flag after execut- ing at least one instruction (refer to Figure 44\` ) Fig. 45 External 1 interrupt program example ˙ One Time PROM version The operating power voltage of the One Time PROM version is 2.5 V to 5.5 V. ¨ Multifunction The input of D 6, D7, P20–P22, I/O of P30 and P31, input of CMP0-, CMP0+, CMP1-, CMP1+, and I/O of P40–P4 3 can be used even when CNTR0, CNTR1, S CK , SOUT , SIN, INT0, INT1, AIN0–A IN3 and AIN4–AIN7 are selected. ˘ P31/INT1 pin When the interrupt valid waveform of P31/INT1 pin is changed with the bit 2 of register I2 in software, be careful about the fol- lowing notes.
Clear the bit 1 of register V1 to “0” before the interrupt valid wave- form of P3 1/INT1 pin is changed with the bit 2 of register I2 (refer to Figure 45´ ).
Depending on the input state of the P31/INT1 pin, the external 1 interrupt request flag (EXF1) may be set when the interrupt valid waveform is changed. Accordingly, clear bit 2 of register I2 and execute the SNZ1 instruction to clear the EXF1 flag after execut- ing at least one instruction (refer to Figure 45ˆ ). LA 8 ; ( 55 05 2) LA 8 TI2A ; Change of the interrupt valid waveform SNZ1 ; The SNZ1 instruction is executed NOP 5 : this bit is not related to the setting of INT1. ... ... LA 4 ; ( 555 02) LA 4 ; TI1A ; Interrupt valid waveform is changed SNZ0 ; The SNZ0 instruction is executed NOP 5 : this bit is not related to the setting of INT0 pin. ... Fig. 44 External 0 interrupt program example

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. É A-D converter-1 When the operating mode of the A-D converter is changed from the comparator mode to the A-D conversion mode with the bit 3 of register Q2 in a program, be careful about the following notes.

Clear the bit 2 of register V2 to “0” to change the operating mode of the A-D converter from the comparator mode to the A-D con- version mode with the bit 3 of register Q2 (refer to Figure 46˜ ).
The A-D conversion completion flag (ADF) may be set when the operating mode of the A-D converter is changed from the com- parator mode to the A-D conversion mode. Accordingly, set a value to register Q2, and execute the SNZAD instruction to clear the ADF flag. Do not change the operating mode (both A-D conversion mode and comparator mode) of A-D converter with the bit 3 of register Q2 during operating the A-D converter. LA 8 ; ( 5 055 2) LA 0 ; (0 555 2) TQ2A ; Change of the operating mode of the A-D converter from the comparator mode to the A-D conversion mode SNZAD NOP ... Fig. 47 Analog input external circuit example-1 Fig. 48 Analog input external circuit example-2 POF instruction Execute the POF instruction immediately after executing the EPOF instruction to enter the RAM back-up. Note that system cannot enter the RAM back-up state when ex- ecuting only the POF instruction. Be sure to disable interrupts by executing the DI instruction be- fore executing the EPOF instruction. Analog input pins Note the following when using the analog input pins also for I/O port P4 functions:
Even when P4 0/AIN4–P4 3/AIN7 are set to pins for analog input, they continue to function as P40–P4 3 I/O. Accordingly, when any of them are used as I/O port P4 and others are used as analog input pins, make sure to set the outputs of pins that are set for analog input to “1.” Also, the port input function of the pin func- tions as an analog input is undefined.
TALA instruction When the TALA instruction is executed, the low-order 2 bits of register AD is transferred to the high-order 2 bits of register A, si- multaneously, the low-order 2 bits of register A is “0.” Program counter Make sure that the PC H does not specify after the last page of the built-in ROM. Port P3 In the 4513 Group, when the IAP3 instruction is executed, note that the high-order 2 bits of register A is undefined. A-D converter-2 Each analog input pin is equipped with a capacitor which is used to compare the analog voltage. Accordingly, when the analog voltage is input from the circuit with high-impedance and, charge/ discharge noise is generated and the sufficient A-D accuracy may not be obtained. Therefore, reduce the impedance or, con- nect a capacitor (0.01 µF to 1 µF) to analog input pins (Figure 47). When the overvoltage applied to the A-D conversion circuit may occur, connect an external circuit in order to keep the voltage within the rated range as shown the Figure 48. In addition, test the application products sufficiently. 5 : this bit is not related to the change of the operating mode of the A-D conversion. Fig. 46 A-D converter operating mode program example Sensor AIN Apply the voltage withiin the specifications to an analog input pin. Sensor AIN About 1kΩ

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

16 Voltage comparator function

When the voltage comparator function is valid with the voltage comparator control register Q3, it is operating even in the RAM back-up mode. Accordingly, be careful about such state because it causes the increase of the operation current in the RAM back- up mode. In order to reduce the operation current in the RAM back-up mode, invalidate (bits 2 and 3 of register Q3 = “0”) the voltage comparator function by software before the POF instruction is ex- ecuted. Also, while the voltage comparator function is valid, current is al- ways consumed by voltage comparator. On the system required for the low-power dissipation, invalidate the voltage comparator when it is unused by software. Register Q3 Bits 0 and 1 of register Q3 can be only read. Note that they can- not be written. Reading the comparison result of voltage comparator Read the voltage comparator comparison result from register Q3 after the voltage comparator response time (max. 20 µs) is passed from the voltage comparator function become valid.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. SYMBOL The symbols shown below are used in the following instruction function table and instruction list. Symbol A B DR E AD SI MR PU0 FR0 X Y Z DP PC PC H PC L SK SP CY

Register A (4 bits) Register B (4 bits) Register D (3 bits) Register E (8 bits) A-D control register Q1 (4 bits) A-D control register Q2 (4 bits) Voltage comparator control register Q3 (4 bits) Successive comparison register AD (10 bits) Serial I/O mode register J1 (4 bits) Serial I/O register SI (8 bits) Interrupt control register V1 (4 bits) Interrupt control register V2 (4 bits) Interrupt control register I1 (4 bits) Interrupt control register I2 (4 bits) Timer control register W1 (4 bits) Timer control register W2 (4 bits) Timer control register W3 (4 bits) Timer control register W4 (4 bits) Timer control register W6 (4 bits) Clock control register MR (4 bits) Key-on wakeup control register K0 (4 bits) Pull-up control register PU0 (4 bits) Direction register FR0 (4 bits) Register X (4 bits) Register Y (4 bits) Register Z (2 bits) Data pointer (10 bits) (It consists of registers X, Y, and Z) Program counter (14 bits) High-order 7 bits of program counter Low-order 7 bits of program counter Stack register (14 bits 5 8) Stack pointer (3 bits) Carry flag Timer 1 reload register Timer 2 reload register Timer 3 reload register Timer 4 reload register Timer 1 Timer 2 Timer 3 Timer 4 Timer 1 interrupt request flag Timer 2 interrupt request flag Timer 3 interrupt request flag Timer 4 interrupt request flag Watchdog timer flag Watchdog timer enable flag Interrupt enable flag External 0 interrupt request flag External 1 interrupt request flag Power down flag A-D conversion completion flag Serial I/O transmission/reception completion flag Port D (8 bits) Port P0 (4 bits) Port P1 (4 bits) Port P2 (3 bits) Port P3 (4 bits) Port P4 (4 bits) Port P5 (4 bits) Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal variable Hexadecimal constant Hexadecimal constant Hexadecimal constant Binary notation of hexadecimal variable A (same for others) Direction of data movement Data exchange between a register and memory Decision of state shown before “?” Contents of registers and memories Negate, Flag unchanged after executing instruction RAM address pointed by the data pointer Label indicating address a 6 a5 a4 a3 a2 a1 a0 Label indicating address a6 a5 a4 a3 a2 a1 a0 in page p5 p4 p3 p2 p1 p0 Hex. C + Hex. number x (also same for others) Symbol T1F T2F T3F T4F WDF1 WEF INTE EXF0 EXF1 P ADF SIOF D x y z p n i j A 3A2A1A0 ( ) M(DP) a p, a C x Note :The 4513/4514 Group just invalidates the next instruction when a skip is performed. The contents of program counter is not increased by 2. Accord- ingly, the number of cycles does not change even if skip is not performed. However, the cycle count becomes “1” if the TABP p, RT, or RTS instruction is skipped.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. LIST OF INSTRUCTION FUNCTION Group- ingRAM addresses Function (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15 (PC L) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 Comparison operation Subroutine operation Branch operation Bit operationReturn operation Mnemonic SB j RB j SZB j SEAM SEA n B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS Mnemonic XAMI j TMA j LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR Function (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PC H ) ← p (PCL) ← (DR2–DR 0, A3–A 0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (A) ← (A) + (M(DP)) (CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 Mnemonic TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j Function (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) 7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 (Z) ← z, z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 RAM to register transferArithmetic operation RAM to register transfer Register to register transfer Group- ing Group- ing

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. LIST OF INSTRUCTION FUNCTION (continued) Function (T1F) = 1 ? After skipping (T1F) ← 0 (T2F) = 1 ? After skipping (T2F) ← 0 (T3F) = 1 ? After skipping (T3F) ← 0 (T4F) = 1 ? After skipping (T4F) ← 0 (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) 2–A0) ← (P22–P2 0) (A3) ← 0 (A) ← (P3) (P3) ← (A) (A) ← (P4) (P4) ← (A) (A) ← (P5) (P5) ← (A) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7 Mnemonic SNZT1 SNZT2 SNZT3 SNZT4 IAP0 OP0A IAP1 OP1A IAP2 IAP3 OP3A IAP4* OP4A* IAP5* OP5A* CLD RD SD SZD Input/Output operation Function (A) ← (W4) (W4) ← (A) (A) ← (W6) (W6) ← (A) (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R37–R3 4) ← (B) (T37–T34) ← (B) (R33–R3 0) ← (A) (T33–T30) ← (A) (B) ← (T47–T44) (A) ← (T43–T40) (R47–R4 4) ← (B) (T47–T44) ← (B) (R43–R4 0) ← (A) (T43–T40) ← (A) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (R37–R3 4) ← (B) (R33–R3 0) ← (A) Mnemonic TAW4 TW4A TAW6 TW6A TAB1 T1AB TAB2 T2AB TAB3 T3AB TAB4 T4AB TR1AB TR3AB Function (INTE) ← 0 (INTE) ← 1 (EXF0) = 1 ? After skipping (EXF0) ← 0 (EXF1) = 1 ? After skipping (EXF1) ← 0 (A) ← (V1) (V1) ← (A) (A) ← (V2) (V2) ← (A) (A) ← (I1) (I1) ← (A) (A) ← (I2) (I2) ← (A) (A) ← (W1) (W1) ← (A) (A) ← (W2) (W2) ← (A) (A) ← (W3) (W3) ← (A) Mnemonic DI EI SNZ0 SNZ1 SNZI0 SNZI1 TAV1 TV1A TAV2 TV2A TAI1 TI1A TAI2 TI2A TAW1 TW1A TAW2 TW2A TAW3 TW3A Group- ing Timer operation Interrupt operationTimer operation Group- ing Group- ing Timer operation *: The 4513 Group does not have these instructions.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. LIST OF INSTRUCTION FUNCTION (continued) Mnemonic TK0A TAK0 TPU0A TAPU0 TFR0A* TABSI TSIAB TAJ1 TJ1A SST SNZSI Function (K0) ← (A) (A) ← (K0) (PU0) ← (A) (A) ← (PU0) (FR0) ← (A) (A) ← (SI3–SI0) (B) ← (SI7–SI4) (SI3–SI0) ← (A) (SI7–SI4) ← (B) (A) ← (J1) (J1) ← (A) (SIOF) ← 0 Serial I/O starting (SIOF) = 1 ? After skipping (SIOF) ← 0 Mnemonic TABAD TALA TADAB TAQ1 TQ1A ADST SNZAD TAQ2 TQ2A NOP POF EPOF SNZP WRST TAMR TMRA TAQ3 TQ3A Function (A) ← (AD5–AD 2) (B) ← (AD9–AD 6) However, in the com- parator mode, (A) ← (AD3–AD 0) (B) ← (AD7–AD 4) (AD3–AD 0) ← (A) (AD7–AD 4) ← (B) (A) ← (Q1) (Q1) ← (A) (ADF) ← 0 A-D conversion starting (ADF) = 1 ? After skipping (ADF) ← 0 (A) ← (Q2) (Q2) ← (A) (PC) ← (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? (WDF1) ← 0, (WEF) ← 1 (A) ← (MR) (MR) ← (A) (A) ← (Q3) (Q3 3, Q32) ← (A3, A2) (Q3 1) ← (CMP1 com- parison result) (Q3 0) ← (CMP0 com- parison result) Serial I/O control operation Input/Output operation Other operation A-D conversion operation *: The 4513 Group does not have these instructions. Group- ing Group- ing

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. INSTRUCTION CODE TABLE (for 4513 Group) D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 NOP POF SNZP DI EI RC SC AM AMC TYA TBA 000001 BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY 000010 SZB SZB SZB SZB SZD SEAn SEAM TDA TABE SZC 000011 BMLA SNZ0 SNZ1 SNZI0 SNZI1 TV2A TV1A 000100 RT RTS RTI LZ LZ LZ LZ RB RB RB RB 000101 TASP TAD TAX TAZ TAV1 TAV2 EPOF SB SB SB SB 000110 A A A A A A A A A A A A A A A A 000111 LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA 001000 TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP 001001 TABP 16* TABP 17* TABP 18* TABP 19* TABP 20* TABP 21* TABP 22* TABP 23* TABP 24* TABP 25* TABP 26* TABP 27* TABP 28* TABP 29* TABP 30* TABP 31* 001010 001011 001100 001101 001110 001111 BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML* BML* BML* BML* BML* BML* BML* BML* BML* BML* BML* BML* BML* BML* BML* BML* BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BL* BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 010000 010111 011000 011111 18–1F B B B B B B B B B B B B B B B B BL BML BLA BMLA SEA SZD The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 TABP 32 TABP 33 TABP 34 TABP 35 TABP 36 TABP 37 TABP 38 TABP 39 TABP 40 TABP 41 TABP 42 TABP 43 TABP 44 TABP 45 TABP 46 TABP 47 TABP 48* TABP 49* TABP 50* TABP 51* TABP 52* TABP 53* TABP 54* TABP 55* TABP 56* TABP 57* TABP 58* TABP 59* TABP 60* TABP 61* TABP 62* TABP 63*

*, , and * cannot be used in the M34513M2-XXXSP/FP .
* and ** cannot be used in the M34513M4-XXXSP/FP.
* and ** cannot be used in the M34513E4FP.
* cannot be used in the M34513M6-XXXFP. 10–17 000000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representa- tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. INSTRUCTION CODE TABLE (continued) (for 4513 Group) TJ1A TQ1A TQ2A TQ3A TW1A TW2A TW3A TW4A TW6A TMRA TI1A TI2A TK0A T1AB T2AB T3AB T4AB TSIAB TADAB TR3AB TR1AB TAJ1 TAQ1 TAQ2 TAQ3 TALA TAW1 TAW2 TAW3 TAW4 TAW6 TAMR TAI1 TAI2 TAK0 TAPU0 IAP0 IAP1 IAP2 IAP3 TAB1 TAB2 TAB3 TAB4 TABSI TABAD SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI SST ADST WRST TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA BL BML BLA BMLA SEA SZD The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 OP0A OP1A OP3A TPU0A D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 111111 30–3F 100000 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low- order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. INSTRUCTION CODE TABLE (for 4514 Group) NOP POF SNZP DI EI RC SC AM AMC TYA TBA BLA CLD INY RD SD DEY AND OR TEAB CMA RAR TAB TAY SZB SZB SZB SZB SZD SEAn SEAM TDA TABE SZC BMLA SNZ0 SNZ1 SNZI0 SNZI1 TV2A TV1A RT RTS RTI LZ LZ LZ LZ RB RB RB RB TASP TAD TAX TAZ TAV1 TAV2 EPOF SB SB SB SB A A A A A A A A A A A A A A A A LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA LA TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP TABP BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BML BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL BL TABP 48* TABP 49* TABP 50* TABP 51* TABP 52* TABP 53* TABP 54* TABP 55* TABP 56* TABP 57* TABP 58* TABP 59* TABP 60* TABP 61* TABP 62* TABP 63* D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 000001 000010 000011 000100 000101 000110 000111 001000 001001 001010 001011 001100 001101 001110 001111 BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM BM 010000 010111 011000 011111 18–1F B B B B B B B B B B B B B B B B 10–17 000000 BL BML BLA BMLA SEA SZD The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011

* cannot be used in the M34514M6-XXXFP. The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low-order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representa- tion of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. INSTRUCTION CODE TABLE (continued) (for 4514 Group) TJ1A TQ1A TQ2A TQ3A TW1A TW2A TW3A TW4A TW6A TMRA TI1A TI2A TK0A T1AB T2AB T3AB T4AB TSIAB TADAB TR3AB TR1AB TAJ1 TAQ1 TAQ2 TAQ3 TALA TAW1 TAW2 TAW3 TAW4 TAW6 TAMR TAI1 TAI2 TAK0 TAPU0 IAP0 IAP1 IAP2 IAP3 IAP4 IAP5 TAB1 TAB2 TAB3 TAB4 TABSI TABAD SNZT1 SNZT2 SNZT3 SNZT4 SNZAD SNZSI OP0A OP1A OP3A OP4A OP5A TFR0A TPU0A SST ADST WRST TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM TAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAM XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMI XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD XAMD LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY LXY TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA TMA D 3–D 0 Hex. notation 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 A B C D E F D 9–D 4 100001 100010 100011 100100 100101 100110 100111 101000 101001 101010 101011 101100 101101 101110 101111 110000 111111 30–3F 100000 BL BML BLA BMLA SEA SZD The second word 10 paaa aaaa 10 paaa aaaa 10 pp00 pppp 10 pp00 pppp 00 0111 nnnn 00 0010 1011 The above table shows the relationship between machine language codes and machine language instructions. D3–D 0 show the low- order 4 bits of the machine language code, and D9–D 4 show the high-order 6 bits of the machine language code. The hexadecimal representation of the code is also provided. There are one-word instructions and two-word instructions, but only the first word of each instruction is shown. Do not use code marked “–.” The codes for the second word of a two-word instruction are described below.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (A) ← (B) (B) ← (A) (A) ← (Y) (Y) ← (A) (E7–E4) ← (B) (E3–E0) ← (A) (B) ← (E7–E4) (A) ← (E3–E0) (DR 2–DR 0) ← (A2–A0) (A2–A0) ← (DR2–DR 0) (A3) ← 0 (A3, A2) ← 0 (A) ← (X) (A2–A0) ← (SP2–SP 0) (A3) ← 0 (X) ← x, x = 0 to 15 (Y) ← y, y = 0 to 15 (Z) ← z, z = 0 to 3 (Y) ← (Y) + 1 (Y) ← (Y) – 1 (A) ← (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) – 1 (A) ← → (M(DP)) (X) ← (X)EXOR(j) j = 0 to 15 (Y) ← (Y) + 1 (M(DP)) ← (A) (X) ← (X)EXOR(j) j = 0 to 15 TAB TBA TAY TYA TEAB TABE TDA TAD TAZ TAX TASP LXY x, y LZ z INY DEY TAM j XAM j XAMD j XAMI j TMA j MACHINE INSTRUCTIONS 0000011110 0000001110 0000011111 0000001100 0000011010 0000101010 0000101001 0001010001 0001010011 0001010010 0001010000 11x 3 x2 x1 x0 y3 y2 y1 y0 00010010z 1 z0 0000010011 0000010111 101100 jjjj 101101 jjjj 101111 jjjj 101110 jjjj 101011 jjjj 01E 00E 01F 00C 01A 02A 029 051 053 052 050 3xy 048 013 017 2C j 2D j 2Fj 2Ej 2Bj RAM addressesRAM to register transfer Register to register transfer

Skip condition Datailed description Carry flag CY 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Transfers the contents of register B to register A. Transfers the contents of register A to register B. Transfers the contents of register Y to register A. Transfers the contents of register A to register Y. Transfers the contents of registers A and B to register E. Transfers the contents of register E to registers A and B. Transfers the contents of register A to register D. Transfers the contents of register D to register A. Transfers the contents of register Z to register A. Transfers the contents of register X to register A. Transfers the contents of stack pointer (SP) to register A. Loads the value x in the immediate field to register X, and the value y in the immediate field to register Y. When the LXY instructions are continuously coded and executed, only the first LXY instruction is executed and other LXY instructions coded continuously are skipped. Loads the value z in the immediate field to register Z. Adds 1 to the contents of register Y . As a result of addition, when the contents of register Y is 0, the next in- struction is skipped. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After transferring the contents of M(DP) to register A, an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Subtracts 1 from the contents of register Y. As a result of subtraction, when the contents of register Y is 15, the next instruction is skipped. After exchanging the contents of M(DP) with the contents of register A, an exclusive OR operation is per- formed between register X and the value j in the immediate field, and stores the result in register X. Adds 1 to the contents of register Y. As a result of addition, when the contents of register Y is 0, the next instruction is skipped. After transferring the contents of register A to M(DP), an exclusive OR operation is performed between reg- ister X and the value j in the immediate field, and stores the result in register X. Continuous (Y) = 0 (Y) = 15 (Y) = 15 (Y) = 0

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Note :p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8. MACHINE INSTRUCTIONS (continued) 07n 08p 00A 00B 06n 018 019 007 006 02F 01C 01D 05C 04C 02j 026 025 07n 000111nnnn 0010p 5 p4 p3 p2 p1 p0 0000001010 0000001011 000110nnnn 0000011000 0000011001 0000000111 0000000110 0000101111 0000011100 0000011101 00010111j j 00010011j j 00001000j j 0000100110 0000100101 000111nnnn LA n TABP p AM AMC A n AND OR SC RC SZC CMA RAR SB j RB j SZB j SEAM SEA n Arithmetic operationComparison operation Bit operation (A) ← n n = 0 to 15 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (B) ← (ROM(PC))7–4 (A) ← (ROM(PC))3–0 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (Note) (A) ← (A) + (M(DP)) (A) ← (A) + (M(DP)) +(CY) (CY) ← Carry (A) ← (A) + n n = 0 to 15 (A) ← (A) AND (M(DP)) (A) ← (A) OR (M(DP)) (CY) ← 1 (CY) ← 0 (CY) = 0 ? (A) ← (A) → CY → A 3A2A1A0 (Mj(DP)) ← 1 j = 0 to 3 (Mj(DP)) ← 0 j = 0 to 3 (Mj(DP)) = 0 ? j = 0 to 3 (A) = (M(DP)) ? (A) = n ? n = 0 to 15

Skip condition Datailed description Carry flag CY 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Continuous Overflow = 0 (CY) = 0 (Mj(DP)) = 0 j = 0 to 3 (A) = (M(DP)) (A) = n Loads the value n in the immediate field to register A. When the LA instructions are continuously coded and executed, only the first LA instruction is executed and other LA instructions coded continuously are skipped. Transfers bits 7 to 4 to register B and bits 3 to 0 to register A. These bits 7 to 0 are the ROM pattern in ad- dress (DR 2 DR1 DR0 A3 A2 A1 A0)2 specified by registers A and D in page p. When this instruction is executed, 1 stage of stack register is used. Adds the contents of M(DP) to register A. Stores the result in register A. The contents of carry flag CY re- mains unchanged. Adds the contents of M(DP) and carry flag CY to register A. Stores the result in register A and carry flag CY. Adds the value n in the immediate field to register A. The contents of carry flag CY remains unchanged. Skips the next instruction when there is no overflow as the result of operation. Takes the AND operation between the contents of register A and the contents of M(DP), and stores the re- sult in register A. Takes the OR operation between the contents of register A and the contents of M(DP), and stores the result in register A. Sets (1) to carry flag CY. Clears (0) to carry flag CY. Skips the next instruction when the contents of carry flag CY is “0.” Stores the one’s complement for register A’s contents in register A. Rotates 1 bit of the contents of register A including the contents of carry flag CY to the right. Sets (1) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Clears (0) the contents of bit j (bit specified by the value j in the immediate field) of M(DP). Skips the next instruction when the contents of bit j (bit specified by the value j in the immediate field) of M(DP) is “0.” Skips the next instruction when the contents of register A is equal to the contents of M(DP). Skips the next instruction when the contents of register A is equal to the value n in the immediate field.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. B a BL p, a BLA p BM a BML p, a BMLA p RTI RT RTS DI EI SNZ0 SNZ1 011a 6 a5 a4 a3 a2 a1 a0 00111p 4 p3 p2 p1 p0 10p 5 a6 a5 a4 a3 a2 a1 a0 0000010000 10p 5 p4 00p 3 p2 p1 p0 010a 6 a5 a4 a3 a2 a1 a0 00110p 4 p3 p2 p1 p0 10p 5 a6 a5 a4 a3 a2 a1 a0 0000110000 10p 5 p4 00p 3 p2 p1 p0 0001000110 0001000100 0001000101 0000000100 0000000101 0000111000 0000111001 18a 0Ep 2pa 010 2pp 1aa 0C p 2pa 030 2pp 046 044 045 004 005 038 039 Subroutine operationReturn operationInterrupt operation MACHINE INSTRUCTIONS (continued) (PCL) ← a6–a0 (PCH ) ← p (PCL) ← a6–a0 (Note) (PCH ) ← p (PCL) ← (DR2–DR 0, A3–A0) (Note) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← 2 (PCL) ← a6–a0 (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← a6–a0 (Note) (SP) ← (SP) + 1 (SK(SP)) ← (PC) (PCH ) ← p (PCL) ← (DR2–DR 0,A3–A0) (Note) (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (PC) ← (SK(SP)) (SP) ← (SP) – 1 (INTE) ← 0 (INTE) ← 1 (EXF0) = 1 ? After skipping (EXF0) ← 0 (EXF1) = 1 ? After skipping (EXF1) ← 0 Branch operation Note :p is 0 to 15 for M34513M2, p is 0 to 31 for M34513M4/E4, p is 0 to 47 for M34513M6 and M34514M6, and p is 0 to 63 for M34513M8/E8 and M34514M8/E8.

Skip condition Datailed description Carry flag CY 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Skip at uncondition (EXF0) = 1 (EXF1) = 1 Branch within a page : Branches to address a in the identical page. Branch out of a page : Branches to address a in page p. Branch out of a page : Branches to address (DR

2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in

page p. Call the subroutine in page 2 : Calls the subroutine at address a in page 2. Call the subroutine : Calls the subroutine at address a in page p. Call the subroutine : Calls the subroutine at address (DR2 DR1 DR0 A3 A2 A1 A0)2 specified by registers D and A in page p. Returns from interrupt service routine to main routine. Returns each value of data pointer (X, Y, Z), carry flag, skip status, NOP mode status by the continuous de- scription of the LA/LXY instruction, register A and register B to the states just before interrupt. Returns from subroutine to the routine called the subroutine. Returns from subroutine to the routine called the subroutine, and skips the next instruction at uncondition. Clears (0) to the interrupt enable flag INTE, and disables the interrupt. Sets (1) to the interrupt enable flag INTE, and enables the interrupt. Skips the next instruction when the contents of EXF0 flag is “1.” After skipping, clears (0) to the EXF0 flag. Skips the next instruction when the contents of EXF1 flag is “1.” After skipping, clears (0) to the EXF1 flag.

Skip condition Datailed description Carry flag CY 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. When bit 2 (I12) of register I1 is “1” : Skips the next instruction when the level of INT0 pin is “H.” When bit 2 (I12) of register I1 is “0” : Skips the next instruction when the level of INT0 pin is “L.” When bit 2 (I22) of register I2 is “1” : Skips the next instruction when the level of INT1 pin is “H.” When bit 2 (I22) of register I2 is “0” : Skips the next instruction when the level of INT1 pin is “L.” Transfers the contents of interrupt control register V1 to register A. Transfers the contents of register A to interrupt control register V1. Transfers the contents of interrupt control register V2 to register A. Transfers the contents of register A to interrupt control register V2. Transfers the contents of interrupt control register I1 to register A. Transfers the contents of register A to interrupt control register I1. Transfers the contents of interrupt control register I2 to register A. Transfers the contents of register A to interrupt control register I2. Transfers the contents of timer control register W1 to register A. Transfers the contents of register A to timer control register W1. Transfers the contents of timer control register W2 to register A. Transfers the contents of register A to timer control register W2. Transfers the contents of timer control register W3 to register A. Transfers the contents of register A to timer control register W3. Transfers the contents of timer control register W4 to register A. Transfers the contents of register A to timer control register W4. Transfers the contents of timer control register W6 to register A. Transfers the contents of register A to timer control register W6. (INT0) = “H” However, I1 2 = 1 (INT0) = “L” However, I12 = 0 (INT1) = “H” However, I22 = 1 (INT1) = “L” However, I22 = 0

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MACHINE INSTRUCTIONS (continued) TAB1 T1AB TAB2 T2AB TAB3 T3AB TAB4 T4AB TR1AB TR3AB SNZT1 SNZT2 SNZT3 SNZT4 270 230 271 231 272 232 273 233 23F 23B 280 281 282 283 1001110000 1000110000 1001110001 1000110001 1001110010 1000110010 1001110011 1000110011 1000111111 1000111011 1010000000 1010000001 1010000010 1010000011 (B) ← (T17–T14) (A) ← (T13–T10) (R17–R1 4) ← (B) (T17–T14) ← (B) (R13–R1 0) ← (A) (T13–T10) ← (A) (B) ← (T27–T24) (A) ← (T23–T20) (R27–R2 4) ← (B) (T27–T24) ← (B) (R23–R2 0) ← (A) (T23–T20) ← (A) (B) ← (T37–T34) (A) ← (T33–T30) (R37–R3 4) ← (B) (T37–T34) ← (B) (R33–R3 0) ← (A) (T33–T30) ← (A) (B) ← (T47–T44) (A) ← (T43–T40) (R47–R4 4) ← (B) (T47–T44) ← (B) (R43–R4 0) ← (A) (T43–T40) ← (A) (R17–R1 4) ← (B) (R13–R1 0) ← (A) (R37–R3 4) ← (B) (R33–R3 0) ← (A) (T1F) = 1 ? After skipping (T1F) ← 0 (T2F) = 1 ? After skipping (T2F) ← 0 (T3F) = 1 ? After skipping (T3F) ← 0 (T4F) = 1 ? After skipping (T4F) ← 0 Timer operation

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MACHINE INSTRUCTIONS (continued) IAP0 OP0A IAP1 OP1A IAP2 IAP3 OP3A IAP4* OP4A* IAP5* OP5A* CLD RD SD SZD TK0A TAK0 TPU0A TAPU0 TFR0A* 260 220 261 221 262 263 223 264 224 265 225 011 014 015 024 02B 21B 256 22D 257 228 1001100000 1000100000 1001100001 1000100001 1001100010 1001100011 1000100011 1001100100 1000100100 1001100101 1000100101 0000010001 0000010100 0000010101 0000100100 0000101011 1000011011 1001010110 1000101101 1001010111 1000101000 Input/Output operation (A) ← (P0) (P0) ← (A) (A) ← (P1) (P1) ← (A) (A3) ← 0 (A) ← (P3) (P3) ← (A) (A) ← (P4) (P4) ← (A) (A) ← (P5) (P5) ← (A) (D) ← 1 (D(Y)) ← 0 (Y) = 0 to 7 (D(Y)) ← 1 (Y) = 0 to 7 (D(Y)) = 0 ? (Y) = 0 to 7 (K0) ← (A) (A) ← (K0) (PU0) ← (A) (A) ← (PU0) (FR0) ← (A) *: The 4513 Group does not have these instructions.

Parameter Instruction code Function Number of cycles Number of words Mnemonic Type of instructions D 9 D 8 D 7 D 6 D 5 D 4 D 3 D 2 D 1 D 0 Hexadecimal notation 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. MACHINE INSTRUCTIONS (continued) TABSI TSIAB TAJ1 TJ1A SST SNZSI TABAD TALA TADAB TAQ1 TQ1A ADST SNZAD TAQ2 TQ2A NOP POF EPOF SNZP WRST TAMR TMRA TAQ3 TQ3A 278 238 242 202 29E 288 279 249 239 244 204 29F 287 245 205 000 002 05B 003 2A0 252 216 246 206 1001111000 1000111000 1001000010 1000000010 1010011110 1010001000 1001111001 1001001001 1000111001 1001000100 1000000100 1010011111 1010000111 1001000101 1000000101 0000000000 0000000010 0001011011 0000000011 1010100000 1001010010 1000010110 1001000110 1000000110 A-D conversion operationOther operation (A) ← (SI3–SI0) (B) ← (SI7–SI4) (SI3–SI0) ← (A) (SI7–SI4) ← (B) (A) ← (J1) (J1) ← (A) (SIOF) ← 0 Serial I/O starting (SIOF) = 1 ? After skipping (SIOF) ← 0 (A) ← (AD 5–AD 2) (B) ← (AD9–AD 6) However, in the comparator mode, (A) ← (AD 3–AD 0) (B) ← (AD7–AD 4) (AD3–AD 0) ← (A) (AD7–AD 4) ← (B) (A) ← (Q1) (Q1) ← (A) (ADF) ← 0 A-D conversion starting (ADF) = 1 ? After skipping (ADF) ← 0 (A) ← (Q2) (Q2) ← (A) (PC) ← (PC) + 1 RAM back-up POF instruction valid (P) = 1 ? (WDF1) ← 0 (WEF) ← 1 (A) ← (MR) (MR) ← (A) (A) ← (Q3) (Q3 3, Q32) ← (A3, A2) (Q31) ← (CMP1 comparison result) (Q30) ← (CMP0 comparison result) Serial I/O control operation

Skip condition Datailed description Carry flag CY 4513/4514 Group SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. (SIOF) = 1 (ADF) = 1 (P) = 1 Transfers the contents of serial I/O register SI to registers A and B. Transfers the contents of registers A and B to serial I/O register SI. Transfers the contents of serial I/O mode register J1 to register A. Transfers the contents of register A to serial I/O mode register J1. Clears (0) to SIOF flag and starts serial I/O. Skips the next instruction when the contents of SIOF flag is “1.” After skipping, clears (0) to SIOF flag. Transfers the high-order 8 bits of the contents of register AD to registers A and B. Transfers the low-order 2 bits of the contents of register AD to the high-order 2 bits of the contents of regis- ter A. Simultaneously, the low-order 2 bits of the contents of the register A is “0.” Transfers the contents of registers A and B to the comparator register at the comparator mode. Transfers the contents of the A-D control register Q1 to register A. Transfers the contents of register A to the A-D control register Q1. Clears the ADF flag, and the A-D conversion at the A-D conversion mode or the comparator operation at the comparator mode is started. Skips the next instruction when the contents of ADF flag is “1”. After skipping, clears (0) the contents of ADF flag. Transfers the contents of the A-D control register Q2 to register A. Transfers the contents of register A to the A-D control register Q2. No operation Puts the system in RAM back-up state by executing the POF instruction after executing the EPOF instruction. Makes the immediate POF instruction valid by executing the EPOF instruction. Skips the next instruction when P flag is “1”. After skipping, P flag remains unchanged. Operates the watchdog timer and initializes the watchdog timer flag WDF1. Transfers the contents of the clock control register MR to register A. Transfers the contents of register A to the clock control register MR. Transfers the contents of the voltage comparator control register Q3 to register A. Transfers the contents of the high-order 2 bits of register A to the high-order 2 bits of voltage comparator control register Q3, and the comparison result of the voltage comparator is transferred to the low-order 2 bits of the register Q3.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. V13 V12 V11 V10 V23 V22 V21 V20 Serial I/O interrupt enable bit A-D interrupt enable bit Timer 4 interrupt enable bit Timer 3 interrupt enable bit Interrupt control register V1 Timer 2 interrupt enable bit Timer 1 interrupt enable bit External 1 interrupt enable bit External 0 interrupt enable bit Interrupt disabled (SNZT2 instruction is valid) Interrupt enabled (SNZT2 instruction is invalid) Interrupt disabled (SNZT1 instruction is valid) Interrupt enabled (SNZT1 instruction is invalid) Interrupt disabled (SNZ1 instruction is valid) Interrupt enabled (SNZ1 instruction is invalid) Interrupt disabled (SNZ0 instruction is valid) Interrupt enabled (SNZ0 instruction is invalid) Interrupt disabled (SNZSI instruction is valid) Interrupt enabled (SNZSI instruction is invalid) Interrupt disabled (SNZAD instruction is valid) Interrupt enabled (SNZAD instruction is invalid) Interrupt disabled (SNZT4 instruction is valid) Interrupt enabled (SNZT4 instruction is invalid) Interrupt disabled (SNZT3 instruction is valid) Interrupt enabled (SNZT3 instruction is invalid) R/Wat RAM back-up : 0000 2at reset : 00002 R/Wat RAM back-up : 00002at reset : 00002 Interrupt control register V2 R/Wat RAM back-up : 00002at reset : 00002 CONTROL REGISTERS I13 I12 I11 I10 I23 I22 I21 I20 Not used Interrupt valid waveform for INT0 pin/ return level selection bit (Note 2) INT0 pin edge detection circuit control bit INT0 pin timer 1 control enable bit This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT1 pin is recognized with the SNZI1 instruction)/“L” level Rising waveform (“H” level of INT1 pin is recognized with the SNZI1 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Not used Interrupt valid waveform for INT1 pin/ return level selection bit (Note 3) INT1 pin edge detection circuit control bit INT1 pin timer 3 control enable bit Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: When the contents of I12 is changed, the external interrupt request flag EXF0 may be set. Accordingly, clear EXF0 flag with the SNZ0 instruction. 3: When the contents of I22 is changed, the external interrupt request flag EXF1 may be set. Accordingly, clear EXF1 flag with the SNZ1 instruction. Interrupt control register I1 R/Wat RAM back-up : state retainedat reset : 00002 This bit has no function, but read/write is enabled. Falling waveform (“L” level of INT0 pin is recognized with the SNZI0 instruction)/“L” level Rising waveform (“H” level of INT0 pin is recognized with the SNZI0 instruction)/“H” level One-sided edge detected Both edges detected Disabled Enabled Interrupt control register I2 R/Wat RAM back-up : state retainedat reset : 0000

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Stop (state initialized) Operating Instruction clock divided by 4 Instruction clock divided by 16 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Prescaler control bit Prescaler dividing ratio selection bit Timer 1 control bit Timer 1 count start synchronous circuit control bit Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 1 underflow signal Prescaler output CNTR0 input 16 bit timer (WDT) underflow signal Timer 2 control bit Not used Timer 2 count source selection bits W1 2 W1 1 W1 0 W2 3 W2 2 W2 1 W2 0 W3 3 W3 2 W3 1 W3 0 W4 3 W4 2 W4 1 W4 0 W6 3 W6 2 W6 1 W6 0 Timer control register W1 R/Wat RAM back-up : 00002at reset : 00002 R/Wat RAM back-up : 00002at reset : 00002 Timer control register W2 R/Wat RAM back-up : state retainedat reset : 00002 W3 1 Stop (state retained) Operating Count start synchronous circuit not selected Count start synchronous circuit selected Count source Timer 2 underflow signal Prescaler output Not available Not available Timer 3 control bit Timer 3 count start synchronous circuit control bit Timer 3 count source selection bits Timer control register W3 R/Wat RAM back-up : state retainedat reset : 00002 W4 1 Stop (state retained) Operating This bit has no function, but read/write is enabled. Count source Timer 3 underflow signal Prescaler output CNTR1 input Not available Timer 4 control bit Not used Timer 4 count source selection bits Timer control register W4 R/Wat RAM back-up : state retainedat reset : 00002 Timer 3 underflow signal output divided by 2 CNTR1 output control by timer 4 underflow signal divided by 2 D 7(I/O)/CNTR1 input CNTR1 (I/O)/D7(input) Timer 1 underflow signal output divided by 2 CNTR0 output control by timer 2 underflow signal divided by 2 D 6(I/O)/CNTR0 input CNTR0 (I/O)/D6(input) CNTR1 output control bit D 7/CNTR1 function selection bit CNTR0 output control bit D 6/CNTR0 output control bit Timer control register W6 R/Wat RAM back-up : state retainedat reset : 00002 Note: “R” represents read enabled, and “W” represents write enabled.

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Selected pins AIN0 AIN1 AIN2 AIN3 AIN4 (Not available for the 4513 Group) AIN5 (Not available for the 4513 Group) AIN6 (Not available for the 4513 Group) AIN7 (Not available for the 4513 Group) This bit has no function, but read/write is enabled. Instruction clock signal divided by 8 Instruction clock signal divided by 4 Input ports P2 0, P21, P22 selected Serial I/O ports SCK , SOUT , SIN/input ports P20, P21, P22 selected External clock Internal clock (instruction clock divided by 4 or 8) J12 J11 J10 Serial I/O mode register J1 Not used Serial I/O internal clock dividing ratio selection bit Serial I/O port selection bit Serial I/O synchronous clock selection bit at reset : 00002 at RAM back-up : state retained R/W Q1 3 Q1 2 Q1 1 Q1 0 A-D control register Q1 Note used Analog input pin selection bits (Note 2) at reset : 00002 at RAM back-up : state retained Q12 This bit has no function, but read/write is enabled. at reset : 00002 Q2 3 Q2 2 Q2 1 Q2 0 A-D control register Q2 A-D conversion mode Comparator mode 3, P42 (read/write enabled for the 4513 Group) AIN7, AIN6/P43, P42 (read/write enabled for the 4513 Group) P41 (read/write enabled for the 4513 Group) AIN5/P41 (read/write enabled for the 4513 Group) P40 (read/write enabled for the 4513 Group) AIN4/P40 (read/write enabled for the 4513 Group) A-D operation mode selection bit P4 3/AIN7 and P42/AIN6 pin function selec- tion bit (Not used for the 4513 Group) P41/AIN5 pin function selection bit (Not used for the 4513 Group) 0/AIN4 pin function selection bit (Not used for the 4513 Group) at RAM back-up : state retained Notes 1: “R” represents read enabled, “W” represents write enabled. 2: Select AIN4–A IN7 with register Q1 after setting register Q2. 3: Bits 0 and 1 of register Q3 can be only read. Q10 R/W R/W MR 3 MR 2 MR 1 MR 0 Clock control register MR f(XIN) (high-speed mode) f(XIN)/2 (middle-speed mode) This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. This bit has no function, but read/write is enabled. System clock selection bit Not used Not used Not used at reset : 10002 at RAM back-up : 10002 R/W Q3 3 Q3 2 Q3 1 Q3 0 Comparator control register Q3 (Note 3) at reset : 00002 at RAM back-up : state retained R/W Voltage comparator (CMP1) invalid Voltage comparator (CMP1) valid Voltage comparator (CMP0) invalid Voltage comparator (CMP0) valid CMP1- > CMP1+ CMP1- < CMP1+ CMP0- > CMP0+ CMP0- < CMP0+ Voltage comparator (CMP1) control bit Voltage comparator (CMP0) control bit CMP1 comparison result store bit CMP0 comparison reslut store bit

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. K03 K02 K01 K00 Key-on wakeup control register K0 PU0 3 PU0 2 PU0 1 PU0 0 Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Key-on wakeup not used Key-on wakeup used Pins P1 2 and P13 key-on wakeup control bit Pins P10 and P11 key-on wakeup control bit Pins P0 2 and P03 key-on wakeup control bit Pins P0 0 and P01 key-on wakeup control bit at reset : 00002 at RAM back-up : state retained Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pull-up transistor OFF Pull-up transistor ON Pins P1 2 and P13 pull-up transistor control bit Pins P1 0 and P11 pull-up transistor control bit Pins P0 2 and P03 pull-up transistor control bit Pins P00 and P01 pull-up transistor control bit R/W Pull-up control register PU0 at reset : 00002 at RAM back-up : state retained R/W Notes 1: “R” represents read enabled, and “W” represents write enabled. 2: The 4513 Group does not have the direction register FR0. FR0 3 FR0 2 FR0 1 FR0 0 Port P53 input Port P53 output Port P52 input Port P52 output Port P51 input Port P51 output Port P50 input Port P50 output Port P53 input/output control bit Port P52 input/output control bit Port P51 input/output control bit Port P50 input/output control bit Direction register FR0 (Note 2) at reset : 00002 at RAM back-up : state retained W

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. ABSOLUTE MAXIMUM RATINGS Parameter Supply voltage Input voltage P0, P1, P2, P3, P4, P5, RESET , XIN, VDCE Input voltage D0–D 7 Input voltage AIN0–AIN7 Output voltage P0, P1, P3, P4, P5, RESET Output voltage D0–D 7 Output voltage XOUT Power dissipation Operating temperature range Storage temperature range Conditions Output transistors in cut-off state Ta = 25 °C Symbol VDD VI VI VI VO VO VO Pd Topr Tstg Package: 42P2R Package: 32P6B Package: 32P4B Unit V V V V V V V mW Ratings –0.3 to 7.0 –0.3 to VDD +0.3 –0.3 to 13 –0.3 to VDD +0.3 –0.3 to VDD +0.3 –0.3 to 13 –0.3 to VDD +0.3 300 300 1100 –20 to 85 –40 to 125

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. RECOMMENDED OPERATING CONDITIONS 1 (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol VDD VRAM VSS VIH VIH VIH VIH VIL VIL VIL IOH (peak) IOH (avg) IOL (peak) IOL (peak) IOL (peak) IOL (peak) IOL (avg) IOL (avg) IOL (avg) IOL (avg) ΣIOH (avg) ΣIOL (avg) Parameter Supply voltage RAM back-up voltage (at RAM back-up mode) Supply voltage “H” level input voltage “H” level input voltage “H” level input voltage “H” level input voltage “L” level input voltage “L” level input voltage “L” level input voltage “H” level peak output current “H” level average output current “L” level peak output current “L” level peak output current “L” level peak output current “L” level peak output current “L” level average output current “L” level average output current “L” level average output current “L” level average output current “H” level total average current “L” level total average current Note: The average output current (IOH , IOL ) is the average value during 100 ms. Unit V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA Conditions Mask ROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version Middle-speed mode One Time PROM version High-speed mode Mask ROM version One Time PROM version P0, P1, P2, P3, P4, P5, X IN, VDCE D 0–D 7 RESET CNTR0, CNTR1, S IN, SCK , INT0, INT1 P0, P1, P2, P3, P4, P5, D0–D 7, XIN, VDCE RESET CNTR0, CNTR1, S IN, SCK , INT0, INT1 P5 (Note) P3, RESET D 6, D7 D 0–D 5 P0, P1, P4, P5, SCK , SOUT P3, RESET (Note) D 6, D7 (Note) D 0–D 5 (Note) P0, P1, P4, P5, SCK , SOUT (Note) P5, D, RESET , SCK , SOUT P0, P1, P3, P4 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 V DD VDD VDD 0.2VDD 0.3VDD 0.15VDD Limits Min. 2.5 2.0 4.0 2.5 2.0 2.5 4.0 2.5 1.8 2.0 0.8V DD 0.8VDD 0.85VDD 0.85VDD –20 –10 –10 –30 Typ. f(XIN) ≤ 4.2 MHz f(XIN) ≤ 3.0 MHz f(XIN) ≤ 4.2 MHz f(XIN) ≤ 2.0 MHz f(XIN) ≤ 1.5 MHz f(XIN) ≤ 4.2 MHz f(XIN) ≤ 4.2 MHz f(XIN) ≤ 2.0 MHz VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V VDD = 5.0 V VDD = 3.0 V

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V VDD = 2.0 V to 5.5 V VDD = 4.0 V to 5.5 V VDD = 2.5 V to 5.5 V RECOMMENDED OPERATING CONDITIONS 2 (Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol f(XIN) f(XIN) tw(SCK ) tw(CNTR) Parameter Oscillation frequency (with a ceramic resonator) Oscillation frequency (with external clock input) Serial I/O external clock period (“H” and “L” pulse width) Timer external input period (“H” and “L” pulse width) Conditions Unit MHz MHz µs ns µs ns µs µs ns µs ns µs Max. 4.2 3.0 4.2 4.2 2.0 1.5 4.2 2.0 3.0 3.0 3.0 1.0 0.8 3.0 1.0 Limits Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Mask ROM version Middle-speed mode One Time PROM version Middle-speed mode Mask ROM version High-speed mode One Time PROM version High-speed mode Min. Typ. 1.5 3.0 4.0 1.5 3.0 750 1.5 2.0 750 1.5 1.5 3.0 4.0 1.5 3.0 750 1.5 2.0 750 1.5

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change.

ELECTRICAL CHARACTERISTICS

(Mask ROM version:Ta = –20 °C to 85 °C, VDD = 2.0 V to 5.5 V, unless otherwise noted) (One Time PROM version:Ta = –20 °C to 85 °C, VDD = 2.5 V to 5.5 V, unless otherwise noted) Symbol VOH VOL VOL VOL VOL IIH IIH IIL IIL IDD R PU VT+ – VT– VT+ – VT– Parameter “H” level output voltage P5 “L” level output voltage P0, P1, P4, P5 “L” level output voltage P3, RESET “L” level output voltage D6, D7 “L” level output voltage D0–D 5 “H” level input current P0, P1, P2, P3, P4, P5, RESET , VDCE “H” level input current D0–D 7 “L” level input current P0, P1, P2, P3, P4, P5, RESET , VDCE “L” level input current D0–D 7 Supply current Pull-up resistor value Hysteresis INT0, INT1, CNTR0, CNTR1, SIN, SCK Hysteresis RESET at active mode at RAM back-up mode Unit V V V V V V µA µA µA µA mA µA kΩ V V Test conditions VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VI = VDD , port P4 selected, port P5: input state V I = 12 V VI = 0 V No pull-up of ports P0 and P1, port P4 selected, port P5: input state V I = 0 V VDD = 5 V Middle-speed mode VDD = 3 V Middle-speed mode V DD = 5 V High-speed mode V DD = 3 V High-speed mode Ta = 25 °C VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V VDD = 5 V VDD = 3 V Limits Max. 0.9 0.9 0.9 0.9 0.9 5.5 1.5 2.7 0.6 9.0 1.8 2.7 0.9 125 250 IOH = –10 mA IOH = –5 mA IOL = 12 mA IOL = 6 mA IOL = 5 mA IOL = 2 mA IOL = 30 mA IOL = 10 mA IOL = 15 mA IOL = 5 mA IOL = 15 mA IOL = 3 mA Min. Typ. 1.8 0.5 0.9 0.2 3.0 0.6 0.9 0.3 0.1 100 0.3 0.3 1.5 0.6 f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 4.0 MHz f(XIN) = 400 kHz f(XIN) = 2.0 MHz f(XIN) = 400 kHz VI = 0 V

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. A-D CONVERTER RECOMMENDED OPERATING CONDITIONS (Comparator mode included, Ta = –20 °C to 85 °C, unless otherwise noted) Symbol VDD VIA f(XIN) Parameter Supply voltage Analog input voltage Oscillation frequency A-D CONVERTER CHARACTERISTICS (Ta = –20 °C to 85 °C, unless otherwise noted) Conditions Unit V V MHz MHz Middle-speed mode, VDD ≥ 2.7 V High-speed mode, VDD ≥ 2.7 V Min. 2.7 0.8 0.4 Typ. Max. 5.5 VDD Limits Symbol V0T VFST IADD TCONV Parameter Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage A–D operating current A-D conversion time Comparator resolution Comparator error (Note) Comparator comparison time Test conditions Unit bits LSB LSB mV mV mA µs bits mV µs Ta = 25 °C, VDD = 2.7 V to 5.5 V Ta = –25 °C to 85 ° C, VDD = 3.0 V to 5.5 V Ta = 25 °C, VDD = 2.7 V to 5.5 V Ta = –25 °C to 85 ° C, VDD = 3.0 V to 5.5 V VDD = 5.12 V VDD = 3.072 V VDD = 5.12 V VDD = 3.072 V VDD = 5.0 V VDD = 3.0 V f(XIN) = 4.0 MHz, Middle-speed mode f(XIN) = 4.0 MHz, High-speed mode Comparator mode VDD = 5.12 V VDD = 3.072 V f(XIN) = 4.0 MHz, Middle-speed mode f(XIN) = 4.0 MHz, High-speed mode Min. 5105 3060 Typ. 5115 3069 0.7 0.2 Max. ±0.9 5125 3075 2.0 0.4 93.0 46.5 ±20 ±15 Limits f(XIN) = 0.4 MHz to 4.0 MHz f(XIN) = 0.4 MHz to 2.0 MHz Note: As for the error from the ideal value in the comparator mode, when the contents of the comparator register is n, the logic value of the comparison volt- age Vref which is generated by the built-in DA converter can be obtained by the following formula. Logic value of comparison voltage Vref Vref = 5 n n = Value of register AD (n = 0 to 255) VDD 256 VOLTAGE DROP DETECTION CIRCUIT CHARACTERISTICS (Ta = –20 °C to 85 °C, unless otherwise noted) Test conditions Ta = 25 °C VDD = 5.0 V Parameter Detection voltage Operation current of voltage drop detection circuit Symbol VRST IRST Limits Unit V µA Min. 2.7 3.3 Typ. 3.5 Max. 4.1 3.7 100

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. BASIC TIMING DIAGRAM VOLTAGE COMPARATOR RECOMMENDED OPERATING CONDITION (Ta = –20 °C to 85 °C, unless otherwise noted) Conditions VDD = 3.0 V to 5.5 V VDD = 3.0 V to 5.5 V Parameter Supply voltage Voltage comparator input voltage Voltage comparator response time Symbol V DD VINCMP tCMP Limits Unit V V µs Min. 3.0 0.3VDD Typ. Max. 5.5 0.7VDD VOLTAGE COMPARATOR CHARACTERISTICS (Ta = –20 °C to 85 °C, VDD = 3.0 V to 5.5 V, unless otherwise noted) Test conditions CMP0- > CMP0+, CMP0- < CMP0+ CMP1- > CMP1+, CMP1- < CMP1+ V DD = 5.0 V Parameter Comparison decision voltage error Voltage comparator operation current Symbol ICMP Limits Unit mV µA Min. Typ. Max. 100 XIN System clock = f(XIN) Mi Mi+1 D 0–D 7 P00–P03 P10–P13 P00–P03 P10–P13 P20–P22 D 0–D 7 P30–P33 P40–P43 P50–P53 P30–P33 P40–P43 P50–P53 INT0,INT1 Machine cycle Pin nameParameter Clock Port D output Port D input Ports P0, P1, P3, P4, P5 output Ports P0, P1, P2, P3, P4, P5 input Interrupt input XIN System clock = f(XIN)/2

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Table 25 Product of built-in PROM version Product M34513E4SP/FP M34513E8FP M34514E8FP ROM type One Time PROM version [shipped in blank] PROM size (5 10 bits) 4096 words 8192 words 8192 words RAM size (5 4 bits) 256 words 384 words 384 words Package SP: 32P4B FP: 32P6B-A 32P6B-A 42P2R-A Fig. 49 Pin configuration of built-in PROM version of 4513 Group BUILT-IN PROM VERSION In addition to the mask ROM versions, the 4513/4514 Group has programmable ROM version software compatible with mask ROM. The built-in PROM of One Time PROM version can be written to and not be erased. The built-in PROM versions have functions similar to those of the mask ROM versions, but they have PROM mode that enables writ- ing to built-in PROM. Table 25 shows the product of built-in PROM version. Figure 49 and 50 show the pin configurations of built-in PROM versions. Fig. 50 Pin configuration of built-in PROM version of 4514 Group P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1- AIN1/CMP0+ AIN0/CMP0- P31/INT1 P30/INT0 VDCE VDD M34514E8FP Outline 42P2R-A P13 D 1 D 2 D 3 D 4 D 5 D 6/CNTR0 D 7/CNTR1 P21/SOUT P20/SCK P22/SIN CNV SS XOUT XIN VSS RESET P43/AIN7 P32 P33 P42/AIN6 P41/AIN5 P40/AIN432 D 0 P50 P51 P52 P53 M34513E4SP P13 P12 P11 P10 P03 P02 P01 P00 AIN3/CMP1+ AIN2/CMP1- AIN1/CMP0+ AIN0/CMP0- P31/INT1 P30/INT0 VDCE VDD D 0 D 1 D 2 D 3 D 4 D 5 D 6/CNTR0 D 7/CNTR1 P20/SCK P21/SOUT P22/SIN RESET CNV SS XOUT XIN VSS Outline 32P4B 9 10 11 12 13 14 15 16 32 31 30 29 28 27 26 25 M34513ExFP D 2 D 1 D 0 P13 P12 P11 P10 P03 RESETCNV SS XOUT XIN VSS VDD VDCE P30/INT0 Outline 32P6B-A D 3 D 4 D 5 D 6/CNTR 0 D 7/CNTR 1 P20/SCK P21/SOUT P22/SIN P02 P01 P00 AIN3/CMP1+ AIN2/CMP1- AIN1/CMP0+ AIN0/CMP0- P31/INT1

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 52 Flow of writing and test of the product shipped in blank Fig. 51 PROM memory map (1) PROM mode The built-in PROM version has a PROM mode in addition to a nor- mal operation mode. The PROM mode is used to write to and read from the built-in PROM. In the PROM mode, the programming adapter can be used with a general-purpose PROM programmer to write to or read from the built-in PROM as if it were M5M27C256K. Programming adapters are listed in Table 26.Contact addresses at the end of this sheet for the appropriate PROM programmer.

Writing and reading of built-in PROM Programming voltage is 12.5 V. Write the program in the PROM of the built-in PROM version as shown in Figure 51. (2) Notes on handling À A high-voltage is used for writing. Take care that overvoltage is not applied. Take care especially at turning on the power. \` For the One Time PROM version shipped in blank, Mitsubishi Electric corp. does not perform PROM writing test and screening in the assembly process and following processes. In order to im- prove reliability after writing, performing writing and test according to the flow shown in Figure 52 before using is recom- mended (Products shipped in blank: PROM contents is not written in factory when shipped). Table 26 Programming adapters Microcomputer M34513E4SP M34513E4FP, M34513E8FP M34514E8FP Programming adapter PCA7442SP PCA7442FP PCA7441 Address 000016 1FFF 16 400016 5FFF 16 7FFF 16 /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 1 11 D 4 D 3 D 2 D 1 D 0 High-order 5 bits /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines/LiteDiagLines 1 11 D 4 D 3 D 2 D 1 D 0 Low-order 5 bits Set “FF16” to the shaded area. Writing with PROM programmer Screening (Leave at 150 °C for 40 hours) (Note) Verify test with PROM programmer Function test in target device Since the screening temperature is higher than storage temperature, never expose the microcomputer to 150 °C exceeding 100 hours. Note:

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name: M34513M2-XXXSP M34513M2-XXXFP Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: Customer 27C256 27C512 Low-order 5-bit data /,/,/, /,/,/,/,/, /, /,/,/,/,/,/,/,/, /,/, High-order 5-bit data /,/,/, /,/,/, 000016 07FF 16 400016 47FF 16 7FFF 2.00K 2.00K Low-order 5-bit data /,/,/, High-order 5-bit data /,/,/, /,/,/, 0000 16 07FF 16 4000 16 47FF 16 FFFF 2.00K 2.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data. 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M2-XXXSP, 32P6B-A for M34513M2-XXXFP) and attach to the Mask ROM Order Confirmation Form. 3. Comments T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH52-45B <81A0>

4500 SERIES MASK ROM ORDER CONFIRMATION FORM

SINGLE-CHIP MICROCOMPUTER M34513M2-XXXSP/FP MITSUBISHI ELECTRIC Please fill in all items marked ] .

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Microcomputer name: M34513M4-XXXSP M34513M4-XXXFP Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: Customer 27C256 27C512 Low-order 5-bit data /,/,/, High-order 5-bit data /,/,/, /,/,/, 000016 0FFF 16 400016 4FFF 16 7FFF 16 4.00K 4.00K Low-order 5-bit data /,/,/, High-order 5-bit data /,/,/, /,/,/, 0000 16 0FFF 16 4000 16 4FFF 16 FFFF 16 4.00K 4.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data. 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P4B for M34513M4-XXXSP, 32P6B-A for M34513M4-XXXFP) and attach to the Mask ROM Order Confirmation Form. 3. Comments T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH52-44B <81A0> SINGLE-CHIP MICROCOMPUTER M34513M4-XXXSP/FP MITSUBISHI ELECTRIC Please fill in all items marked .]

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: Customer 27C256 27C512 Low-order 5-bit data /,/,/, High-order 5-bit data /,/,/, /,/,/, 000016 17FF 16 400016 57FF 16 7FFF 16 6.00K 6.00K Low-order 5-bit data /,/,/, High-order 5-bit data /,/,/, /,/,/, 0000 16 17FF 16 4000 16 57FF 16 FFFF 16 6.00K 6.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data. 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. 3. Comments T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH53-01B <85A0> SINGLE-CHIP MICROCOMPUTER M34513M6-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked .]

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: Customer 27C256 27C512 Low-order 5-bit data High-order 5-bit data 000016 1FFF 16 400016 5FFF 16 7FFF 16 8.00K 8.00K Low-order 5-bit data High-order 5-bit data 0000 16 1FFF 16 4000 16 5FFF 16 FFFF 16 8.00K 8.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data. 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (32P6B-A for M34513M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. 3. Comments T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH52-99B <85A0> SINGLE-CHIP MICROCOMPUTER M34513M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked .]

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: Customer 27C256 27C512 Low-order 5-bit data /,/,/, High-order 5-bit data /,/,/, /,/,/, 000016 17FF 16 400016 57FF 16 7FFF 16 6.00K 6.00K Low-order 5-bit data /,/,/, High-order 5-bit data /,/,/, /,/,/, 0000 16 17FF 16 4000 16 57FF 16 FFFF 16 6.00K 6.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data. 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M6-XXXFP) and attach to the Mask ROM Order Confirmation Form. 3. Comments T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH52-41B <81A0> SINGLE-CHIP MICROCOMPUTER M34514M6-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked .]

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 1. Confirmation Specify the type of EPROMs submitted. Three sets of EPROMs are required for each pattern (check in the approximate box). If at least two of the three sets of EPROMs submitted contain the identical data, we will produce masks based on this data. We shall assume the responsibility for errors only if the mask ROM data on the products we produce differ from this data. Thus, the customer must be especially careful in verifying the data contained in the EPROMs submitted. Checksum code for entire EPROM area (hexadecimal notation) EPROM Type: Company name Date issued Date: Customer 27C256 27C512 Low-order 5-bit data High-order 5-bit data 000016 1FFF 16 400016 5FFF 16 7FFF 16 8.00K 8.00K Low-order 5-bit data High-order 5-bit data 0000 16 1FFF 16 4000 16 5FFF 16 FFFF 16 8.00K 8.00K Set “FF16” in the shaded area. Set “1112” in the area of low-order and high-order 5-bit data. 2. Mark Specification Mark specification must be submitted using the correct form for the type of package being ordered. Fill out the approximate Mark Specification Form (42P2R-A for M34514M8-XXXFP) and attach to the Mask ROM Order Confirmation Form. 3. Comments T E L ( ) Mask ROM number Date: Section head signature Supervisor signature Responsible officer Supervisor Issuance signature Receipt GZZ-SH52-40B <81A0> SINGLE-CHIP MICROCOMPUTER M34514M8-XXXFP MITSUBISHI ELECTRIC Please fill in all items marked .]

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 32P4B (32-PIN SHRINK DIP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi IC catalog name and the special mark (if needed). A. Standard Mitsubishi Mark Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the upper figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box on the right. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. 3 : The standard Mitsubishi font is used for all characters except for a logo. Special logo required Mitsubishi IC catalog name C. Special Mark Required B. Customer’s Parts Number + Mitsubishi catalog name Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 16 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,  ,. (periods), and , (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box on the right. Mitsubishi logo is not required Mitsubishi lot number (6-digit or 7-digit) 1 16 Mitsubishi lot number (6-digit or 7-digit) 1 16 1 16

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 32P6B (32-PIN LQFP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark B. Customer’s Parts Number + Mitsubishi catalog name Mitsubishi IC catalog name Mitsubishi IC catalog name Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 7 characters : Only 0 ~ 9, A ~ Z, +, –, /, (, ), &,  ,. (periods),, (commas) are usable. 1625 1724 Mitsubishi lot number (4-digit or 5-digit) 1625 1724

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. 42P2R-A (42-PIN SHRINK SOP) MARK SPECIFICATION FORM Mitsubishi IC catalog name Please choose one of the marking types below (A, B, C), and enter the Mitsubishi catalog name and the special mark (if needed). A. Standard Mitsubishi Mark C. Special Mark Required B. Customer’s Parts Number + Mitsubishi catalog name Mitsubishi IC catalog name Mitsubishi IC catalog name Note1 : If the Special Mark is to be Printed, indicate the desired layout of the mark in the left figure. The layout will be duplicated as close as possible. Mitsubishi lot number (6-digit or 7-digit) and Mask ROM number (3-digit) are always marked. 2 : If the customer’s trade mark logo must be used in the Special Mark, check the box below. Please submit a clean original of the logo. For the new special character fonts a clean font original (ideally logo drawing) must be submitted. Special logo required Customer’s Parts Number Note : The fonts and size of characters are standard Mitsubishi type. Mitsubishi IC catalog name Note1 : The mark field should be written right aligned. 2 : The fonts and size of characters are standard Mitsubishi type. 3 : Customer’s Parts Number can be up to 11 characters : Only 0 ~ . (periods),, (commas) are usable. 4 : If the Mitsubishi logo is not required, check the box below. Mitsubishi logo is not required 1 21 2242 Mitsubishi lot number (6-digit or 7-digit) 1 21 2242 Mitsubishi lot number (6-digit or 7-digit) 1 21 2242

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. PACKAGE OUTLINE SDIP32-P-400-1.78 Weight(g) – 2.2 JEDEC CodeEIAJ Package Code Lead Material Alloy 42/Cu Alloy 32P4B Plastic 32pin 400mil SDIP Symbol Min Nom Max A b c E D L Dimension in Millimeters A1 0.51 – – –3 . 8– 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 27.8 28.0 28.2 8.75 8.9 9.05 – 1.778 – – 10.16 – 3.0 – – 0° –1 5 ° – – 5.08 e 32 17 161 E ce1 A2A1 b2bb1e LA SEATING PLANE D LQFP32-P-77-0.80 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 32P6B-A Plastic 32pin 75 7mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.5 ––I2 1.0 ––M D 7.4 ––M E 7.4 10°0° 0.1 1.0 0.70.50.3 9.29.08.8 9.29.08.8 0.8 7.17.06.9 7.17.06.9 0.1750.1250.105 0.450.350.3 1.4 1.7 e e e E c H E 32 25 H D D M D M E A F b A1 A2 L y Recommended Mount Pad Detail F

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINARY Notice: This is not a final specification. Some parametric limits are subject to change. SSOP42-P-450-0.80 Weight(g) JEDEC Code 0.63 Alloy 42/Cu Alloy 42P2R-A Plastic 42pin 450mil SSOP Symbol Min Nom Max A b c D E L y Dimension in Millimeters H E .350 .050 .130 .317 .28 .6311 .30 .271 .02 .40 .150 .517 .48 .80 .9311 .50 .7651 .4311 .42 .50 .20 .717 .68 .2312 .70 .150 b 2 –. 5 0– 0° –1 0 ° e 42 22 211 H E E D be y F A A2 A1 L c e b2 Recommended Mount Pad Detail F

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Rev. Rev. No. date

1.0 First Edition 980807

REVISION DESCRIPTION LIST 4513/4514 GROUP DATA SHEET (1/1) Revision Description

Product Information

4514 specifications and overview.

Summary

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Rev.1.0

Description

SINGLE-CHIP 4-BIT CMOS MICROCOMPUTER Rev.1.0

Source title 4514 Datasheet(PDF) - Mitsubishi Electric Semiconductor

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