440EP

440EP AMCC | Alldatasheet

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Datasheet sections

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Features

• P o w e r P C® 440 processor core operating up to 667MHz with 32KB I-cache and D-cache with parity checking.
• Selectable processor:bus cl ock ratios of N:1, N:2.
• Floating Point Unit wit h single- and double- precision and single-cycle throughput.
• Dual bridged Processor Local Buses (PLBs) with 64- and 128-bit widths.
• Double Data Rate (DDR) Synchronous DRAM (SDRAM) interface operating up to 133MHz with ECC.
• DMA support for external peripherals, internal UART and memory.
• PCI V2.2 interface (3.3V on ly). Thirty-two bits at up to 66MHz.
• Programmable interrupt controller supports interrupts from a variety of sources.
• Programmable General Purpose Timers (GPT).
• Two Ethernet 10/100Mbps half- or full-duplex interfaces. Operational modes supported are MII, RMII, and SMII with packet reject.
• Up to four serial ports (16750 compatible UART).
• Two USB ports. One USB 1.1 Host interface with on-chip PHY. One USB 2.0 Device interface, with dedicated DMA, configured as a 1.1 on-chip PHY or a 2.0 UTMI.
• External peripheral bus (16-bit data) for up to six devices with external mastering.
• Two IIC interfaces (one with boot parameter read capability).
• NAND Flash interface.
• SPI interface.
• General Purpose I/O (GPIO) interface.
• JTAG interface for board level testing.
• Boot from PCI memory, NOR Flash on the external peripheral bus, or NAND Flash on the NAND Flash interface.
• Available in RoHS compliant lead-free package.

Description

Designed specifically to address high-end embedded applications, the PowerPC 440EP (PPC440EP) provides a high-performance, low- power solution that interfaces to a wide range of peripherals and incorporates on-chip power management features. This chip contains a high-performance RISC processor, a floating point unit, DDR SDRAM controller, PCI bus interface, control for external ROM and peripherals, DMA with scatter-gather support, Ethernet ports, serial ports, IIC interfaces, SPI interface, USB ports, NAND Flash interface, and general purpose I/O. Technology: CMOS Cu-11, 0.13μm. Package: 35mm, 456-ball standard plastic ball grid array (E-PBGA), with and without lead (RoHS compliant). Typical power (measured): Less than 3W at 533MHz, 2.5W at 400MHz. Supply voltages required: 3.3V, 2.5V, 1.5V.

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For information on the availability of the following parts, contact your local AMCC sales office. number for identification purposes only. Figure 1. Order Part Number Key B = standard (E-PBGA) and contains lead.

1. fff = Processor frequency
2. C = Case temperature range:

667MHz, and is shipped in tape-and-reel packaging.

Figure 2. PPC440EP Functional Block Diagram The PPC440EP is a system on a chip (SOC) using IBM CoreConnect Bus™ Architecture.

1 MII

2 RMII

2 SMII

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running on the PPC440EP processor through the use of mtdcr and mfdcr instructions. Table 1. System Memory Address Map (Sheet 1 of 2)

1. DDR SDRAM can be located anywhere in the Local Memory area of the memory map.
2. EBC and PCI are relocatable, but this map reflects the suggested configuration.

Table 1. System Memory Address Map (Sheet 2 of 2)

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Table 2. DCR Address Map (4KB of Device Configuration Registers)

1. DCR address space is addressable with up to 10 bits (1024 or 1K unique addresses). Each unique address represents a single 32-bit

(word) register. One kiloword (1024W) equals 4KB (4096 B).

440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 PowerPC 440 Processor Core The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, iSCSI, routers, switches, printers, set-top boxes, etc. It is the first processor core to implement the new Book E PowerPC embedded architecture and the first to use the 128-bit version of IBM’s on-chip CoreConnect Bus Architecture. Features include:

• Up to 667MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache – UTLB Word Wide parity on data and tag address parity with exception force
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• 3 execution pipelines
• Dynamic branch prediction
• Memory management unit – 64-entry, full associative, unified TLB with optional parity – Separate instruction and data micro-TLBs – Storage attributes for write-through, cache- inhibited, guarded, and big or little endian
• Debug facilities – Multiple instruction and data range breakpoints – Data value compare – Single step, branch, and trap events – Non-invasive real-time trace interface
• 24 DSP instructions – Single cycle multiply and multiply-accumulate – 32 x 32 integer multiply – 16 x 16 -> 32-bit MAC Floating Point Unit (FPU) Features include:
• Five stages with 2 MFlops/MHz
• Hardware support for IEEE 754
• Single- and double-precision
• Single-cycle throughput on most instructions
• Thirty-two 64-bit floating point registers

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440EP – PPC440EP Embedded ProcessorRevision 1.26 – April 25, 2007 Data Sheet Internal Buses The PowerPC 440EP features five standard on-chip buses: two Processor Local Buses (PLBs), two On-Chip Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth cores such as the PowerPC 440 processor core, the DDR SDRAM memory controller, and the PCI bridge connect to the PLBs. The primary OPB hosts lower data rate peripherals. The secondary OPB is dedicated to USB 2.0 and DMA. The daisy-chained DCR provides a lower bandwidth path for passing status and control information between the processor core and the other on-chip cores. Features include:

• PLB 128 (PLB4) – 128-bit implementation of the PLB architecture – Separate and simultaneous read and write data paths – 36-bit address – Simultaneous control, address, and data phases – Four levels of pipelining – Byte-enable capa bility supporting unaligned transfers – 32- and 64-byte burst transfers – 133MHz, maximum 4.25GB/s (simultaneous read and write) – Processor:bus clock ratios of N:1 and N:2
• PLB 64 (PLB3) – 64-bit implementation of the PLB architecture – 32-bit address – 133MHz (1:1 ratio with PLB 128), maximum 1.1GB/s (no simultaneous read and write)
• O P B ( 2 ) – 32-bit data path – 32-bit address – 66.66MHz
• DCR – 32-bit data path – 10-bit address

440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 PCI Interface The PCI interface allows connection of PCI devices to the PowerPC processor and local memory. This interface is designed to Version 2.2 of the PCI Specification and supports 32- bit PCI devices. Reference Specifications:

• PowerPC CoreConnect Bus (PLB) Specification Version 3.1
• PCI Specification Version 2.2
• PCI Bus Power Management Interface Specification Version 1.1 Features include:
• P C I 2 . 2 – Frequency to 66MHz – 32-bit bus
• PCI Host Bus Bridge or an Adapter Device's PCI interface
• Internal PCI arbitration function, supporting up to six ex ternal devices, that can be disabled for use with an external arbiter
• Support for Message Signaled Interrupts
• Simple message passing capability
• Asynchronous to the PLB
• PCI Power Management 1.1
• PCI register set addressable both from on-chip processor and PCI device sides
• Ability to boot from PCI bus memory
• Error tracking/status
• Supports initiation of transfer to the following address spaces: – Single beat I/O reads and writes – Single beat and burst memory reads and writes – Single beat configuration reads and writes (type 0 and type 1) – Single beat special cycles DDR SDRAM Memory Controller The Double Data Rate (DDR) SDRAM memory controller supports industry standard discrete devices. Up to four 256MB logical banks are supported in limited configurations. Global memory timings, address and bank sizes, and memory addressing modes are programmable. Features include:
• Registered and non-registered industry standard discrete devices
• 32-bit memory interface with optional 8-bit ECC (SEC/DED)
• Sustainable 1.1GB/s peak bandwidth at 133MHz
• SSTL_2 logic
• 1 to 4 chip selects
• CAS latencies of 2, 2.5 and 3 supported
• DDR200/266 support
• Page mode accesses (up to eight open pages) with configurable paging policy
• Programmable address mapping and timing
• Hardware and software initiated self-refresh
• Power management (self-refresh, suspend, sleep)

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440EP – PPC440EP Embedded ProcessorRevision 1.26 – April 25, 2007 Data Sheet External Peripheral Bus Controller (EBC) Features include:

• Up to six ROM, EPROM, SRAM, Flash memory , and slave peripheral I/O banks supported
• Up to 66.66MHz operation
• Burst and non-burst devices
• 16-bit byte-addressable data bus
• 30-bit address
• Peripheral Device pacing with external “Ready”
• Latch data on Ready, synchronous or asynchronous
• Programmable access timing per device – 256 Wait States for non-burst – 32 Burst Wait States for first access and up to 8 Wait States for subsequent accesses – Programmable CSon, CSoff relative to address – Programmable OEon, WEon, WEoff (1 to 4 clock cycles) relative to CS
• Programmable address mapping
• External DMA Slave Support
• External master interface – Write posting from external master – Read prefetching on PLB for external master reads – Bursting capable from external master – Allows external master access to all non-EBC PLB slaves – External master can control EBC sl aves for own access and control Ethernet Controller Interface Ethernet support provided by the PPC440EP interfaces to the physical layer but the PHY is not included on the chip:
• One to two 10/100 interfaces running in full- and half-duplex modes – One full Media Independent Interface (MII) with 4-bit parallel data transfer – Two Reduced Media Independent Interfaces (RMII) with 2-bit parallel data transfer – Two Serial Media Independent Interfaces (SMII) – Packet reject support DMA to PLB 64 Controller This DMA controller provides a DMA interface between the OPB and the 64-bit PLB. Features include:
• Supports the following transfers: – Memory-to-memory transfers – Buffered peripheral to memory transfers – Buffered memory to peripheral transfers
• Four channels
• Scatter/Gather capability for pr ogramming multiple DMA operations
• 32-byte buffer
• 8-, 16-, 32-bit peripheral support (OPB and external)
• 32-bit addressing
• Address increment or decrement
• Supports internal and external peripherals
• Support for memory mapped peripherals
• Support for peripherals running on slower frequency buses

440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 DMA to PLB 128 Controller This DMA controller provides a DMA interface dedicated to the USB 2.0 device ports and the 128-bit PLB. Features include:

• 4 independent channels supporting internal USB 2.0 Device endpoints 1 and 2
• Support for memory-to-memory, peripheral-to-memory, and memory-to-peripheral transfers
• Scatter/gather capability
• 128-byte buffer with programmable thresholds Serial Ports (UART) Features include:
• Up to four ports in th e following combinations: – One 8-pin – Two 4-pin – One 4-pin and two 2-pin – Four 2-pin
• Selectable internal or external serial clock to allow wide range of baud rates
• Register compatibility wit h NS16750 register set
• Complete status reporting capability
• Fully programmable serial-i nterface characteristics
• Supports DMA using internal DMA function on PLB 64 IIC Bus Interface Features include:
• Two IIC interfaces provided
• Support for Philips® Semiconductors I2C Specification, dated 1995
• Operation at 100kHz or 400kHz
• 8 - b i t d a t a
• 10- or 7-bit address
• Slave transmitter and receiver
• Master transmitter and receiver
• Multiple bus masters
• Supports fixed V DD IIC interface
• Two independent 4 x 1 byte data buffers
• Twelve memory-mapped, fully prog rammable configuration registers
• One programmable interrupt request signal
• Provides full management of all IIC bus protocols
• Programmable error recovery
• Includes an integrated boot-strap controller th at is multiplexed with the second IIC interface

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440EP – PPC440EP Embedded ProcessorRevision 1.26 – April 25, 2007 Data Sheet Serial Peripheral Interface (SPI/SCP) The Serial Peripheral Interface (also known as the Serial Communications Port) is a full-duplex, synchronous, character-oriented (byte) port that allows the exchange of data with other serial devices. The SCP is a master on the serial port supporting a 3-wire interface (receive, transmit, and clock), and is a slave on the OPB. Features include:

• Three-wire serial port interface
• Full-duplex synchronous operation
• SCP bus master
• OPB bus slave
• Programmable clock rate divider
• Clock inversion
• Reverse data
• Local data loop back for test Universal Serial Bus (USB) The USB interfaces provide both device and host support for version 1.1 and device support for version 2.0. Support for the USB 2.0 Transceiver Macrocell Interface (UTMI) specification is included. Features include:
• USB 1.1 Host port with internal PHY
• USB 2.0 Device UTMI or USB 1.1 Device PHY
• Device support provides 6 end points (3 in, 3 out)
• 1024B FIFO (double buffering of 512B packets)
• FIFOs are not shared between in and out endpoints
• Endpoints do not support high-bandwidth isochronous transfers
• Two USB 2.0 device end points have DMA dedicated channels (DMA to PLB 128) NAND Flash Controller The NAND Flash controller provides a simple interface between the EBC and up to four separate external NAND Flash devices. It provides both direct command, address, and data access to the external device as well as a memory-mapped linear region that generates data accesses. NAND Flash device data appears on the peripheral data bus. Features include:
• 1 to 4 banks supported on EBC
• Direct Interfacing to: – Discrete NAND Flash de vices (up to 4 devices) – SmartMedia Card socket (22-pins)
• Device sizes 4MB-256MB supported
• (512 + 16)-B or (2K + 64)-B device page sizes supported
• Boot-from-NAND: Execute a linear sequence of boot code out of single page of first block (512B)
• Support DMA to allow direct, no-processor-int ervention block copy from NAND Flash to SDRAM
• ECC provides single-bit error correction and double-bit error detection in each 256B of stored data
• Chip selects shared with EBC

440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 General Purpose Timers (GPT) Provides a separate time base counter and additional system timers in addition to those defined in the processor core. Features include:

• 32-bit Time Base Counter dr iven by the OPB bus clock
• Seven 32-bit compare timers General Purpose IO (GPIO) Controller
• Controller functions and GPIO registers are programm ed and accessed via memory-mapped OPB bus master accesses.
• 64 GPIOs are multiplexed with other functions. DCRs control whether a particular pin that has GPIO capabilities acts as a GPIO or is used for another purpose.
• Each GPIO output is separately programmable to emulate an open drain driver (that is, drives to zero, tri-stated if output bit is 1). Universal Interrupt Controller (UIC) Two Universal Interrupt Controllers (UIC) are employed. They provide control, status, and communications necessary between the external and internal sources of interrupts and the on-chip PowerPC processor. Note: Processor specific interrupts (for example, page faults) do not use UIC resources. Features include:
• 10 external interrupts
• Edge triggered or level-sensitive
• Positive or negative active
• Non-critical or critical interrupt to the on-chip processor core
• Programmable interrupt priority ordering
• Programmable critical interrupt ve ctor for faster vector processing JTAG Features include:
• IEEE 1149.1 Test Access Port
• IBM RISCWatch Debugger support
• JTAG Boundary Scan Description Language (BSDL)

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Figure 3. 35mm, 456-Ball E-PBGA

1.27 TYP

Notes: 1. All dimensions are in mm.

2.65 MAX

1. Package is available in both lead-free and leaded versions.

30 TYPPPC440EP

Table 3. Signals Listed Alphabetically (Sheet 1 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 2 of 24)

Table 3. Signals Listed Alphabetically (Sheet 3 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 4 of 24)

Table 3. Signals Listed Alphabetically (Sheet 5 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 6 of 24)

Table 3. Signals Listed Alphabetically (Sheet 7 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 8 of 24)

Table 3. Signals Listed Alphabetically (Sheet 9 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 10 of 24)

Table 3. Signals Listed Alphabetically (Sheet 11 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 12 of 24)

Table 3. Signals Listed Alphabetically (Sheet 13 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 14 of 24)

Table 3. Signals Listed Alphabetically (Sheet 15 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 16 of 24)

Table 3. Signals Listed Alphabetically (Sheet 17 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 18 of 24)

Table 3. Signals Listed Alphabetically (Sheet 19 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 20 of 24)

Table 3. Signals Listed Alphabetically (Sheet 21 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 22 of 24)

Table 3. Signals Listed Alphabetically (Sheet 23 of 24)

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Table 3. Signals Listed Alphabetically (Sheet 24 of 24)

up the primary signal name in Table 3, Signals Listed Alphabetically. Table 4. Signals Listed by Ball Assignment (Sheet 1 of 7)

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Table 4. Signals Listed by Ball Assignment (Sheet 2 of 7)

Table 4. Signals Listed by Ball Assignment (Sheet 3 of 7)

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Table 4. Signals Listed by Ball Assignment (Sheet 4 of 7)

Table 4. Signals Listed by Ball Assignment (Sheet 5 of 7)

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Table 4. Signals Listed by Ball Assignment (Sheet 6 of 7)

Table 4. Signals Listed by Ball Assignment (Sheet 7 of 7)

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following tables describe the package level pinout. Alphabetically” on page 17 for the pin (ball) number to which each signal is assigned. actual circuit type is the same as the primary signal. Table 5. Pin Summary

440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 Multimode Signals In some cases (for example, Ethernet) the function of a pin may vary with different modes of operation. When a pin has multiple signal names assigned to distinguish different modes of operation, all of the names are shown. Strapping Pins One group of pins is used as strapped inputs during system reset. These pins function as strapped inputs only during reset and are used for other functions during normal operation (see “Strapping” on page 80). Note that these are not multiplexed pins since the function of the pins is not programmable.

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Table 6. Signal Functional Description (Sheet 1 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

Indicates that the specified agent is granted access to the bus. the internal arbiter is disabled, output is Req. PCIGnt1:5 Indicates that the specified agent is granted access to the bus. . When internal arbiter is disabled, input is Gnt.

Table 6. Signal Functional Description (Sheet 2 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

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EMCCD, EMC1RxErr MII: Collision detection. EMCCrS, EMC0CrsDV MII: Carrier sense. EMCDV, EMC1CrsDV MII: Data valid. SMII A and B: Transmit data. RMII A: Transmit data enabled. Table 6. Signal Functional Description (Sheet 3 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

master mode, otherwise used by external master. Note: PerData00 is the most significant bit (msb) on this bus. read from memory, low indicates a write to memory. indicate the direction of transfer. Table 6. Signal Functional Description (Sheet 4 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

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internally generated clock rates are not satisfactory. Table 6. Signal Functional Description (Sheet 5 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

with a frequency between 32kHz and 48MHz. Table 6. Signal Functional Description (Sheet 6 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

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Indicates status of device during program erase or page read. This signal is wire-or connected from all NAND Flash devices. captured synchronously with SysClk. Table 6. Signal Functional Description (Sheet 7 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

an open-drain output (two states; 0 or open circuit). Table 6. Signal Functional Description (Sheet 8 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

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Table 6. Signal Functional Description (Sheet 9 of 9)

1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required

Table 7. Absolute Maximum Ratings operating at these maximum ratings.

1. If OV DD ≤ 0.4V, it is required that VDD ≤ 0.4V. Supply excursions not meeting this criteria must be limited to less than 25ms duration

during each power up or power down event.

1. The analog voltages used for the on-chip P LLs can be derived from the logic voltage, but must be filtered before entering the
2. This value is not a spec ification of the operational temperature range, it is a stress rating only.

Table 8. Recommended DC Operating Conditions (Sheet 1 of 2) conditions can affect device reliability.

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667MHz parts in the TE-PBGA package.

1. PCI drivers meet PCI specifications.
2. The analog voltages used for the on-chip P LLs can be derived from the logic voltage, but must be filtered before entering the

PPC440EP. See “Absolute Maximum Ratings” on page 59. Table 8. Recommended DC Operating Conditions (Sheet 2 of 2) conditions can affect device reliability.

(OVDD and VDD are below +0.4V) before a new power-up cycle is started. Table 9. Input Capacitance Table 10. Typical DC Power Supply Requirements

1. Typical Power is based on nominal voltage of V

application that exercises each core with representative traffic. Table 11. VDD Supply Power Dissipation that exercises each core with representative traffic.

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Table 12. DC Power Supply Current Loads

1. See “Absolute Maximum Ratings” on page 59 for filter recommendations.
2. The maximum current values listed above are not guaranteed to be the highest obtainable. These values are dependent on many factors

are primarily dependent on the capacitive loading, frequency, and utilization of the external buses.

1. Typical current is estimated at 667MHz with VDD = +1.5V, OVDD = +3.3V, SVDD = +2.5V, and TC = +85°C, while running Linux and a test

application that exercises each core with representative traffic.

1. Maximum current is estimated at 667MHz with VDD = +1.6V, OVDD = +3.6V, SVDD = +2.7V, TC = +85°C, and a best-case process (which

drives worst-case power), while running Linux and a test application that exercises each core with representative traffic. Table 13. Package Thermal Specifications

1. Case temperature, T C, is measured at top center of case surface with device soldered to circuit board.
2. T A = TC - P×θCA, where TA is ambient temperature and P is power consumption.
3. T CMax = TJMax - P×θJC, where TJMax is maximum junction temperature (+125°C) and P is power consumption.
4. The preceding equations assume that the chip is mount ed on a board with at least one signal and two power planes.
5. Values for an attached heat sink were achieved with a 35mm x 35mm x 15mm unit (see Thermal Management below), attached with a

0.1mm thickness of adhesive having a thermal conductivity of 1.3W/mK.

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shown in the figure to the right. Figure 4. Timing Waveform Table 14. Clocking Specifications

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440EP – PPC440EP Embedded ProcessorRevision 1.26 – April 25, 2007 Data Sheet Spread Spectrum Clocking Care must be taken when using a spread spectrum clock generator (SSCG) with the PPC440EP. This controller uses a PLL for clock generation inside the chip. The accuracy with which the PLL follows the SSCG is referred to as tracking skew. The PLL bandwidth and phase angle determine how much tracking skew there is between the SSCG and the PLL for a given frequency deviation and modulation frequency. When using an SSCG with the PPC440EP the following conditions must be met:

• The frequency deviation must not violate the minimum clock cycle time. Therefore, when operating the PPC440EP with one or more internal clocks at their maximum supported frequency, the SSCG can only lower the frequency.
• The maximum frequency de viation cannot exceed −3%, and the modulation frequency cannot exceed 40kHz. In some cases, on-board PPC440EP peripherals impose more stringent requirements.
• Use the Peripheral Bus Clock for logic that is synchron ous to the peripheral bus since this clock tracks the modulation.
• Use the DDR SDRAM MemClkOut sinc e it also tracks the modulation. Notes: 1. The serial port baud rates are synchronous to the modulated clock. The serial port has a tolerance of approximately 1.5% on baud rate before framing errors begin to occur. The 1.5% tolerance assumes that the connected device is running at precise baud rates. 2. Ethernet operation is unaffected. 3. IIC operation is unaffected. Important: It is up to the system designer to ensure that any SSCG used with the PPC440EP meets the above requirements and does not adversely affect other aspects of the system.

Table 15. Peripheral Interface Clock Timings

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Figure 5. Input Setup and Hold Waveform Figure 6. Output Delay and Float Timing Waveform mum OPB clock frequency is 66.66 MHz. Table 15. Peripheral Interface Clock Timings (Continued)

Table 16. I/O Specifications—All Speeds (Sheet 1 of 3)

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

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Table 16. I/O Specifications—All Speeds (Sheet 2 of 3)

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

Table 16. I/O Specifications—All Speeds (Sheet 3 of 3)

1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.

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Table 17. I/O Specifications—333MHz to 533MHz

1. PerClk rising edge at package pin with a 10pF load trails the internal PLB clock by approximately 1.3ns.

same frequency as the PLB clock signal and is in phase with the PLB clock signal. SDRAM controller chapter in the PowerPC 440EP User’s Manual). MemClkOut0(90). The rising edge of MemClkOut0(90) aligns with the first rising edge of the DQS signal. The following DDR data is generated by means of simulation and includes logic, driver, package RLC, and lengths. conditions and maximum values are measured under worst case conditions. The signals are terminated as indicated in the figure below for the DDR timing data in the following sections. Figure 7. DDR SDRAM Simulation Signal Termination Model Note: This diagram illustrates the model of the DDR SDRAM interface used when generating simulation timing data. factors, including the type of memory used and the board layout.

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Table 18. DDR SDRAM Output Driver Specifications

The following diagram illustrates the relationship among the signals involved with a DDR write operation. Figure 8. DDR SDRAM Write Cycle Timing

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Note: The timing data in the following tables is based on simulation runs using Einstimer. Table 19. I/O Timing—DDR SDRAM T DS

1. All of the DQS signals are referenced to MemClkOut0(0).

DS values in the table include 3/4 of a cycle at 133MHz (7.5ns x 0.75 = 5.625 ns).

1. To obtain adjusted values for lower clock frequencies, subtract 5.625 ns from the values in the table and add 3/4 of the cycle

time for the lower clock frequency (TDS - 5.625 + 0.75TCYC). Table 20. I/O Timing—DDR SDRAM T SK, TSA, and THA

1. Clock speed is 133MHz. TSK is referenced to MemClkOut0(0). TSA and THA are referenced to MemClkOut0(90).
2. To obtain adjusted TSA values for lower clock frequencies, use 3/4 of the cycle time for the lower clock frequency and subtract

TSK maximum (0.75TCYC - TSKmax).

1. To obtain adjusted THA values for lower clock frequencies, use 1/4 of the cycle time for the lower clock frequency and add

TSK minimum (0.25TCYC + TSKmin). Table 21. I/O Timing—DDR SDRAM T SD and THD

1. TSD and THD are measured under worst case conditions.
2. Clock speed for the values in the table is 133MHz.
3. To obtain adjusted TSD and THD values for lower clock frequencies, subtract 1.875 ns from the values in the table and add

MemClkOut(0) relative to the PLB clock (TMD) is provided. Figure 9. DDR SDRAM MemClkOut0 and Read Clock Delay Stage 1, Stage 2, or Stage 3 data for sampling at RDSP. min values assume best case conditions. max values assume worst case conditions.

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Figure 10. DDR SDRAM Read Data Path routing. It is recommended that the signal length for all of the eight DQS signals be matched. Table 22. I/O Timing—DDR SDRAM T SIN and TDIN

1. TSIN = Delay from DQS at package pin to C on Stage 1 FF.
2. TDIN = Delay from data at package pin to D on Stage 1 FF.
3. Clock speed for the values in the table is 133MHz.

system dependent and taken into account by controller initialization software. Figure 11. DDR SDRAM Read Cycle Timing—Example 1 TDIN = Delay from data at package pin to D on Stage 1 FF. TSIN = Delay from DQS at package pin to C on Stage 1 FF.

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and taken into account by controller initialization software. Figure 12. DDR SDRAM Read Cycle Timing—Example 2

system dependent and taken into account by controller initialization software. Figure 13. DDR SDRAM Read Cycle Timing—Example 3

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strapping on external pins (see “Strapping” below). resistors to select the desired default conditions. These pins are used for strap functions only during reset. shown in parentheses following the pin number. SDR0_SDSTP2 and SDR0_SDSTP3 registers accordingly. The initialization settings and their default values are covered in detail in the PowerPC 440EP User’s Manual. Table 23. Strapping Pin Assignments

440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 Revision Log Date Version Contents of Modification 08/21/2003 Initial creation of document. 09/22/2003 Misc. updates and corrections. 10/07/2003 Misc. updates and corrections. 10/13/2003 Add I/O timing. 10/31/2003 Miscellaneous updates. 11/03/2003 Correct initialization strappi ng pins and response IIC interface. 11/25/2003 Correct OV DD and SVDD pin assignments. 12/15/2003 Delete heat sink mounting information placeholders and remove Confidential status. 12/19/2003 Restore Confidential status. 01/12/2004 Update DDR SDRAM interface timing section. 03/15/2004 Correct MemClkOut0 pin assignment. Correct SDRAM PLL voltage. Add Note 6 to UARTn_CTS signal. Correct SDRAM I/O worst case spec temperature. Change 333MHz to 400MHz. 04/7/2004 Correct label on Ethernet transmit signals. 09/2/2004 Convert to AMCC format. 09/8/2004 Modify headers to flip between left and right pages like the footers. Change part numbers to AMCC part numbers. Remove Confidential status, again 09/28/2004 Add USB clock frequency numbers. Number table and figure captions. 10/06/2004 Correct USB block diagram and description. Update formatting and PDF book marking. 10/12/2004 Add missing DDR SDRAM timing data. 10/28/2004 Miscellaneous updates. 11/18/2004 Add RejectPkt signal to pin Y25. Issue 31 Corrected numbering on PCIReq signal. Issue 30 Added notes to USB signals to correctly define required pull-ups and pull-downs. Issue 20 Correct typo on voltage specification for SAVDD in the DC Power Supply Loads table. Issue 9 Misc. typo corrections. Issue 29 11/19/2004 Change bootstrap option numbers to letters and add two options. 11/22/2004 Correct bootstrap pin settings to match new letter designations. 12/17/2004 Add Revision B part numbers for both leaded and lead-free packages and tape-and-reel shipping. 01/18/2005 Add input capacitance values. Update and add missing voltage supply currents. 01/31/2005 Update DDR SDRAM timing. 02/08/2005 Change circuit type info for some system interface signals and move RejectPkt to the Ethernet group.

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440EP – PPC440EP Embedded ProcessorRevision 1.26 – April 25, 2007 Data Sheet 02/15/2005 Miscellaneous updates 03/10/2005 Miscellaneous updates 03/25/2005 Correct I/O timing specs for ExtReq signal. 04/27/2005 USB 2.0 I/O and DDR SDRAM timing updates. 05/24/2005 Add RoHS compliance statement. 06/14/2005 Updates and additions to power and thermal specifications. Add new 667MHz PNs and remove old 466MHz PNs. 07/06/2005 Change maximum NAND Flash to 256MB. 08/08/2005 Change solder ball size specification and add thermally enhanced package specification. 10/05/2005 1.20 Miscellaneous updates 11/18/2005 1.21 Remove metal-layer specification from technology description. Change default configuration when bootstrap IIC read fails from option A to configuration X. Add package nomenclature. Correct MemClkOut duty cycle. Correct and move PerErr signal description from master to slave. Change maximum VCO freqruency to 1334MHz. 02/16/2006 1.22 Add revision level 2.1 (C) part number and PVR number. 05/24/2006 1.23 Update power dissipation and add additional temperature data. 07/19/2006 1.24 Correct enable/disable specif ications for PCI Gnt/Req signals. 12/18/2006 1.25 Change analog voltage filter circuit inductor part number. Change all multiplexed GPIO signal defaults to the GPIO signals. Change AC12 default from IRQ5 to DMAReq1. Correct descriptions of LeakTest, RcvrInh, ModeCtrl, RefEn, and DrvrInh1:2 signals Remove “Preliminary” status from header. 04/25/2007 1.26 Remove thermally enhanced package. Date Version Contents of Modification

440EP – PPC440EP Embedded Processor Data Sheet Revision 1.26 – April 25, 2007 Printed in the United States of America, April 30, 2007 The following are trademarks of AMCC Corporation in the United States, or other countries, or both: AMCC Other company, product, and service names may be trademarks or service marks of others. April 30, 2007 This document contains information on a new product under development by AMCC. AMCC reserves the right to change or discontinue this product without notice. This document is a preliminary edition of the PowerPC 440EP data sheet. Make sure you are using the correct edition for the level of the product. While the information contained herein is believed to be accurate, such information is preliminary, and should not be relied upon for accuracy or completeness, and no representations or warranties of accuracy or completeness are made. The information contained in this document is subject to change or withdrawal at any time without notice and is being provided on an "AS IS" basis without warranty or indemnity of any kind, whether express or implied, including without limitation, the implied warranties of non-infringement, merchantability, or fitness for a particular purpose. Any products, services, or programs discussed in this document are sold or licensed under AMCC's standard terms and conditions, copies of which may be obtained from your local AMCC representative. Nothing in this document shall operate as an expressed or implied license or indemnity under the intellectual property rights of AMCC or third parties. Without limiting the generality of the foregoing, any performance data contained in this document was determined in a specific or controlled environment and not submitted to any formal AMCC test. Therefore, the results obtained in other operating environments may vary significantly. Under no circumstances will AMCC be liable for any damages whatsoever arising out of or resulting from any use of the document or the information contained herein.

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440EP – PPC440EP Embedded ProcessorRevision 1.26 – April 25, 2007 Data Sheet Applied Micro Circuits Corporation

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Phone: (858) 450-9333 — (800) 755-2622 — Fax: (858) 450-9885 http://www.amcc.com AMCC reserves the right to make changes to its products, its data sheets, or related documentation, without notice and war- rants its products solely pursuant to its terms and conditions of sale, only to substantially comply with the latest available data sheet. Please consult AMCC’s Term and Conditions of Sale for its warranties and other terms, conditions and limitations. AMCC may discontinue any semiconductor product or service wi thout notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information is current. AMCC does not assume any lia- bility arising out of the application or use of any product or circuit described herein, neither does it convey any license under its patent rights nor the rights of others. AMCC reserves the ri ght to ship devices of higher grade in place of those of lower grade. AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED , INTENDED, AUTHORIZED, OR WARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS. AMCC is a registered Trademark of Applied Micro Circuits Corporation. Copyright © 2007 Applied Micro Circuits Corporation.