410-251

410-251 DIGILENT | Alldatasheet

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Pullman, WA 99163 509.334.6306 www.digilentinc.com JTAG-SMT™ Programming Module for Xilinx® FPGAs Revised August 31, 2016 This manual applies to the JTAG-SMT2 rev. D DOC#: 502-251 Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 1 of 12 Overview The Joint Test Action Group (JTAG)-SMT2 is a compact, complete, and fully self-contained surface-mount programming module for Xilinx field-programmable gate arrays (FPGAs). The module can be accessed directly from all Xilinx Tools, including iMPACT, Chipscope™, and EDK. Users can load the module directly onto a target board and reflow it like any other component. The JTAG-SMT2 uses a 3.3V main power supply and a separate Vref supply to drive the JTAG signals. All JTAG signals use high speed, 24mA, three-state buffers that allow signal voltages from 1.8V to 5V and bus speeds of up to 30MBit/sec. The JTAG bus can be shared with other devices as systems hold JTAG signals at high-impedance, except when actively driven during programming. The SMT2 modu le is CE certified and fully compliant with EU RoHS and REACH directives. The module uses a standard Type-A to Micro-USB cable available for purchase from Digilent, Inc. Users can connect JTAG signals directly to the corresponding FPGA signals, as shown in Fig. 1. For best results, mount the module adjacent to the edge of the host PCB over a ground plane. Although users may run signal traces on top of the host PCB beneath the SMT2, Digilent recommends keeping the are a immediately beneath the SMT2 clear. Note: Keep the impedance between the SMT2 and FPGA below 100 Ohms to operate the JTAG at maximum speed . 4 8 GND TCK TDI TMS GPIO1 GPIO2 GPIO0 TDO VREF GND Vdd (3.3V)  Small, complete, all-in-one JTAG programming/debugging solution for Xilinx FPGAs  Compatible with all Xilinx Tools  Compatible with IEEE 1149.7-2009 Class T0 – Class T4 (includes 2-Wire JTAG)  GPIO pin allows debugging software to reset the processor core of Xilinx’s Zynq® platform  Single 3.3V supply  Separate Vref drives JTAG signal voltages; Vref can be any voltage between 1.8V and 5V.  High-Speed USB2 port that can drive JTAG/SPI bus at up to 30Mbit/sec (frequency settable by user)  SPI programming solution (modes 0 and 2 up to 30Mbit/sec, modes 1 and 3 up to 2Mbit/sec)  Uses micro-AB USB2 connector  Small form-factor surface-mount module can be directly loaded on target boards  A similar circuit is available as a stand-alone programming cable; see Digilent’s JTAG-HS2. Features include: The JTAG-SMT2 JTAG-SMT2.

Copyright Digilent, Inc. All rights reserved. support for interfacing IEEE 1149.7-2009 JTAG targets in both 2 and 4-wire modes. features supported by each port. The HS2 supports SPI modes 0, 1, 2, and 3.

2 Yes Yes Yes 30 MHz 8 KHz 0 – 1000 µS

Figure 1. JTAG-SMT2 port connections. Figure 2. SMT2 SPI port connections. Table 1. Supported features.

Copyright Digilent, Inc. All rights reserved.

1 Software Support

public application programming interfaces (API) that allow user applications to directly drive the JTAG chain. modes. Please see the Adept SDK reference manual for more information. Figure 3. 4-Wire series topology.

Copyright Digilent, Inc. All rights reserved. controller using the MScan, OScan0, and OScan1 scan formats.

3 GPIO Pins

high-impedance state until a host application enables DPIO port 0 and configures the applicable pin as an output. (100K ohm) ensure that the GPIO signals do not float while not being actively driven ( see Fig. 8). Figure 6. Adding a current limiting resistor. Figure 7. 200 Ohm resistor limiting current flow. Figure 8. GPIO signals.

Copyright Digilent, Inc. All rights reserved. section for more information. used as a general purpose I/O if the Xilinx Tools are going to be used to communicate with the SMT2. Note: DPIO port 0 can only be used while both JTAG and SPI are disabled.

4 Application Examples

voltage makes it possible to eliminate the external pull-up that is normally required for the PS_SRST_B pin. Figure 9. Connecting the JTAG-SMT2 to Xilinx’s Zynq-7000.

JTAG -SMT2™ Programming Module for Xilinx® FPGAs Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 9 of 12

5 Mechanical Information

22.75mm 21.5mm 3mm5mm 2mm 4mm Pads on bottom PCB surface 5mm 2mm 5.75mm SMT2 Top View Note: PCB dimensions have a tolerance of +/- 0.13mm. 2 3 41 9 81011 3.5mm 3.0mm 5mm 4mm 19.5mm PCB Edge Recommended PCB Land Pattern 15mm 21.75mm 6 7 3.0mm 3.5mm 4.75mm5mm 2.6mm 2.2mm 6.2mm 2.6mm 2.2mm 6.2mm Electrical Keepout 2.45mm Electrical Keepout

JTAG -SMT2™ Programming Module for Xilinx® FPGAs Copyright Digilent, Inc. All rights reserved. Other product and company names mentioned may be trademarks of their respective owners. Page 10 of 12

6 Absolute Maximum Ratings

Symbol Parameter Condition Min Max Unit Vdd Operating supply voltage -0.3 4.0 V Vref I/O reference/supply voltage -0.3 6 V VIO Signal Voltage -0.3 6 V IIK,IOK TMS, TCK, TDI, TDO, GPIO0, GPIO1, GPIO2 DC Input/Output Diode Current VIO < -0.3V -50 mA VIO > 6V +20 IOUT DC Output Current ±50 mA TSTG Storage Temperature -20 +60 ºC ESD Human Body Model JESD22-A114 4000 V Charge Device Model JESD22-C101 2000 V

7 DC Operating Characteristics

Symbol Parameter Min Typ Max Unit Vdd Operating supply voltage 2.97 3.3 3.63 Volts Vref I/O reference/supply voltage 1.65 2.5/3.3 5.5 Volts TDO, GPIO0, GPIO1, GPIO2 Input High Voltage (VIH) 1.62 5.5 Volts Input Low Voltage (VIL) 0 0.65 Volts TMS, TCK, TDI, GPIO0, GPIO1, GPIO2 Output High (VOH) 0.85 x Vref 0.95 x Vref Vref Volts Output Low (VOL) 0 0.05 x Vref 0.15 x Vref Volts TA Operating Temperature -40 -85 ºC

Copyright Digilent, Inc. All rights reserved.

8 AC Operating Characteristics

Xilinx Tools. Note: Please refer to Xilinx’s iMPACT documentation for more information.

9 Mounting to Host PCBs

suitable for reflow for up to 168 hours without additional drying. The factory finishes the JTAG-SMT2 signal pads with the ENIG process using 2u” gold over 150u” electroless nickel. solder is sufficient to hold the SMT2 firmly in place so mounting should require no additional adhesives. Figure 12. Timing diagram. Table 2. JTAG signal timing. Note: these parameters are specified for Vref = 3.3V.

Copyright Digilent, Inc. All rights reserved.

10 Packaging

and ship larger quantities in groups of 45 positioned in an antistatic bubble tray (see Fig. 14). Figure 13. JTAG-SMT2 reflow temperature over time. Figure 14. JTAG-SMT2 shipping arrangement.