38C2

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER????

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M38C2XMX MITSUBISHI | Alldatasheet

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PIN CONFIGURATION (TOP VIEW) Package type : 64P6N-A/64P6Q-A

DESCRIPTION

The 38C2 group is the 8-bit microcomputer based on the 740 family core technology. The 38C2 group has an LCD drive control circuit, a 10-channel A-D converter, and a Serial I/O as additional functions. The various microcomputers in the 38C2 group include variations of internal memory size and packaging. For details, refer to the section on part numbering.

FEATURES

(at 8MHz oscillation frequency) G Memory size (common to SEG: 24) G LCD drive control circuit G Two clock generating circuits (connect to external ceramic resonator or quartz-crystal oscillator) (average current: 15 mA, peak current: 30 mA, total current: 90 mA) G Power source voltage (at 8 MHz oscillation frequency) (at 4 MHz oscillation frequency, A-D operation excluded) (at 32 kHz oscillation frequency) G Power dissipation (at 8 MHz oscillation frequency, V CC = 5 V) (at 32 kHz oscillation frequency, VCC = 3 V) Fig. 1 M38C2XMX-XXXFP pin configuration 38C2 Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS P 06/ S E G 6 P 07/ S E G 7 P 10/ S E G 8 P 11/ S E G 9 P 12/ S E G 1 P 13/ S E G 1 P 14/ S E G 1 P 15/ S E G 1 P 16/ S E G 1 P 17/ S E G 1 P 60/ C N T R 1 P 37/ C N T R 0/ ( L E D 7 6789 1 01 11 21 41 51 54 44 14 0 3 73 63 P24/SEG 20 P25/SEG 21 COM 2 COM 1 COM 0 P27/SEG 23/VL2 P26/SEG 22/VL1 C O M 3 ( K W 7) / P 03/ S E G 3 P 04/ S E G P 05/ S E G 5 P51/INT1 ( K W 2) / P 56/ SC L K ( K W 1) / P 55/ TXD 1 ( K W 0) / P 54/ R XD 1 P 53/ T4 O U T/ P W M 1 P 20/ S E G 1 P 21/ S E G 1 P 22/ S E G 1 P 23/ S E G 1 1234 5 M 3 8 C 2 X M X - X X X F P P 36/ T2 O U T/φ/ ( L E D 6 XO U T P 52/ T3 O U T/ P W M 0 VRE F VL3 P 43/ A N 3 P 42/ A N 2 P 44/ A N 4 P 47/ R T P1/ A N 7 P 46/ R T P0/ A N 6 P 45/ A N 5 VS S P 32/ TXD 2/ ( L E D 2 P31/SCLK2 /(LED1) P33/RXD 2/(LED3) P 50/ I N T0 AV SS ( K W 6) / P 02/ S E G 2 ( K W 5) / P 01/ S E G 1 ( K W 4) / P 00/ S E G 0 P 41/ O O U T 1/ A N 1 P 40/ O O U T 0/ A N 0 C N VS S P 62/ XC O U T P 61/ XC I N VC C XI N R E S E T ( K W 3) / P 57/ SR D Y P 30/ SR D Y 2/ ( L E D 0 P 35/ TX O U T/ ( L E D 5 P 34/ I N T2/ ( L E D 4 PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. FUNCTIONAL BLOCK DIAGRAM Fig. 2 Functional block diagram T i m e r T i m e r X b i t s P W M b i t s I G B T o u t p u t T i m e r Y b i t s T i m e r b i t s T i m e r b i t s T i m e r b i t s P W M b i t s T i m e r b i t s P W M b i t s P o r t P P o r t P P o r t P I n t e r n a l p e r i p h e r a l f u n c t i o n A D c o n v e r s i o n b i t c h a n n e l S e r i a l I O S e r i a l I O ( U A R T o r C l o c k s y n c h r o n o u s S e r i a l I O ( U A R T o r C l o c k s y n c h r o n o u s L C D d r i v e c o n t r o l c i r c u i t C O M S E G S y s t e m c l o c k φ g e n e r a t i o n XI XO U T M a i n c l o c k XC I XC O U T S u b c l o c k M e m o r y R O M R A M f o r L C D d i s p l a y b y t e s R A M C P U c o r e W a t c h d o g t i m e r P o r t P P o r t P P o r t P P o r t P

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.

Apply voltage of 1.8 V to 5.5 V to VCC , and 0 V to VSS .
Reference voltage input pin for A-D converter.
GND input pin for A-D converter. Connect to VSS .
Reset input pin for active “L.”
Input and output pins for the main clock generating circuit.
Feedback resistor is built in between XIN pin and XOUT pin.
Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency. When an external clock is used, connect the clock source to XIN, and leave XOUT pin open.
Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage.
Input 0 – VL3 voltage to LCD.
LCD common output pins.
COM 2 and COM3 are not used at 1/2 duty ratio.
COM 3 is not used at 1/3 duty ratio.
8-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each port to be individually programmed as either input or output.
Pull-up control is enabled. VCC , VSS VREF AV SS RESET XIN VL3 COM 0 – COM 3 P00/SEG 0 – P03/SEG 3 P04/SEG 4 – P07/SEG 7 P10/SEG 8 – P17/SEG 15 P20/SEG 16 – P25/SEG 21 P26/SEG 22/VL1 P27/SEG 23/VL2 P30/SRDY2 P31/SCLK2 P32/TxD2 P33/RxD2 P34/INT2 P35/TXOUT P36/T2OUT /φ P37/CNTR 0 P40/OOUT0 /AN0 P41/OOUT1 /AN1 P42/AN2– P45/AN5 P46/RTP0/AN6 P47/RTP1/AN7 P50/INT0 P51/INT1 P52/T3OUT /PWM 0 P53/T4OUT /PWM 1 P54/RxD1 P55/TxD1 P56/SCLK1 P57/SRDY1 Power source Analog reference voltage Analog power source Reset input Clock input LCD power source Common output I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 I/O port P5 Function except a port function PIN DESCRIPTION Table 1 Pin description (1) FunctionPin Name
LCD segment output pins
Serial I/O2 function pins
External interrupt pin
Timer X, Timer 2 output pins
Timer X function pin
AD converter input pins
External interrupt pins
Timer 3, Timer 4 output pins
PWM output pins
Serial I/O1 function pins
Key input interrupt input pins
Key input interrupt pins
LCD power source input pins
Oscillation external output pins
Real time port function pins XOUT Clock output

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Function except a port function PIN DESCRIPTION Table 2 Pin description (2) FunctionPin Name P60/CNTR 1 P61/XCIN P62/XCOUT CNV SS I/O port P6 CNV SS

3-bit I/O port.
CMOS compatible input level.
CMOS 3-state output structure.
I/O direction register allows each pin to be individually programmed as either input or output.
Pull-up control is enabled.
VPP power input pin in the flash mode. When MCU is operating, connect to VSS .
Timer Y function pin
I/O pins for sub-clock generating circuit. Connect oscillators to them.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. PART NUMBERING Fig. 3 Part numbering M38C2 9 M C – XXX HPProduct ROM/PROM size : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M F : Mask ROM version : Flash memory version RAM size : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes Package type FP HP ROM number Omitted in Flash memory version. Characteristics – : Standard D : Extended operating temperature version : 64P6N-A package : 64P6Q-A package A B C D E F : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. GROUP EXPANSION Mitsubishi plans to expand the 38C2 group as follows. Memory Type Support for mask ROM, Flash-memory versions Memory Size Memory Expansion Plan Fig. 4 Memory expansion plan Currently supported products are listed below. As of May 2000 Package 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A 64P6N-A 64P6Q-A Product name ROM size (bytes) ROM size for User in ( ) 49152 (49022) 24576 (24446) 16384 (16254) 61440 (61310) RAM size (bytes) 2048 640 640 2048 Table 3 Support products Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Flash memory version Flash memory version Remarks Packages Products under development or planning : the development schedule and specification may be revised without notice. ROM size (bytes) 32K 28K 24K 20K 16K 12K 256 384 512 640 768 896 1024192 RAM size (bytes) 40K 48K 56K 60K Under development Under development Under development 1536 2048 M38C24M6 M38C24M4 M38C29FF Under development M38C29MC M38C29MC-XXXFP M38C29MC-XXXHP M38C24M6-XXXFP M38C24M6-XXXHP M38C24M4-XXXFP M38C24M4-XXXHP M38C29FFFP M38C29FFHP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 38C2 group uses the standard 740 Family instruction set. Refer to the table of 740 Family addressing modes and machine instruc- tions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 Family instructions are as follows: The FST and SLW instructions cannot be used. The STP, WIT, MUL, and DIV instructions can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the con- tents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and pop- ping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with program when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit regis- ters PC H and PCL. It is used to indicate the address of the next in- struction to be executed. Fig. 5 740 Family CPU register structure A Accumulator b7 b0 b7b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPC H N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Table 4 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 6 Register push and pop at interrupt generation and subroutine call N o t e: C o n d i t i o n f o r a c c e p t a n c e o f a n i n t e r r u p t I n t e r r u p t e n a b l e f l a g i s “ 1 ” E x e c u t e J S R O n g o i n g R o u t i n e M S P C H ) S S M S P C L) E x e c u t e R T S P C L)M S S S S S S S P C H )M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M S P S E x e c u t e R T I P S S S S S S I n t e r r u p t S e r v i c e R o u t i n e P O P c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r f r o m s t a c k M S P C H ) S S M S P C L) S S P C L)M S S S S S P C H )M S P O P r e t u r n a d d r e s s f r o m s t a c k I F l a g i s s e t f r o m “ 0 ” t o “ 1 ” F e t c h t h e j u m p v e c t o r P u s h r e t u r n a d d r e s s o n s t a c k P u s h c o n t e n t s o f p r o c e s s o r s t a t u s r e g i s t e r o n s t a c k I n t e r r u p t r e q u e s t N o t e I n t e r r u p t d i s a b l e f l a g i s “ 0 ”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. [Processor Status Register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic opera- tion and 3 flags which decide MCU operation. Branch operations can be performed by testing the Carry (C) flag , Zero (Z) flag, Over- flow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arithmetic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt generated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are ex- ecuted in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was gener- ated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to gener- ate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed be- tween accumulator and memory. When the T flag is “1”, direct arith- metic operations and direct data transfers are enabled between memory locations.
Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location operated on by the BIT instruction is stored in the overflow flag.
Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 5 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the control bit for the internal system clock. The CPU mode register is allocated at address 003B 16. Fig. 7 Structure of CPU mode register Not available Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : RAM in the zero page is used as stack area 1 : RAM in page 1 is used as stack area Not used (returns “1” when read) (Do not write “0” to this bit.) Main clock (X IN–XOUT ) division ratio selection bits b5 b4 0 0 : XIN/8 (frequency/8 mode) 0 1 : XIN/4 (frequency/4 mode) 1 0 : XIN/2 (frequency/2 mode) 1 1 : XIN (through mode) System clock control bits b7 b6 0 0 : X IN stop, XCIN oscillating, system clock = XCIN 0 1 : XIN oscillating, XCIN stop, system clock = XIN 1 0 : XIN oscillating, XCIN oscillating, system clock = XCIN 1 1 : XIN oscillating, XCIN oscillating, system clock = XIN CPU mode register (CPUM (CM) : address 003B16) b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains control registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page Access to this area with only 2 bytes is possible in the special page addressing mode. Fig. 8 Memory map diagram 010016 0 0 0 01 0 0 4 01 0 8 4 01 F F 0 01 F F D C 1 F F F E1 F F F F1 1 9 2 XXXX 16 0 0 F F1 B B B 4 0 9 6 F 0 0 01 E D C B A F 0 8 01 E D C B A Y Y Y Y1 Z Z Z Z1 RAM ROM R A M a r e a R A M s i z e b y t e s A d d r e s s X X X ROM area R O M s i z e b y t e s Address YYYY 16 Address ZZZZ 16 R e s e r v e d a r e a S F R a r e a N o t u s e d Interrupt vector area R e s e r v e d R O M a r e a b y t e s Zero page S p e c i a l p a g e L C D d i s p l a y R A M a r e a R e s e r v e d R O M a r e a S F R a r e a 0 0 4 C 1

0 F E 01

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 9 Memory map of special function register (SFR) 0FF916 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) A-D control register (ADCON) A-D conversion register (low-order) (ADL) A-D conversion register (high-order) (ADH) Interrupt control register 2 (ICON2) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1 (IREQ1) Interrupt request register 2 (IREQ2) Interrupt control register 1 (ICON1) Timer 1 (T1) Timer 3 (T3) PWM01 register (PWM01) Timer 12 mode register (T12M) Timer 2 (T2) Timer 4 (T4) Compare register (low-order) (COMPL) Compare register (high-order) (COMPH) Timer X (low-order) (TXL) LCD power control register (VLCON) LCD mode register (LM) Timer X (high-order) (TXH) Timer X (extension) (TXEX) 0FF0 0FF116 0FF216 0FF316 0FF416 0FF516 0FF616 0FF716 0FE0 16 0FE1 16 0FE2 16 0FE6 16 0FE7 16 0FE9 16 0FE3 16 0FE4 16 0FE5 16 Port P3 direction register (P3D) Transmit/receive buffer register 1 (TB1/RB1) Serial I/O1 status register (SIO1STS) Transmit/receive buffer register 2 (TB2/RB2) Serial I/O2 status register (SIO2STS) UART1 control register (UART1CON) Serial I/O1 control register (SIO1CON) Serial I/O2 control register (SIO2CON) Baudrate generator 1 (BRG1) Baudrate generator 2 (BRG2) UART2 control register (UART2CON) 0FEA 16 0FEB 16 0FEC 16 0FED 16 0FEE 16 0FEF 16 Clock output control register (CKOUT) PULL register (PULL) Timer 34 mode register (T34M) Timer Y (low-order) (TYL) Timer Y (high-order) (TYH) Timer X mode register (TXM) Timer Y mode register (TYM) Watchdog timer control register (WDTCON) 0FF816 0FFA 16 0FFB 16 0FFC 16 0FFD 16 0FFE 16 0FFF 16 Oscillation output control register (OSCOUT) Key input control register (KIC) Timer 1234 mode register (T1234M) Timer X control register (TXCON) Timer 12 frequency division selection register (PRE12) Timer 34 frequency division selection register (PRE34) Timer XY frequency division selection register (PREXY) Segment output disable register 0 (SEG0) Segment output disable register 1 (SEG1) Segment output disable register 2 (SEG2) Timer Y mode register 2 (TYM2) Flash memory control register (FMCR) Reserved area 0FE8 16

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. I/O PORTS Direction Registers The I/O ports P0–P6 have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit of the direction register, the correspond- ing pin becomes an input pin. As for ports P0–P2, when “1” is written to the bit of the direction register and the segment output disable register, the corresponding pin becomes an output pin. As for ports P3 –P6, when “1” is written to the bit of the direction register, the corresponding pin becomes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are float- ing. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Pull-up Control Each individual bit of ports P0–P2 can be pulled up with a program by setting direction registers and segment output disable registers 0 to 2 (addresses 0FF8 16 to 0FFA16). The pin is pulled up by setting “0” to the direction register and “1” to the segment output disable register. By setting the PULL register (address 0FF116), ports P3–P6 can con- trol pull-up with a program. However, the contents of PULL register do not affect ports pro- grammed as the output ports. Fig. 11 Structure of PULL register and segment output disable register Fig. 10 Structure of ports P0 to P2 S e g m e n t o u t p u t d i s a b l e r e g i s t e r D i r e c t i o n r e g i s t e r I n p u t p o r t N o p u l l u p S e g m e n t o u t p u t P o r t o u t p u t I n p u t p o r t P u l l u p I n i t i a l s t a t e P30–P33 pull-up P34–P37 pull-up P40–P43 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60–P62 pull-up Not used (return “0” when read) PULL register (PULL : address 0FF116) b7 b0 P00 pull-up P01 pull-up P02 pull-up P03 pull-up P04 pull-up P05 pull-up P06 pull-up P07 pull-up Segment output disable register 0 (SEG0 : address 0FF816) b7 b0 Note: The PULL register and segment output disable register affect only ports programmed as the input ports. 0: No pull-up 1: Pull-up P10 pull-up P11 pull-up P12 pull-up P13 pull-up P14 pull-up P15 pull-up P16 pull-up P17 pull-up b7 b0 Segment output disable register 1 (SEG1 : address 0FF916) P20 pull-up P21 pull-up P22 pull-up P23 pull-up P24 pull-up P25 pull-up P26 pull-up P27 pull-up b7 b0 Segment output disable register 2 (SEG2 : address 0FFA16) 0: No pull-up 1: Pull-up

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Name Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Common Input/Output Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits Input/Output, individual bits Output I/O format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD common output Non-port function LCD segment output Serial I/O2 function I/O External interrupt input Timer X output Timer 2 output Timer X function input A-D conversion input External interrupt input Timer 3 output Timer 4 output PWM output Serial I/O1 function I/O Timer Y function input Sub-clock oscillation circuit Related SFRs Segment output disable register 1 Segment output disable register 2 Segment output disable register 3 PULL register Serial I/O2 control register Serial I/O2 status register UART2 control register PULL register Interrupt edge selection register PULL register Timer X mode register Timer 12 mode register PULL register Timer X mode register PULL register A-D control register PULL register A-D control register Timer Y mode register PULL register Interrupt edge selection register PULL register Timer 12 mode register PULL register Serial I/O1 control register Serial I/O1 status register UART1 control register PULL register Timer Y mode register PULL register CPU mode register LCD mode register Ref. No. (1) (2) (3) (4) (5) (6) (7) (8) (9) (7) (11) (10) (11) (7) (9) (12) (13) (14) (15) (7) (16) (17) (18) Table 6 List of I/O port function Notes 1: For details of how to use double/triple function ports as function I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. P00/SEG 0 – P03/SEG 3 P04/SEG 4 – P07/SEG 7 P10/SEG 8 – P17/SEG 15 P20/SEG 16 – P25/SEG 21 P26/SEG 22/VL1 P27/SEG 23/VL2 P30/SRDY2 P31/SCLK2 P32/TxD2 P33/RxD2 P34/INT2 P35/TXOUT P36/T2OUT /φ P37/CNTR 0 P40/OOUT0 /AN0 P41/OOUT1 /AN1 P42/AN2– P45/AN5 P46/RTP0/AN6 P47/RTP1/AN7 P50/INT0 P51/INT1 P52/T3OUT /PWM 0 P53/T4OUT /PWM 1 P54/RxD1 P55/TxD1 P56/SCLK1 P57/SRDY1 P60/CNTR 1 P61/XCIN P62/XCOUT COM 0–COM 3 Pin Key input (key-on wakeup) interrupt input LCD power input Oscillation external output Real time port function output Key input (key-on wakeup) interrupt input

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 12 Port block diagram (1) P o r t s P 00– P (3) Port P30 Data bus Serial I/O output P o r t l a t c h P u l l u p c o n t r o l Serial I/O ready output Data bus P o r t l a t c h D i r e c t i o n r e g i s t e r P u l l u p c o n t r o l P u l l u p c o n t r o l Direction register Data bus S e r i a l I O i n p u t P o r t l a t c h Data bus S e r i a l I O c l o c k o u t p u t S e r i a l I O c l o c k i n p u t Serial I/O mode selection bit Serial I/O enable bit Port latch Direction register P u l l u p c o n t r o l S e g m e n t o u t p u t d i s a b l e b i t D a t a b u s P o r t l a t c h VL 2/ VL VL 1/ VS S K e y i n p u t c o n t r o lK e y - o n w a k e u p i n t e r r u p t i n p u t S e g m e n t d a t a S e g m e n t o u t p u t d i s a b l e b i t D i r e c t i o n r e g i s t e r D a t a b u s P o r t l a t c h L C D p o w e r i n p u t ( VL 1, VL o n l y f o r P 26, P VL 2/ VL VL 1/ VS S S e g m e n t d a t a S e g m e n t o u t p u t d i s a b l e b i t Segment output disable bit P o r t s P 04– P 07, P P D i r e c t i o n r e g i s t e r Serial I/O mode selection bit Serial I/O enable bit SRDY output enable bit (5) Port P32 P 32/ T x D 2 P c h a n n e l o u t p u t d i s a b l e b i t S e r i a l I O e n a b l e b i t T r a n s m i t e n a b l e b i t (6) Port P33 S e r i a l I O e n a b l e b i t R e c e i v e e n a b l e b i t P o r t P Serial I/O synchronous clock selection bit Serial I/O enable bit D i r e c t i o n r e g i s t e r

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 13 Port block diagram (2) A n a l o g i n p u t p i n s e l e c t i o n b i t A-D conversion input D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r Pull-up control Data bus Serial I/O clock output Port latch Direction register Pull-up control Serial I/O clock input K e y o n w a k e u p i n t e r r u p t i n p u t K e y i n p u t c o n t r o l Data bus Direction register Port latch P u l l u p c o n t r o l Port latchData bus P u l s e o u t p u t m o d e T i m e r X o u t p u t D i r e c t i o n r e g i s t e r Pull-up control Direction register D a t a b u s Serial I/O enable bit Receive enable bit Port latch Pull-up control Serial I/O input Key-on wakeup interrupt input K e y i n p u t c o n t r o l P o r t l a t c hD a t a b u s D i r e c t i o n r e g i s t e r P u l l u p c o n t r o l Data bus P o r t l a t c h Direction register Pull-up control Analog input pin selection bit A D c o n v e r s i o n i n p u t D a t a b u s S e r i a l I O o u t p u t Port latch Direction register Pull-up control K e y o n w a k e u p i n t e r r u p t i n p u t K e y i n p u t c o n t r o l P o r t s P 34, P 37, P 50, P 51, P P o r t s P 36, P 52, P P o r t s P 40, P 41, P 46, P P o r t P (14) Port P56 (12) Port P54 (8) Port P35 (10) Ports P42–P45 C N T R 0, C N T R 1 i n t e r r u p t i n p u t I N T0– I N i n t e r r u p t i n p u t P o r t T i m e r o u t p u t s e l e c t i o n T i m e r o u t p u t P W M o u t p u t T i m e r o u t p u t S y s t e m c l o c k φ o u t p u t O s c i l l a t i o n o u t p u t c o n t r o l b i t R e a l t i m e c o n t r o l b i t O s c i l l a t i o n o u t p u t D a t a f o r r e a l t i m e p o r t S e r i a l I O e n a b l e b i t T r a n s m i t e n a b l e b i t S e r i a l I O s y n c h r o n o u s c l o c k s e l e c t i o n b i t S e r i a l I O e n a b l e b i t S e r i a l I O m o d e s e l e c t i o n b i t S e r i a l I O e n a b l e b i t P 55/ T x D 1 P c h a n n e l o u t p u t d i s a b l e b i t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 14 Port block diagram (3) VL3 VL2 VL1 VSS P o r t P S e r i a l I O r e a d y o u t p u t Data bus P o r t l a t c h D i r e c t i o n r e g i s t e r P u l l u p c o n t r o l K e y o n w a k e u p i n t e r r u p t i n p u t Key input control X c o s c i l l a t i o n e n a b l e d Port P61 Oscillator Xc oscillation enabled (17) Port P62 D a t a b u s P o r t l a t c h D i r e c t i o n r e g i s t e r X c o s c i l l a t i o n e n a b l e d P u l l u p c o n t r o l ( C O M 0– C O M 3 P o r t P Data bus Port latch Direction register X c o s c i l l a t i o n e n a b l e d Xc oscillation enabled + Pull-up control Sub-clock generation circuit input S e r i a l I O m o d e s e l e c t i o n b i t S e r i a l I O e n a b l e b i t SR D Y o u t p u t e n a b l e b i t Gate input signal of each gate depends on the duty ratio and bias values.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. INTERRUPTS Interrupts occur by nineteen sources: six external, twelve internal, and one software. Interrupt Control Each interrupt except the BRK instruction interrupt have both an in- terrupt request bit and an interrupt enable bit, and is controlled by the interrupt disable flag. An interrupt occurs if the corresponding inter- rupt request and enable bits are “1” and the interrupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt re- quest bits can be cleared by software, but cannot be set by software. The BRK instruction interrupt and reset cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt and reset. If several interrupts requests occurs at the same time the interrupt with highest priority is accepted first. Interrupt Operation By acceptance of an interrupt, the following operations are automati- cally performed: 1. The processing being executed is stopped. 2. The contents of the program counter and processor status reg- ister are automatically pushed onto the stack. 3. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 4. The interrupt jump destination address is read from the vector table into the program counter. I Notes on Interrupts When the active edge of an external interrupt (INT0 – INT2, CNTR0 or CNTR1) is set or an interrupt source where several interrupt source is assigned to the same vector address is switched, the correspond- ing interrupt request bit may also be set. Therefore, take following sequence: (1) Disable the interrupt. (2) Set the interrupt edge selection register (Timer X control reg- ister for CNTR 0, Timer Y mode register for CNTR1). (3) Clear the set interrupt request bit to “0.” (4) Enable the interrupt. Interrupt Source Reset (Note 2) INT0 INT1 INT2 Key input (key-on wakeup) Serial I/O1 receive Serial I/O1 transmit Serial I/O2 receive Serial I/O2 transmit Timer X Timer 1 Timer 2 Timer 3 Timer 4 CNTR Timer Y CNTR A-D conversion BRK instruction Priority Vector Addresses (Note 1) High FFFD FFFB 16 FFF9 16 FFF7 16 FFF5 16 FFF3 16 FFF116 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE5 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 Interrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT 0 input At detection of either rising or falling edge of INT1 input At detection of either rising or falling edge of INT2 input At falling of ports P00–P03, P54–P57 input logical level AND At completion of serial I/O1 data receive At completion of serial I/O1 transmit shift or transmit buffer is empty At completion of serial I/O2 data receive At completion of serial I/O2 transmit shift or transmit buffer is empty At timer X underflow At timer 1 underflow At timer 2 underflow At timer 3 underflow At timer 4 underflow At detection of either rising or falling edge of CNTR 0 input At timer Y underflow At detection of either rising or falling edge of CNTR 1 input At completion of A-D conversion At BRK instruction execution Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when INT 2 interrupt is selected External interrupt (active edge selectable) Valid when key input interrupt is selected External interrupt (falling valid) Valid only when serial I/O1 is selected Valid only when serial I/O1 is selected Valid only when serial I/O2 is selected Valid only when serial I/O2 is selected Valid only when timer 1 interrupt is selected Valid only when timer 2 interrupt is selected External interrupt (active edge selectable) External interrupt (active edge selectable) Valid when A-D conversion interrupt is se- lected Non-maskable software interrupt Low FFFC FFFA 16 FFF8 16 FFF6 16 FFF4 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE4 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 Notes 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Table 7 Interrupt vector addresses and priority Remarks

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 15 Interrupt control Fig. 16 Structure of interrupt-related registers Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request b7 b0 Interrupt edge selection register INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT2/Key input interrupt switch bit Timer Y/CNTR1 interrupt switch bit Not used (return “0” when read) (Do not write to “1”) (INTEDGE : address 003A16) Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit INT2 interrupt request bit Key input interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Serial I/O2 receive interrupt request bit Serial I/O2 transmit interrupt request bit Timer X interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit INT2 interrupt enable bit Key input interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Serial I/O2 receive interrupt enable bit Serial I/O2 transmit interrupt enable bit Timer X interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C16) (ICON1 : address 003E16) Interrupt request register 2 Timer 1 interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Timer 4 interrupt request bit CNTR 0 interrupt request bit Timer Y interrupt request bit CNTR 1 interrupt request bit AD conversion interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D16) Interrupt control register 2 Timer 1 interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit Timer 4 interrupt enable bit CNTR 0 interrupt enable bit Timer Y interrupt enable bit CNTR 1 interrupt enable bit AD conversion interrupt enable bit Not used (returns “0” when read) (Do not write to “1”.) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16) 0 : Falling edge active 1 : Rising edge active b7 b0 b7 b0 b7 b0 b7 b0 0 : INT2 interrupt 1 : Key input interrupt 0 : Timer Y interrupt 1 : CNTR1 interrupt

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Key Input Interrupt (Key-on Wake-Up) A key input interrupt request is generated by detecting the falling edge from any pin of ports P00–P03, P54–P57 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by press- ing one of the keys consisted as an active-low key matrix which in- puts to ports P5 4–P57. Fig. 17 Connection example when using key input interrupt and ports P0 and P5 block diagram Key input control register = “1” K e y i n p u t c o n t r o l r e g i s t e r K e y i n p u t c o n t r o l r e g i s t e r Key input control register = “1” Key input control register = “1” Key input control register = “1” Key input control register = “1” Port P54 latch Port P54 direction register = “0” Port P55 latch P o r t P 55 d i r e c t i o n r e g i s t e r Port P56 latch Port P56 direction register = “0” Port P57 latch P o r t P 57 d i r e c t i o n r e g i s t e r P o r t P 00 l a t c h Port P00 direction register = “1” Port P01 latch Port P01 direction register = “1” Port P02 latch P o r t P 02 d i r e c t i o n r e g i s t e r P o r t P 03 l a t c h Port P03 direction register = “1” P 54 i n p u t P 55 i n p u t P56 input P 57 i n p u t P 00 o u t p u t P 01 o u t p u t P 02 o u t p u t P 03 o u t p u t PULL register Bit 5 = “1” P o r t P 0 I n p u t r e a d i n g c i r c u i t P o r t P X x L l e v e l o u t p u t K e y i n p u t i n t e r r u p t r e q u e s t P o r t P 5 I n p u t r e a d i n g c i r c u i t Key input control register = “1” Segment output disable register 1 Bit 3 = “1” S e g m e n t o u t p u t d i s a b l e r e g i s t e r B i t Segment output disable register 1 Bit 1 = “1” Segment output disable register 1 Bit 0 = “1” ✽ P-channel transistor for pull-up ✽ ✽ CMOS output buffer ✽ ✽✽

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. A key input interrupt is controlled by the key input control register and port direction registers. When the key input interrupt is enabled, set “1” to the key input control register. A key input of any pin of ports 0–P03, P54–P57 that have been set to input mode is accepted. Fig. 18 Structure of key input control register Key input control register P54 key input control bit P55 key input control bit P56 key input control bit P57 key input control bit P00 key input control bit P01 key input control bit P02 key input control bit P03 key input control bit (KIC : address 0FF216) b7 b0 0 : Key input interrupt disabled 1 : Key input interrupt enabled

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. TIMERS 8-Bit Timer The 38C2 group has four built-in timers : Timer 1, Timer 2, Timer 3, and Timer 4. Each timer has the 8-bit timer latch. All timers are down-counters. When the timer reaches “00 16,” the contents of the timer latch is reloaded into the timer with the next count pulse. In this mode, the interrupt request bit corresponding to that timer is set to “1.” The count can be stopped by setting the stop bit of each timer to “1.” G Frequency Divider For Timer Timer 1, timer 2, timer 3 and timer 4 have the frequency divider for the count source. The count source of the frequency divider is switched to X IN or XCIN by the CPU mode register. The frequency divider is controlled by the 3-bit register. The division ratio can be selected from as follows; IN) or f(XCIN). G Timer 1, Timer 2 The count sources of timer 1 and timer 2 can be selected by setting the timer 12 mode register. When f(X CIN) is selected as the count source, counting can be per- formed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. Also, by the timer 12 mode register, each time timer 2 underflows, the signal of which polarity is inverted can be output from P36/T2OUT pin. At reset, all bits of the timer 12 mode register are cleared to “0,” timer 1 is set to “FF16,” and timer 2 is set to “0116.” When executing the STP instruction, previously set the wait time at return. G Timer 3, Timer 4 The count sources of timer 3 and timer 4 can be selected by setting the timer 34 mode register. Also, by the timer 34 mode register, each time timer 3 or timer 4 underflows, the signal of which polarity is inverted can be output from P5 2/T3OUT pin or P53/T4OUT pin. G Timer 3 PWM 0 Mode, Timer 4 PWM1 Mode A PWM rectangular waveform corresponding to the 10-bit accuracy can be output from the P52/PWM 0 pin and P53/PWM 1 pin by set- ting the timer 34 mode register and PWM01 register (refer to Figure 21). The “n” is the value set in the timer 3 (address 002216) or the timer 4 (address 002316). The “ts” is one period of timer 3 or timer 4 count source. One output pulse is the short interval. Four output pulses are the long interval. “H ” width of the short interval is obtained by n ✕ ts. However, in the long interval, “H ” width of output pulse is extended for ts which is set by the PWM01 register (address 0024 16).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Timer 12 mode register (T12M: address 002516) Timer 1 count stop bit 0 : Count operation 1 : Count stop Timer 2 count stop bit 0 : Count operation 1 : Count stop Timer 1 count source selection bits b3 b2 0 0 : Frequency divider for Timer 1 0 1 : f(X CIN) 1 0 : Underflow of Timer Y 1 1 : Not available Timer 2 count source selection bits b5 b4 0 0 : Underflow of Timer 1 0 1 : f(XCIN) 1 0 : Frequency divider for Timer 2 1 1 : Not available Timer 2 output selection bit (P36) 0 : I/O port 1 : Timer 2 output T2OUT output edge switch bit 0 : Start at “L” output 1 : Start at “H ” output Timer 34 mode register (T34M: address 002616) Timer 3 count stop bit 0 : Count operation 1 : Count stop Timer 4 count stop bit 0 : Count operation 1 : Count stop Timer 3 count source selection bit 0 : Frequency divider for Timer 3 1 : Underflow of Timer 2 Timer 4 count source selection bits b4 b3 0 0 : Frequency divider for Timer 4 0 1 : Underflow of Timer 3 1 0 : Underflow of Timer 2 1 1 : Not available Timer 3 operating mode selection bit 0 : Timer mode 1 : PWM mode Timer 4 operating mode selection bit 0 : Timer mode 1 : PWM mode Not used (returns “0” when read) Timer 1234 mode register (T1234M: address 0FF316) T3OUT output edge switch bit 0 : Start at “L” output 1 : Start at “H ” output T4OUT output edge switch bit 0 : Start at “L” output 1 : Start at “H ” output Timer 3 output selection bit (P52) 0 : I/O port 1 : Timer 3 output Timer 4 output selection bit (P53) 0 : I/O port 1 : Timer 4 output Timer 2 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 3 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer 4 write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Not used (returns “0” when read) b7 b0 b7 b0 b7 b0 PWM01 register (PWM01: address 002416) PWM0 set bits b1 b0 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods PWM1 set bits b3 b2 0 0 : No extended 0 1 : Extended once in four periods 1 0 : Extended twice in four periods 1 1 : Extended three times in four periods Not used (returns “0” when read) Timer 12 frequency division selection register (PRE12: address 0FF5 16) Timer 1 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 ✕ f(XIN) or 1/16 ✕ f(XCIN) 0 0 1 : 1/1 ✕ f(XIN) or 1/1 ✕ f(XCIN) 0 1 0 : 1/2 ✕ f(XIN) or 1/2 ✕ f(XCIN) 0 1 1 : 1/32 ✕ f(XIN) or 1/32 ✕ f(XCIN) 1 0 0 : 1/64 ✕ f(XIN) or 1/64 ✕ f(XCIN) 1 0 1 : 1/128 ✕ f(XIN) or 1/128 ✕ f(XCIN) 1 1 0 : 1/256 ✕ f(XIN) or 1/256 ✕ f(XCIN) 1 1 1 : 1/1024 ✕ f(XIN) or 1/1024 ✕ f(XCIN) Timer 2 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 ✕ f(XIN) or 1/16 ✕ f(XCIN) 0 0 1 : 1/1 ✕ f(XIN) or 1/1 ✕ f(XCIN) 0 1 0 : 1/2 ✕ f(XIN) or 1/2 ✕ f(XCIN) 0 1 1 : 1/32 ✕ f(XIN) or 1/32 ✕ f(XCIN) 1 0 0 : 1/64 ✕ f(XIN) or 1/64 ✕ f(XCIN) 1 0 1 : 1/128 ✕ f(XIN) or 1/128 ✕ f(XCIN) 1 1 0 : 1/256 ✕ f(XIN) or 1/256 ✕ f(XCIN) 1 1 1 : 1/1024 ✕ f(XIN) or 1/1024 ✕ f(XCIN) Not used (returns “0” when read) b7 b0 b7 b0 Timer 34 frequency division selection register (PRE34: address 0FF616) Timer 3 frequency division selection bits b2 b1 b0 0 0 0 : 1/16 ✕ f(XIN) or 1/16 ✕ f(XCIN) 0 0 1 : 1/1 ✕ f(XIN) or 1/1 ✕ f(XCIN) 0 1 0 : 1/2 ✕ f(XIN) or 1/2 ✕ f(XCIN) 0 1 1 : 1/32 ✕ f(XIN) or 1/32 ✕ f(XCIN) 1 0 0 : 1/64 ✕ f(XIN) or 1/64 ✕ f(XCIN) 1 0 1 : 1/128 ✕ f(XIN) or 1/128 ✕ f(XCIN) 1 1 0 : 1/256 ✕ f(XIN) or 1/256 ✕ f(XCIN) 1 1 1 : 1/1024 ✕ f(XIN) or 1/1024 ✕ f(XCIN) Timer 4 frequency division selection bits b5 b4 b3 0 0 0 : 1/16 ✕ f(XIN) or 1/16 ✕ f(XCIN) 0 0 1 : 1/1 ✕ f(XIN) or 1/1 ✕ f(XCIN) 0 1 0 : 1/2 ✕ f(XIN) or 1/2 ✕ f(XCIN) 0 1 1 : 1/32 ✕ f(XIN) or 1/32 ✕ f(XCIN) 1 0 0 : 1/64 ✕ f(XIN) or 1/64 ✕ f(XCIN) 1 0 1 : 1/128 ✕ f(XIN) or 1/128 ✕ f(XCIN) 1 1 0 : 1/256 ✕ f(XIN) or 1/256 ✕ f(XCIN) 1 1 1 : 1/1024 ✕ f(XIN) or 1/1024 ✕ f(XCIN) Not used (returns“0”when read) b7 b0 Fig. 19 Structure of timer related register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 20 Block diagram of timers 1, 2, 3 and 4 Timer 1 latch (8) T i m e r T i m e r i n t e r r u p t r e q u e s t T i m e r i n t e r r u p t r e q u e s t T i m e r i n t e r r u p t r e q u e s t XCIN D a t a b u s Timer 1 count stop bit 10 bit PWM1 circuit Q Q S TP l a t c h P53/PWM 1/T4OUT 10 bit PWM0 circuit Q Q S T T i m e r o p e r a t i n g m o d e s e l e c t i o n b i t P52 latch Timer 3 output control bit P52 direction register P 52/ P W M 0/ O U T “00” “01” C l o c k f o r T i m e r C l o c k f o r T i m e r Clock for Timer 3 C l o c k f o r T i m e r S y s t e m c l o c k c o n t r o l b i t s F r e q u e n c y d i v i s i o n s e l e c t i o n b i t s b i t s f o r e a c h T i m e r C l o c k f o r T i m e r C l o c k f o r T i m e r C l o c k f o r T i m e r C l o c k f o r T i m e r T h e f o l l o w i n g v a l u e s c a n b e s e l e c t e d t h e c l o c k f o r T i m e r Frequency divider 1/2Q Q S T T2OUT output edge switch bit Timer 2 output control bit P36 direction register P 36/ O U f L E D 6) P36 latch T i m e r o u t p u t s e l e c t i o n b i t P c l o c k o u t p u t c o n t r o l b i t XC I N XI N S y s t e m c l o c k f “10”T i m e r Y o u t p u t T i m e r w r i t e c o n t r o l b i t PWM01 register (2) P W M r e g i s t e r Timer 2 write control bit T i m e r c o u n t s o u r c e s e l e c t i o n b i t s Timer 2 count source selection bits Timer 2 count stop bit Timer 3 count source selection bit Timer 3 count stop bit T i m e r T i m e r T i m e r T i m e r Timer 2 latch (8) T i m e r Timer 3 latch (8) Timer 3 (8) T i m e r i n t e r r u p t r e q u e s t T i m e r w r i t e c o n t r o l b i t Timer 4 latch (8) T i m e r Timer 4 count source selection bits Timer 4 count stop bit T3OUT output edge switch bitT i m e r o u t p u t s e l e c t i o n b i t T i m e r o p e r a t i n g m o d e s e l e c t i o n b i t Timer 4 output control bit P d i r e c t i o n r e g i s t e r O U T o u t p u t e d g e s w i t c h b i tT i m e r o u t p u t s e l e c t i o n b i t “0” “1” “0” “1” “1” “0” “1” “0” “0” “1” “01” “00” “1” “0” “

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 21 Waveform of PWM01 16-bit Timer G Frequency Divider For Timer Each timer X and timer Y have the frequency dividers for the count source. The count source of the frequency divider is switched to XIN or XCIN by the CPU mode register. The division ratio of each timer can be controlled by the 3-bit register. The division ratio can be se- lected from as follows; IN) or f(XCIN). G Timer X The timer X count source can be selected by setting the timer X mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. The timer X operates as down-count. When the timer contents reach “000016”, an underflow occurs at the next count pulse and the timer latch contents are reloaded. After that, the timer continues count- down. When the timer underflows, the interrupt request bit correspond- ing to the timer X is set to “1”. Six operating modes can be selected for timer X by the timer X mode register and timer X control register. (1) Timer Mode The count source can be selected by setting the timer X mode regis- ter. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). (2) Pulse Output Mode Pulses of which polarity is inverted each time the timer underflows are output from the T XOUT pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the T XOUT pin to output mode. (3) IGBT Output Mode After dummy output from the TXOUT pin, count starts with the INT0 pin input as a trigger. In the case that the timer X output edge switch bit is “0”, when the trigger is detected or the timer X underflows, “H ” is output from the TXOUT pin. When the count value corresponds with the compare register value, the TXOUT output becomes “L”. After noise is cleared by noise filters, judging continuous 4-time same levels with sampling clocks to be signals, the INT0 signal can use 4 types of delay time by a delay circuit. When using this mode, set the port sharing the INT 0 pin to input mode and set the port sharing the TXOUT pin to output mode. When the timer X output control bit 1 or 2 of the timer X control reg- ister is set to “1”, the timer X count stop bit is fixed to “1” forcibly by the interrupt signal of INT1 or INT2. And then, by stopping the timer X counting, the TXOUT output can be fixed to the signal output at that time. Do not write “1” to the timer X register (extension) when using the IGBT output mode. (4) PWM Mode IGBT dummy output, an external trigger with the INT0 pin and output control with pins INT1 and INT2 are not used. Except for those, this mode operates just as in the IGBT output mode. The period of PWM waveform is specified by the timer X set value. In the case that the timer X output edge switch bit is “0”, the “H ” interval is specified by the compare register set value. When using this mode, set the port sharing the T XOUT pin to output mode. Do not write “1” to the timer X register (extension) when using the PWM mode. O u t p u t w a v e f o r m o f T i m e r 3 P W M 0 o r T i m e r 4 P W M 1 256 ✕ ts 256 ✕ ts 256 ✕ ts 256 ✕ ts n t sn ✕ tsn t sn t s n t sn t sn t s n ✕ ts n t s n t s P W M 0 1 r e g i s t e r = “ 0 02” n: Setting value of Timer 3 or Timer 4 ts: One period of Timer 3 count source or Timer 4 count source PWM01 register (address 0024 16) : 2-bit value corresponding to PWM0 or PWM1 (n+1) ✕ ts (n+1) ✕ ts (n+1) ✕ ts (n+1) ✕ ts ( n t s n t s P W M 0 1 r e g i s t e r = “ 0 12” P W M 0 1 r e g i s t e r = “ 1 02” P W M 0 1 r e g i s t e r = “ 1 12” S h o r t i n t e r v a l Short interval Short interval S h o r t i n t e r v a l 4 ✕ 256 ✕ ts Long interval

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 22 Waveform of PWM/IGBT (5) Event Counter Mode The timer counts signals input through the CNTR0 pin. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When using this mode, set the port sharing the CNTR pin to input mode. In this mode, the window control can be performed by the timer 1 underflow. When the bit 5 (data for control of event counter window) of the timer X mode register is set to “1”, counting is stopped at the next timer 1 underflow. When the bit is set to “0”, counting is re- started at the next timer 1 underflow. (6) Pulse Width Measurement Mode In this mode, the count source is the output of frequency divider for timer. In this mode, timer X operates as the 18-bit counter by setting the timer X register (extension). When the bit 6 of the CNTR 0 active edge switch bits is “0”, counting is executed during the “H ” interval of CNTR 0 pin input. When the bit is “1”, counting is executed during the “L” interval of CNTR0 pin input. When using this mode, set the port sharing the CNTR0 pin to input mode. I Notes on Timer X (1) Write Order to Timer X

In the timer mode, pulse output mode, event counter mode and pulse width measurement mode, write to the following registers in the order as shown below; the timer X register (extension), the timer X register (low-order), the timer X register (high-order). Do not write to only one of them. When the above mode is set and timer X operates as the 16-bit counter, if the timer X register (extension) is never set after reset is released, setting the timer X register (extension) is not required. In this case, write the timer X register (low-order) first and the timer X register (high-order). However, once writing to the timer X register is executed, note that the value is retained to the reload latch.
In the IGBT and PWM modes, do not write “1” to the timer X register (extension). Also, when “1” is already written to the timer X register, be sure to write “0” to the register before using. Write to the following registers in the order as shown below; the compare register (high- and low-order), the timer X register (extension), the timer X register (low-order), the timer X register (high-order). It is possible to use whichever order to write to the compare regis- ter (high- and low-order). However, write both the compare register and the timer X register at the same time. (2) Read Order to Timer X
In all modes, read the following registers in the order as shown below; the timer X register (extension), the timer X register (high-order), the timer X register (low-order). When reading the timer X register (extension) is not required, read the timer X register (high-order) first and the timer X register (low- order). Read order to the compare register is not specified.
If reading to the timer X register during write operation or writing to it during read operation is performed, normal operation will not be performed. (3) Write to Timer X
When writing a value to the timer X address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. Normally, when writing a value to the timer X address, the value is set into the timer and the timer latch at the same time, because they are written at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch.
Do not switch the timer count source during timer count operation. Stop the timer count before switching it. ts Timer X count source T i m e r X P W M m o d e I G B T m o d e n m t sm t s n t s W h e n t h e T i m e r X s e t t i n g v a l u e = n a n d t h e c o m p a r e r e g i s t e r s e t t i n g v a l u e = m , t h e f o l l o w i n g P W M w a v e f o r m i s o u t p u t D u t y n m n P e r i o d n t s t s p e r i o d o f t i m e r X c o u n t s o u r c e

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (4) Set of Timer X Mode Register Set the write control bit of the timer X mode register to “1” (write to the latch only) when setting the IGBT output and PWM modes. Output waveform simultaneously reflects the contents of both regis- ters at the next underflow after writing to the timer X register (high- order). (5) Output Control Function of Timer X When using the output control function (INT1 and INT2) in the IGBT output mode, set the levels of INT1 and INT2 to “H ” in the falling edge active or to “L” in the rising edge active before switching to the IGBT output mode. (6) Note on Switch of CNTR0 Active Edge

When the CNTR0 active edge switch bits are set, at the same time, the interrupt active edge is also affected.
When the pulse width is measured, set the bit 7 of the CNTR0 ac- tive edge switch bits to “0”. Timer Y Timer Y is a 16-bit timer. The timer Y count source can be selected by setting the timer Y mode register. When f(XCIN) is selected as the count source, counting can be performed regardless of XCIN oscillation. However, when XCIN is stopped, the external pulse input from XCIN pin is counted. Four operating modes can be selected for timer Y by the timer Y mode register. Also, the real time port can be controlled. (1) Timer Mode The timer Y count source can be selected by setting the timer Y mode register. (2) Period Measurement Mode The interrupt request is generated at rising/falling edge of CNTR1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting. Except for that, this mode operates just as in the timer mode. The timer value just before the reloading at rising/falling of CNTR pin input is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input is found by CNTR1 inter- rupt. When using this mode, set the port sharing the CNTR1 pin to input mode. (3) Event Counter Mode The timer counts signals input through the CNTR1 pin. Except for that, this mode operates just as in the timer mode. When using this mode, set the port sharing the CNTR1 pin to input mode. (4) Pulse Width HL Continuously Measurement Mode The interrupt request is generated at both rising and falling edges of CNTR 1 pin input signal. Except for that, this mode operates just as in the period measurement mode. When using this mode, set the port sharing the CNTR 1 pin to input mode. I Notes on Timer Y G CNTR 1 Interrupt Active Edge Selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR1 active edge switch bit. G Timer Y Read/Write Control
When reading from/writing to timer Y, read from/write to both the high-order and low-order bytes of timer Y. When the value is read, read the high-order bytes first and the low-order bytes next. When the value is written, write the low-order bytes first and the high- order bytes next. If reading from the timer Y register during write operation or writing to it during read operation is performed, normal operation will not be performed.
When writing a value to the timer Y address to write to the latch only, the value is set into the reload latch and the timer is updated at the next underflow. Normally, when writing a value to the timer Y address, the value is set into the timer and the timer latch at the same time, because they are set to write at the same time. When writing to the latch only, if the write timing to the high-order reload latch and the underflow timing are almost the same, the value is set into the timer and the timer latch at the same time. In this time, counting is stopped during writing to the high-order reload latch.
Do not switch the timer count source during timer count operation. Stop the timer count before switching it. G Real Time Port Control When the real time port function is valid, data for the real time port is output from ports P47 and P46 each time the timer Y underflows. (However, if the real time port control bit is changed from “0” to “1” after the data for real time port is set, data is output independent of the timer Y operation.) When the data for the real time port is changed while the real time port function is valid, the changed data is output at the next underflow of timer Y. Before using this function, set the cor- responding port direction registers to output mode.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 23 Structure of Timer X, Y related registers Timer X mode register (TXM: address 002F16) Timer X operating mode bits b2 b1 b0 0 0 0 : Timer mode 0 0 1 : Pulse output mode 0 1 0 : IGBT output mode 0 1 1 : PWM mode 1 0 0 : Event counter mode 1 0 1 : Pulse width measurement mode Timer X write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Timer X count source selection bit 0 : Frequency divider output 1 : f(X CIN) Data for control of event counter window 0 : Event count enabled 1 : Event count disabled Timer X count stop bit 0 : Count operation 1 : Count stop Timer X output selection bit (P35) 0 : I/O port 1 : Timer X output b7 b0 Timer X control register (TXCON: address 0FF416) Noise filter sampling clock selection bit 0 : f(XIN)/2 1 : f(XIN)/4 External trigger delay time selection bits b2 b1 0 0 : Not delayed 0 1 : (4/f(XIN)) µs 1 0 : (8/f(XIN)) µs 1 1 : (16/f(XIN)) µs Timer X output control bit 1 (P51) 0 : Not used 1 : INT1 interrupt used Timer X output control bit 2 (P34) 0 : Not used 1 : INT2 interrupt used Timer X output edge switch bit 0 : Start at “L” output 1 : Start at “H ” output CNTR 0 active edge switch bits b7 b6 0 0 : Count at rising edge in event counter mode Falling edge active for CNTR0 interrupt Measure “H ” pulse width in pulse width measurement mode 0 1 : Count at falling edge in event counter mode Rising edge active for CNTR0 interrupt Measure “L” pulse width in pulse width measurement mode 1 0 : Count at both edges in event counter mode Both edges active for CNTR0 interrupt 1 1 : Count at both edges in event counter mode Both edges active for CNTR0 interrupt b7 b0 Timer XY frequency division selection register (PREXY: address 0FF716) Timer X frequency division selection bits b2 b1 b0 0 0 0 : 1/16 ✕ f(XIN) or 1/16 ✕ f(XCIN) 0 0 1 : 1/1 ✕ f(XIN) or 1/1 ✕ f(XCIN) 0 1 0 : 1/2 ✕ f(XIN) or 1/2 ✕ f(XCIN) 0 1 1 : 1/32 ✕ f(XIN) or 1/32 ✕ f(XCIN) 1 0 0 : 1/64 ✕ f(XIN) or 1/64 ✕ f(XCIN) 1 0 1 : 1/128 ✕ f(XIN) or 1/128 ✕ f(XCIN) 1 1 0 : 1/256 ✕ f(XIN) or 1/256 ✕ f(XCIN) 1 1 1 : 1/1024 ✕ f(XIN) or 1/1024 ✕ f(XCIN) Timer Y frequency division selection bits b5 b4 b3 0 0 0 : 1/16 ✕ f(XIN) or 1/16 ✕ f(XCIN) 0 0 1 : 1/1 ✕ f(XIN) or 1/1 ✕ f(XCIN) 0 1 0 : 1/2 ✕ f(XIN) or 1/2 ✕ f(XCIN) 0 1 1 : 1/32 ✕ f(XIN) or 1/32 ✕ f(XCIN) 1 0 0 : 1/64 ✕ f(XIN) or 1/64 ✕ f(XCIN) 1 0 1 : 1/128 ✕ f(XIN) or 1/128 ✕ f(XCIN) 1 1 0 : 1/256 ✕ f(XIN) or 1/256 ✕ f(XCIN) 1 1 1 : 1/1024 ✕ f(XIN) or 1/1024 ✕ f(XCIN) Not used (returns “0” when read) b7 b0 Timer Y mode register (TYM: address 003016) Real time port control bit 0 : Real time port function invalid 1 : Real time port functin valid 6 data for real time port P47 data for real time port Timer Y count source selection bit 0 : Frequency divider output 1 : f(XCIN) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuous measurement mode CNTR 1 active edge switch bit 0 : Count at rising edge in event counter mode Measure falling period in period measurement mode Falling edge active for CNTR1 interrupt 1 : Count at falling edge in event counter mode Measure rising period in period measurement mode Rising edge active for CNTR1 interrupt Timer Y count stop bit 0 : Count operation 1 : Count stop b7 b0 Timer Y mode register 2 (TYM2: address 0FFB16) Timer Y write control bit 0 : Write data to both timer latch and timer 1 : Write data to timer latch only Not used (returns “0” when read) b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 24 Block diagram of Timer X, Y Real time port control bit Real time port control bit Q D Latch Q D L a t c h P47 direction register P47 latch P47 data for real time port P46 direction register P46 latch P46 data for real time port Timer Y (low-order) latch (8) CNTR 1 active edge switch bit “10” P 47/ R T P1/ A N 7 P46/RTP0/AN6 P60/CNTR 1 Falling edge detection Period measurement mode T i m e r Y i n t e r r u p t r e q u e s t Pulse width HL continuous measurement mode Timer Y operating mode bits C N T R 1 i n t e r r u p t r e q u e s t Rising edge detection Count source selection bit X cI N Clock for Timer Y D a t a b u s 1 / 2 1 / 4 F r e q u e n c y d i v i d e r N o i s e f i l t e r s a m p l i n g c l o c k s e l e c t i o n b i t“1”“ T i m e r X i n t e r r u p t r e q u e s t Equal “000” “001” “010” “011” “101” P u l s e w i d t h m e a s u r e m e n t m o d e Timer X count stop bit Compare register (low-order)(8) Compare register (high-order)(8) Output selection bit P35 latch P35 direction register P35/TXOUT /(LED5) P 51/ I N T1 P 34/ I N T2/ ( L E D 4) S Q Q T R TXOUT edge switch bit S “0” “ 1 ” Q Q T S Pulse output mode C N T R 0 a c t i v e e d g e s w i t c h b i t s T i m e r X o p e r a t i n g m o d e b i t s CNTR 0 interrupt request E x t e n d l a t c h E x t e n d c o u n t e r T i m e r X w r i t e c o n t r o l b i tT i m e r i n t e r r u p t D Q L a t c h Data for control of event counter window P 37/ C N T R 0/ L E D 7) P 50/ I N T0 0 µs Delay time selection bits 4/f(XIN) “00” “01” “10” “11” 8/f(XIN) 16/f(XIN) N o i s e f i l t e r t i m e s s a m e l e v e l s j u d g m e n t I N T0 i n t e r r u p t r e q u e s t Count source selection bit XcIN C l o c k f o r T i m e r X Sy s t e m c l o c k c o n t r o l b i t s C l o c k f o r T i m e r Y XI N R e a l t i m e p o r t c o n t r o l b i t Timer Y mode register write signal Timer Y (low-order)(8) X cI N XI N F r e q u e n c y d i v i d e r IGBT output mode PWM mode Timer Y operating mode bits Timer X frequency division selection bit Timer Y frequency division selection bit B o t h e d g e s d e t e c t i o n “00” “ 0 1 ” “ 1 0 ” Edge detection TXOUT output control bit 1 TX O U T o u t p u t c o n t r o l b i t Timer X operating mode bits “0” “1” “0” “1” “0” Timer Y write control bit T i m e r Y c o u n t s t o p b i t “000” “001” “011” “100” “101” Timer X operating mode bits ”Delay circuit Timer Y (high-order) latch (8) Timer Y (high-order)(8) Timer X (low-order) latch (8) Timer X (low-order)(8) Timer X (high-order) latch (8) T i m e r X h i g h o r d e r T h e f o l l o w i n g v a l u e s c a n b e s e l e c t e d t h e c l o c k f o r T i m e r “0”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. SERIAL I/O The 38C2 group has built-in two 8-bit serial I/O. Serial I/O can be used as either clock synchronous or asynchronous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. (1) Clock Synchronous Serial I/O Mode Clock synchronous serial I/O mode can be selected by setting the serial I/O mode selection bit of the serial I/O control register to “1”. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB. Fig. 25 Block diagram of clock synchronous serial I/O Fig. 26 Operation of clock synchronous serial I/O function F/F P56/SCLK1 [P31/SCLK2 ] Serial I/O status register Serial I/O control register P57/SRDY1 [P30/SRDY2 ] P54/RXD 1 [P33/RXD 2] P55/TXD 1 [P32/TXD 2] f(XIN) Receive buffer register Address 001C16 [Address 001E16] Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 0FE216 [Address 0FE516] BRG count source selection bit Clock control circuitFalling-edge detector Transmit buffer register Data bus Address 001C16 [Address 001E16] Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001D16 [Address 001F16] Data bus Address 0FE016 [Address 0FE316] Transmit shift register (f(XCIN) in low-speed mode) [ ] : For Serial I/O2 D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD Write pulse to receive/transmit buffer register Overrun error (OE) detection Notes 1: As the transmit interrupt (TI), which can be selected, either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O control register. 2: If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3: The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (2) Asynchronous Serial I/O (UART) Mode Clock asynchronous serial I/O mode (UART) can be selected by clear- ing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift regis- ter cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the re- ceive buffer register. The transmit buffer register can also hold the next data to be trans- mitted, and the receive buffer register can hold a character while the next character is being received. Fig. 27 Block diagram of UART serial I/O f(XIN) OE PE FE Data bus Receive buffer register Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) ST/SP/PA generator Transmit buffer register Data bus Transmit shift register Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) ST detector SP detector UART control register Address 0FE116 [Address 0FE416] Character length selection bit BRG count source selection bit Transmit interrupt source selection bit Serial I/O synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O control register Serial I/O status register (f(XCIN) in low-speed mode) P56/SCLK1 [P31/SCLK2 ] P54/RXD 1 [P33/RXD 2] P55/TXD 1 [P32/TXD 2] Address 001C16 [Address 001E16] Address 0FE216 [Address 0FE516] Address 001C16 [Address 001E16] Address 001D16 [Address 001F16] Address 0FE016 [Address 0FE316] [ ] : For Serial I/O2 Fig. 28 Operation of UART serial I/O function TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes “1” (at 1st stop bit, during reception). 2: As the transmit interrupt (TI), when either the TBE or TSC flag becomes “1,” can be selected to occur depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes “1.” 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer read signal

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. [Transmit Buffer Register/Receive Buffer Reg- ister (TB/RB)] The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. [Serial I/O Status Register (SIO1STS, SIO2STS)] The read-only serial I/O status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer register is read. If there is an error, it is detected at the same time that data is trans- ferred from the receive shift register to the receive buffer register, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the serial I/O control register) also clears all the status flags, including the error flags. All bits of the serial I/O status register are initialized to “0” at reset, but if the transmit enable bit (bit 4) of the serial I/O control register has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. [Serial I/O Control Register (SIO1CON, SIO2CON)] The serial I/O control register consists of eight control bits for the serial I/O function. [UART Control Register (UART1CON, UART2CON)] The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer and one bit (bit 4) which is always valid and sets the output structure of the P5 5/TXD 1 [P32/TxD2] pin. [Baud Rate Generator (BRG1, BRG2)] The baud rate generator determines the baud rate for serial transfer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate generator.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 29 Structure of serial I/O related registers b7b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns “1” when read) Serial I/O status register Serial I/O control register b0 b0 BRG count source selection bit (CSS) 0: f(XIN) (f(XCIN) in low-speed mode) 1: f(XIN)/4 (f(XCIN)/4 in low-speed mode) Serial I/O synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected. BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected. External clock input divided by 16 when UART is selected. S RDY output enable bit (SRDY) 0: P57 [P30] pin operates as ordinary I/O pin 1: P57 [P30] pin operates as SRDY output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O mode selection bit (SIOM) 0: Clock asynchronous (UART) serial I/O 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P5 4 [P30] to P57 [P33] operate as ordinary I/O pins) 1: Serial I/O enabled (pins P5 4 [P30] to P57 [P33] operate as serial I/O pins) b7 UART control register Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD1 [P32/TxD2] P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return “1” when read) (SIO1STS : address 001D16) [SIO2STS : address 001F16] (SIO1CON : address 0FE016) [SIO2CON : address 0FE316] (UART1CON : address 0FE116) [UART2CON : address 0FE416] ( ) : For Serial I/O1 [ ] : For Serial I/O2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. A-D CONVERTER The 38C2 group has a 10-bit A-D converter. The A-D converter per- forms successive approximation conversion. [A-D Conversion Register (ADL, ADH)] One of these registers is a high-order register, and the other is a low- order register. The high-order 8 bits of a conversion result is stored in the A-D conversion register (high-order) (address 001B16), and the low-order 2 bits of the same result are stored in bit 7 and bit 6 of the A-D conversion register (low-order) (address 001A 16). During A-D conversion, do not read these registers. Also, the connection between the resistor ladder and reference volt- age input pin (V REF ) can be controlled by the VREF input switch bit (bit 0 of address 001A16). When “1” is written to this bit, the resistor ladder is always connected to VREF . When “0” is written to this bit, the resistor ladder is disconnected from VREF except during the A-D conversion. [A-D Control Register (ADCON)] This register controls A-D converter. Bits 2 to 0 are analog input pin selection bits. Bit 3 is an AD conversion completion bit and “0” during A- D conversion. This bit is set to “1” upon completion of A-D conversion. A-D conversion is started by setting “0” in this bit. [Comparison Voltage Generator] The comparison voltage generator divides the voltage between AVSS and VREF , and outputs the divided voltages. [Channel Selector] The channel selector selects one of the input ports P47/AN7–P40/ AN 0 and inputs it to the comparator. [Comparator and Control Circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage and stores the result in the A-D conversion register. When an A-D conversion is completed, the con- trol circuit sets the AD conversion completion bit and the AD conver- sion interrupt request bit to “1.” Fig. 31 Block diagram of A-D converter Fig. 30 Structure of A-D control register Data bus AV SS A-D interrupt request b7 b0 P40/OOUT0 /AN0 P41/OOUT1 /AN1 P42/AN2 P43/AN3 P44/AN4 P45/AN5 P46/AN6 P47/AN7 A-D control register Channel selector Comparator A-D control circuit A-D conversion register (H)A-D conversion register (L) (Address 001B16) (Address 001A16) Resistor ladder VREF Analog input pin selection bits b2 b1 b0 0 0 0: P4 0/AN0 0 0 1: P4 1/AN1 0 1 0: P4 2/AN2 0 1 1: P4 3/AN3 1 0 0: P4 4/AN4 1 0 1: P4 5/AN5 1 1 0: P4 6/AN6 1 1 1: P4 7/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed AD conversion clock selection bits b5 b4 0 0: Frequency not divided 0 1: Frequency divided by 2 1 0: Frequency divided by 4 1 1: Frequency divided by 8 10-bit or 8-bit conversion switch bit 0: 10-bit AD 1: 8-bit AD Booster selection bit 0: Booster not used 1: Booster used A-D control register (ADCON: address 001916) b7 b0 10-bit reading (Read address 001B16 before 001A16) A-D conversion register 1 (Address 001B16) A-D conversion register 2 (Address 001A16) 8-bit reading (Read only address 001B16) (Address 001B16) b7 b0 * VREF input switch bit b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 b9 b8 b7 b6 b5 b4 b3 b2 b7 b0 (high-order) (low-order) Note : The bit 5 to bit 1 of address 001A16 becomes “0” at reading. Also, bit 0 is undefined at reading. 1: ON 0: ON only during A-D conversion

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. LCD DRIVE CONTROL CIRCUIT The 38C2 group has the built-in Liquid Crystal Display (LCD) drive control circuit consisting of the following.

LCD display RAM
Segment output disable register
LCD mode register
Selector
Timing controller
Common driver
Segment driver
Bias control circuit A maximum of 24 segment output pins and 4 common output pins can be used. Up to 96 pixels can be controlled for an LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, the Fig. 32 Structure of LCD related registers segment output disable register, and the LCD display RAM, the LCD drive control circuit starts reading the display data automatically, per- forms the bias control and the duty ratio control, and displays the data on the LCD panel. Table 8 Maximum number of display pixels at each duty ratio Duty ratio Maximum number of display pixels 48 dots or 8 segment LCD 6 digits 72 dots or 8 segment LCD 9 digits 96 dots or 8 segment LCD 12 digits Segment output disable bit 0 0 : Segment output SEG0 1 : Output port P00 Segment output disable bit 1 0 : Segment output SEG 1 : Output port P01 Segment output disable bit 2 0 : Segment output SEG 1 : Output port P02 Segment output disable bit 3 0 : Segment output SEG 1 : Output port P03 Segment output disable bit 4 0 : Segment output SEG 1 : Output port P04 Segment output disable bit 5 0 : Segment output SEG 1 : Output port P05 Segment output disable bit 6 0 : Segment output SEG 1 : Output port P06 Segment output disable bit 7 0 : Segment output SEG 1 : Output port P07 Segment output disable register 0 (SEG0 : address 0FF8 16) b7 b0 LCD mode register (LM : address 003916) Duty ratio selection bits b1 b0 0 0 : Not used 0 1 : 2 (use COM0,COM 1) 1 0 : 3 (use COM0–COM 2) 1 1 : 4 (use COM0–COM 3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON LCD drive timing selection bit 0 : Type A 1 : Type B LCD circuit divider division ratio selection bits b6 b5 0 0 : Clock input 0 1 : 2 division of clock input 1 0 : 4 division of clock input 1 1 : 8 division of clock input LCDCK count source selection bit (Note) 0 : f(X CIN)/32 1 : f(XIN)/8192 (f(XCIN)/8192 in low-speed mode) Note : LCDCK is a clock for an LCD timing controller. b7 b0 Segment output disable bit 8 0 : Segment output SEG8 1 : Output port P10 Segment output disable bit 9 0 : Segment output SEG 1 : Output port P11 Segment output disable bit 10 0 : Segment output SEG 1 : Output port P12 Segment output disable bit 11 0 : Segment output SEG 1 : Output port P13 Segment output disable bit 12 0 : Segment output SEG 1 : Output port P14 Segment output disable bit 13 0 : Segment output SEG 1 : Output port P15 Segment output disable bit 14 0 : Segment output SEG 1 : Output port P16 Segment output disable bit 15 0 : Segment output SEG 1 : Output port P17 Segment output disable register 1 (SEG1 : address 0FF9 16) b7 b0 Segment output disable bit 16 0 : Output port P2 1 : Segment output SEG16 Segment output disable bit 17 0 : Output port P2 1 : Segment output SEG17 Segment output disable bit 18 0 : Output port P2 1 : Segment output SEG18 Segment output disable bit 19 0 : Output port P2 1 : Segment output SEG19 Segment output disable bit 20 0 : Output port P2 1 : Segment output SEG20 Segment output disable bit 21 0 : Output port P2 1 : Segment output SEG21 Segment output disable bit 22 0 : Output port P2 1 : Segment output SEG22 Segment output disable bit 23 0 : Output port P2 1 : Segment output SEG23 Segment output disable register 2 (SEG2 : address 0FFA 16) b7 b0 Note : Only pins set to output ports by the direction register can be controlled to switch to output ports or segment outputs by the segment output disable register.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 33 Block diagram of LCD controller/driver f ( XC I f ( XI L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t L e v e l s h i f t C O M C O M C O M C O M V S S P 27/ S E G V V L P 26/ S E G V P 03/ S E G P 02/ S E G P 01/ S E G P 00/ S E G P 20/ S E G “ 0 “ 1 L C D C K P 27/ V L2 S E G P 26/ V L1 S E G D a t a b u s T i m i n g c o n t r o l l e r L C D d i v i d e r ( f ( XC I i n l o w s p e e d m o d e C o m m o n d r i v e r B i a s c o n t r o l A d d r e s s A d d r e s s L C D C K c o u n t s o u r c e s e l e c t i o n b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s B i a s c o n t r o l b i t L C D e n a b l e b i t D u t y r a t i o s e l e c t i o n b i t s S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r L C D d i s p l a y R A M A d d r e s s C S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r S e l e c t o r S e l e c t o r S e g m e n t d r i v e r S e g m e n t d r i v e r L C D p o w e r c o n t r o l r e g i s t e r

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Duty ratio 4Voltage value V L3=VLCD VL2=2/3 VLCD VL1=1/3 VLCD VL3=VLCD VL2=VL1=1/2 VLCD Bias Control and Applied Voltage to LCD Power Input Pins When the voltage is applied from the LCD power input pins (VL1– VL3), set the VL pin input selection bit (bit 5 of the LCD power control register) and VL3 connection bit (bit 6 of LCD power control register) to “1”, apply the voltage value shown in Table 9 according to the bias value. In this case, SEG22 pin and SEG23 pin cannot be used. Select a bias value by the bias control bit (bit 2 of the LCD mode register). Fig. 34 Example of circuit at each bias (at external power input) Table 9 Bias control and applied voltage to VL1–VL3 Bias value 1/3 bias 1/2 bias Note : VLCD is the maximum value of supplied voltage for the LCD panel. Table 10 Duty ratio control and common pins used Note: Unused common pin outputs the unselected waveform. Common pins used COM 0, COM1 COM 0–COM 2 COM 0–COM 3 Bit 1 Bit 0 Duty ratio selection bit Common Pin and Duty Ratio Control The common pins (COM0–COM 3) to be used are determined by duty ratio. Select duty ratio by the duty ratio selection bits (bits 0 and 1 of the LCD mode register). When reset is released, V CC voltage is out- put from the common pin. Segment Signal Output Pin The segment signal output pins (SEG0–SEG 23) are shared with ports P0–P2. When these pins are used as the segment signal output pins, set the direction registers of the corresponding pins to “1”, and clear the segment output disable register to “0”. Also, these pins are set to the input port after reset, the VCC voltage is output by the pull-up resistor. VL3 VL2 VL1 R R4 = R5 C o n t r a s t a d j u s t 1/2 bias VL VL VL C o n t r a s t a d j u s t R R R R b i a s

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. LCD Power Circuit The LCD power circuit has the dividing resistor for LCD power which can be connected/disconnected with the LCD power control register. Fig. 35 Structure of LCD power control register Dividing resistor for LCD power control bit (LCDRON) 0 : Internal dividing resistor disconnected from LCD power circuit 1 : Internal dividing resistor connected to LCD power circuit Dividing resistor for LCD power selection bits (RSEL) b3 b2 1 0 : Larger resistor 0 1 : 0 0 : 1 1 : Smaller resistor Not used (return “0” when read) (Do not write to “1”) VL pin input selection bit (VLSEL) 0 : Input invalid 1 : VL input function valid V L3 connection bit 0 : Connect LCD internal VL3 to VCC 1 : Connect LCD internal VL3 to VL3 pin Not used (return “0” when read) (Do not write to “1”) LCD power control register (VLCON : address 003816) b7 b0 Fig. 36 VL block diagram VL P 27/ S E G 2 VL P 26/ S E G 2 VL Vcc L C D m o d e r e g i s t e r b i t L C D p o w e r c o n t r o l r e g i s t e r b i t LCD power control register (bit 0) D i v i d i n g r e s i s t o r f o r L C D p o w e r L C D p o w e r c o n t r o l r e g i s t e r b i t s a n d LCD power control register (bit 6) L C D i n t e r n a l VL L C D i n t e r n a l VL L C D i n t e r n a l VL

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. (frequency of count source for LCDCK) (divider division ratio for LCD)f(LCDCK)= f(LCDCK) duty ratioFrame frequency= Fig. 37 LCD display RAM map LCD Display RAM The 12-byte area of address 004016 to 004B16 is the designated RAM for the LCD display. When “1” is written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing For the LCD drive timing, type A or type B can be selected. The LCD drive timing is selected by the timing selection bit (bit 4 of LCD mode register). Type A is selected by setting the LCD drive timing selection bit to “0”, type B is selected by setting the bit to “1”. Type A is selected after reset. The LCDCK timing frequency (LCD drive timing) is generated inter- nally and the frame frequency can be determined with the following equation; I Note (1) When the STP instruction is executed, the following bits are cleared to “0”;

LCD enable bit (bit 3 of LCD mode register)
Bits other than bit 6 of the LCD power control register. (2) When the voltage is applied to VL1 to VL3 by using the external resistor, write “102” to dividing resistor for LCD power selection bits (RSEL) of the LCD power control register (address 3816). C O M 3 C O M 2 C O M 1 C O M 0 Bit Address 7 6543 21 0 004016 004116 004216 004316 004416 004516 004616 004716 004816 004916 004A16 004B16 SEG 1 SEG 3 SEG 5 SEG 7 SEG 9 SEG 11 SEG 13 SEG 15 SEG 17 SEG 19 SEG 21 SEG 23 SEG 0 SEG 2 SEG 4 SEG 6 SEG 8 SEG 10 SEG 12 SEG 14 SEG 16 SEG 18 SEG 20 SEG 22 C O M 3 C O M 2 C O M 1 C O M 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 38 LCD drive waveform (1/2 bias, type A) 1 / 4 d u t y Voltage level VL3 VL2=VL1 VSS VL3 VSS C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 O F FO N O F FO N C O M 3 COM 2 COM 1 COM 0 C O M 3 COM 2 COM 1 COM 0 1 / 3 d u t y VL3 VL2=VL1 VSS VL3 VSS OFFO N O NO F F O NO F F 1 / 2 d u t y C O M 0 C O M 1 C O M 2 S E G 0 COM 0 C O M 1 S E G 0 VL3 VL2=VL1 VSS VL3 VSS OFFO N O F FO N OFFO N OFFO N C O M 0 C O M 2 COM 1 C O M 0 C O M 2 COM 1 COM 0 C O M 2 C O M 1 C O M 0 COM 1 COM 0 C O M 1 COM 0 COM 1 C O M 0 I n t e r n a l s i g n a l L C D C K t i m i n g LCD LCD L C D

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 39 LCD drive waveform (1/3 bias, type A) VL VSS C O M 0 C O M 1 C O M 2 C O M 3 SEG 0 C O M 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 C O M 0 C O M 1 COM 2 S E G 0 C O M 0 C O M 1 S E G 0 VL VL VS S VL VL VL VSS VL VL VSS VL VL VS S VL1 VL VS S COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 C O M 1 COM 0 COM 1 COM 0 C O M 1 COM 0 COM 1 COM 0 1 / 4 d u t y Voltage level O F FO N O F FO N 1 / 3 d u t y OFFO NO NO F F O NO F F 1/2 duty OFFO NO F FON O F FO NO F F O N I n t e r n a l s i g n a l L C D C K t i m i n g LCD L C D L C D

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 40 LCD drive waveform (1/2 bias, type B) C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 C O M 0 COM 1 C O M 2 S E G 0 C O M 0 C O M 1 S E G 0 VL3 VL2=VL1 VSS C O M 0 C O M 2 C O M 1 COM 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 COM 1 C O M 0 C O M 1 COM 0 C O M 1 C O M 0 1 frame 1 f r a m e 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame VL3 VSS VL3 VSS VL3 VSS VL3 VL2=VL1 VSS VL3 VL2=VL1 VSS 1/4 duty V o l t a g e l e v e l OFF ON OFF ON 1 / 3 d u t y O F FON O NO F FO N O F F 1 / 2 d u t y O F FO NO F FO NO F FO NO F F ON I n t e r n a l s i g n a l L C D C K t i m i n g L C D L C D LCD

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 41 LCD drive waveform (1/3 bias, type B) C O M 0 C O M 1 C O M 2 C O M 3 SEG 0 C O M 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 C O M 0 C O M 1 COM 2 SEG 0 C O M 0 C O M 1 SEG 0 VL VL VS S VL VL VL VSS VL VL VL VS S VL1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 C O M 1 COM 0 COM 1 COM 0 C O M 1 C O M 0 COM 1 C O M 0 VL VL VSS VL1 VL3 VL VSS VL VL VL VS S VL1 1 f r a m e 1 f r a m e 1 frame 1 frame 1 frame 1 frame 1 frame 1 frame 1 / 4 d u t y V o l t a g e l e v e l OFF ON OFF ON 1 / 3 d u t y O F FO NO NO F FO NO F F 1 / 2 d u t y O F FO NO F FON OFF ON O F FO N I n t e r n a l s i g n a l L C D C K t i m i n g L C D LCD L C D

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, because of a software run-away). The watchdog timer consists of an 8-bit counter. Initial Value of Watchdog Timer At reset or writing to the watchdog timer control register, each watch- dog timer is set to “FF 16.” Instructions such as STA, LDM and CLB to generate the write signals can be used. The written data in bits 0 to 5 are not valid, and the above values are set. Standard Operation of Watchdog Timer The watchdog timer is in the stop state at reset and the watchdog timer starts to count down by writing an optional value in the watch- dog timer control register. An internal reset occurs at an underflow of the watchdog timer. Then, reset is released after the reset release time is elapsed, the program starts from the reset vector address. Normally, writing to the watchdog timer control register before an underflow of the watchdog timer is programmed. If writing to the watch- dog control register is not executed, the watchdog timer does not operate. Fig. 44 Timing diagram of reset output When reading the watchdog timer control register is executed, the contents of the high-order 6-bit counter and the STP instruction dis- able bit (bit 6), and the count source selection bit (bit 7) are read out. When the STP instruction disable bit is “0”, the STP instruction is valid. The STP instruction is disabled by writing to “1” to this bit. In this time, when the STP instruction is executed, it is handled as the undefined instruction, the internal reset occurs. This bit cannot be cleared to “0” by program. This bit is “0” after reset. The time until the underflow of the watchdog timer control register after writing to the watchdog timer control register is executed is as follows (when the bit 7 of the watchdog timer control register is “0”) ;

at through, frequency/2/4/8 mode (f(X IN)) = 8 MHz): 32.768 ms
at low-speed mode (f(XCIN) = 32 KHz): 8.19s I Note The watchdog timer continues to count even during the wait time set by timer 1 and timer 2 to release the stop state and in the wait mode. Accordingly, do not underflow the watchdog timer in this time. Fig. 42 Block diagram of Watchdog timer Fig. 43 Structure of Watchdog timer control register STP instruction disable bit 0: STP instruction enabled 1: STP instruction disabled Watchdog timer count source selection bit 0: 1/1024 of system clock 1: 1/4 of system clock Watchdog timer H (for read-out of high-order 6 bit) “FF16” is set to watchdog timer by writing to these bits. Watchdog timer control register (WDTCON : address 003716) I n t e r n a l r e s e t s i g n a l Watchdog timer detected ≈ 32msec (at f(XIN)=8MH Z) f XI N XIN XC I N Sy s t e m c l o c k c o n t r o l b i t b i t U n d e f i n e d i n s t r u c t i o n R e s e t R E S E TI N Wait until reset release D a t a b u s W a t c h d o g t i m e r H c o u n t s o u r c e s e l e c t i o n b i t R e s e t c i r c u i t S T P i n s t r u c t i o n d i s a b l e b i t Watchdog timer H (6) Internal resetS T P i n s t r u c t i o n Watchdog timer L (2) “ F F1 6” i s s e t w h e n w a t c h d o g t i m e r c o n t r o l r e g i s t e r i s w r i t t e n t o “1” “0” “0” “1”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. CLOCK OUTPUT FUNCTION A system clock φ can be output from I/O port P36.The triple function of I/O port, timer 2 output function and system clock φ output function is performed by the clock output control register (address 001816) and the timer 2 output selection bit of the timer 12 mode register (address 002516). In order to output a system clock φ from I/O port P36, set the timer 2 output selection bit and bit 0 of the clock output control register to “1”. When the clock output function is selected, a clock is output while the direction register of port P3 6 is set to the output mode. P36 is switched to the port output or the output (timer 2 output and the clock output) except port at the cycle after the timer 2 output control bit is switched. Fig. 46 Block diagram of Clock output function Fig. 45 Structure of clock output control register Not used (returns “0” when read) P36 clock output control bit 0: Timer 2 output 1: System clock φ output Clock output control register (CKOUT : address 001816) T i m e r l a t c h T i m e r ) 1 Q Q S T O U T o u t p u t e d g e s w i t c h b i t T i m e r o u t p u t c o n t r o l b i t P l a t c h T i m e r o u t p u t s e l e c t i o n b i t P d i r e c t i o n r e g i s t e r P 36/ O U T/φ S y s t e m c l o c k φ P c l o c k o u t p u t c o n t r o l b i t b b T i m e r m o d e r e g i s t e r a d d r e s s T M T i m e r o u t p u t s e l e c t i o n b i t I O p o r t T i m e r o u t p u t

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H ” level (the power source voltage should be between VCC (min.) and 5.5 V, and the quartz-crystal oscillator should be stable), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage meets VIL spec. when a power source voltage passes VCC (min.). Fig. 48 Reset sequence Fig. 47 Reset circuit example VIL spec. Poweron VCCRESET VCCRESET Power source voltage detection circuit Power source voltage Reset input voltage RESET Internal reset Address Data SYNC φ XIN FFFC FFFD AD H, AD L AD L ??? ? XIN : about 8000 cycles Note Reset address from vector table 1: The frequency relation of f(XIN) and f(φ) is f(XIN) = 8 • f(φ). 2: The question marks (?) indicate an undefined state that depends on the previous state. AD H

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 49 Internal status at reset FF16 FF16 0016 002A16 0 0 2 B1 0 0 2 C 1 0 0 3 71 0 0 3 81 0 0 3 A1 X: Not fixed Since the initial values for other than above mentioned registers and RAM contents are indefinite at reset, they must be set. A d d r e s s R e g i s t e r c o n t e n t s A d d r e s s R e g i s t e r c o n t e n t s 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 00160 0 0 01 0 0 0 11 0 0 0 21 0 0 0 41 0 0 0 51 0 0 0 61 0 0 0 81 0 0 0 91 000A16 0 0 0 B1 0 0 0 C 1 0 0 0 D 1 001816 0 0 1 91 001D 16 0 0 1 F1 002016 0 0 2 11 002216 0 0 2 31 002416 002516 0 0 2 81 C o m p a r e r e g i s t e r ( l o w - o r d e r ) P o r t P 0 P o r t P 0 d i r e c t i o n r e g i s t e r P o r t P 1 P o r t P 2 P o r t P 2 d i r e c t i o n r e g i s t e r P o r t P 3 P o r t P 4 P o r t P 4 d i r e c t i o n r e g i s t e r Port P5 P o r t P 5 d i r e c t i o n r e g i s t e r P o r t P 6 P o r t P 6 d i r e c t i o n r e g i s t e r Clock output control register A-D control register S e r i a l I / O 1 s t a t u s r e g i s t e r Timer 2 T i m e r 3 Timer 4 PWM01 register T i m e r 1 2 m o d e r e g i s t e r Timer 34 mode register C o m p a r e r e g i s t e r ( h i g h - o r d e r ) T i m e r X ( l o w - o r d e r ) Timer X (high-order) (1) (2) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) 0016 002916 T i m e r X ( e x t e n s i o n )(30) ( 3 2 ) (33) ( 3 5 ) ( 3 6 ) ( 3 7 ) ( 3 8 ) T i m e r Y ( l o w - o r d e r ) T i m e r Y ( h i g h - o r d e r ) T i m e r X m o d e r e g i s t e r W a t c h d o g t i m e r c o n t r o l r e g i s t e r L C D p o w e r c o n t r o l r e g i s t e r L C D m o d e r e g i s t e r I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r 0 01 0016 0016 0 0 3 B1 0 0 3 C 1 0 0 3 F1

0 F E 11

0 F E 31

( 3 9 ) ( 4 0 ) ( 4 3 ) (44) ( 4 5 ) ( 4 6 ) (47) CPU mode register I n t e r r u p t r e q u e s t r e g i s t e r 1 I n t e r r u p t r e q u e s t r e g i s t e r 2 Interrupt control register 1 I n t e r r u p t c o n t r o l r e g i s t e r 2 0 01 0 01 0 01 Serial I/O2 status register T i m e r 1 ( 3 1 ) FFFC 16 contents (PS) ( P C H ) ( P C L) P r o g r a m c o u n t e r P r o c e s s o r s t a t u s r e g i s t e r F F F D 1 6 c o n t e n t s 003916 0816 FF16 0116 FF16 FF16 0016 0016 0016 00160 0 0 31 P o r t P 1 d i r e c t i o n r e g i s t e r (4) 0 0 3 E1 ( 4 1 ) ( 4 2 ) 0 01 0 01 0 0 3 D 1 0 01 0016 0016

0 F F 01

0 F F 11

0 F F 21

0 F F 31

( 4 8 ) (49) (50) (51) 0 01 0 01

60 F F 41

( 5 2 ) (53) (54) 0016 0 01 0 01 F F1

0 F F 71

0 F F 81

0 F F 91

( 5 5 ) (56) ( 5 7 ) F F1 F F1 60FFA 16 0FFB 16

0 F F E1

(58) ( 5 9 ) (60) 0 01 (61) ( 6 2 ) P o r t P 3 d i r e c t i o n r e g i s t e r 0 0 0 71 0 0 2 61 0 0 2 D 1 0 0 2 E1 002F16 100000 0 0 100000 0 0 0016( 3 4 )Timer Y mode register 0 0 3 01 S e r i a l I / O 1 c o n t r o l r e g i s t e r U A R T1 c o n t r o l r e g i s t e r S e r i a l I / O 2 c o n t r o l r e g i s t e r U A R T 2 c o n t r o l r e g i s t e r O s c i l l a t i o n o u t p u t c o n t r o l r e g i s t e r PULL register K e y i n p u t c o n t r o l r e g i s t e r Timer 1234 mode register T i m e r X c o n t r o l r e g i s t e r T i m e r 1 2 f r e q u e n c y d i v i s i o n s e l e c t i o n r e g i s t e r T i m e r 3 4 f r e q u e n c y d i v i s i o n s e l e c t i o n r e g i s t e r Timer XY frequency division selection register S e g m e n t o u t p u t d i s a b l e r e g i s t e r 0 S e g m e n t o u t p u t d i s a b l e r e g i s t e r 1 Segment output disable register 2 T i m e r Y m o d e r e g i s t e r 2 F l a s h m e m o r y c o n t r o l r e g i s t e r 0011 11 1 1 0100 10 0 0 0 01 111000 0 0 111000 0 0 1✕✕✕ 0000

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. CLOCK GENERATING CIRCUIT The 38C2 group has two built-in oscillation circuits; main clock XIN– XOUT and sub-clock XCIN–XCOUT . An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer’s recommended values. No external resistor is needed between XIN and XOUT since a feedback resistor exists on-chip. How- ever, an external feedback resistor is needed between XCIN and XCOUT . When the clock signal is supplied from external for the main clock, input the signal to X IN pin and input the inverted-phase signal of XIN to XOUT pin by the external inverter. When the clock signal is supplied from external for the sub-clock, input the signal to X CIN and leave XCOUT open. Immediately after power on, only the XIN oscillation circuit starts os- cillating. Frequency Control (1) Frequency/8 Mode The system clock φ is the frequency of XIN divided by 8. After reset is released, this mode is selected. (2) Frequency/4 Mode The system clock φ is the frequency of XIN divided by 4. (3) Frequency/2 Mode The system clock φ is the frequency of XIN divided by 2. (4) Through Mode The system clock φ is the frequency of XIN. (5) Low-speed Mode The system clock φ is the frequency of XCIN divided by 2. In the low- speed mode, the low-power dissipation operation can be performed when the main clock X IN is stopped by setting the bit 7 of the CPU mode register to “0”. In this case, when main clock XIN oscillation is restarted, generate the wait time until the oscillation is stable by pro- gram after the bit 7 of the CPU mode register is set to “1”. Fig. 50 Ceramic resonator circuit Fig. 51 External clock input circuit XO U T C I N C O U TC C I N C C O U T R f c XC I N XC O U T XI N XC I N XC O U T XI N XO U T E x t e r n a l o s c i l l a t i o n c i r c u i t VC C VS S O p e n VC C VS S E x t e r n a l o s c i l l a t i o n c i r c u i t o r E x t e r n a l p u l s e I Notes on Clock Generating Circuit If you switch the mode between through, frequency/2/4, or 8 and low-speed, stabilize both XIN and XCIN oscillations. The sufficient time is required for the sub-clock to stabilize, especially immediately after power on and at returning from stop mode. When switching the mode, set the frequency on condition that f(X IN) > 3f(XCIN). Oscillation Control (1) Stop Mode If the STP instruction is executed, the system clock φ stops at an “H ” level, and main clock and sub-clock oscillators stop. In this time, values set previously to timer 1 latch and timer 2 latch are loaded automatically to timer 1 and timer 2. Set the values to generate the wait time required for oscillation stabilization to timer 1 latch and timer 2 latch (low-order 8 bits of timer 1 and high-order 8 bits of timer 2) before the STP instruction. The frequency divider for timer 1 is used for the timer 1 count source, and the output of timer 1 is forcibly connected to timer 2. In this time, bits 0 to 5 of the timer 12 mode register are cleared to “0”. The values of the timer 12 frequency divider selection register are not changed. Set the interrupt enable bits of the timer 1 and timer 2 to disabled (“0”) before executing the STP instruction. Oscillator restarts When reset occurs or an interrupt request is re- ceived, but the system clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabi- lize. (2) Wait Mode If the WIT instruction is executed, the system clock φ stops at an “H ” level. The states of XIN and XCIN are the same as the state before executing the WIT instruction. The system clock φ restarts at reset or when an interrupt is received. Since the oscillator does not stop, nor- mal operation can be started immediately after the clock is restarted.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 52 Clock generating circuit block diagram S R QS R Q S R Q XI N XO U T 1 / 21 / 21 / 2 P61/XCIN P 62/ XC O U T T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t s Through mode “01” “00” “ 1 1 ” “ 0 1 ” “ 0 0 ” “00” “ 1 0 ” T i m e r 2 c o u n t s o u r c e s e l e c t i o n b i t s “ 0 0 , 1 0 , 1 1 ” “01” “01,10,11” “ 0 0 ” “10” “ 0 0 , 1 0 ” “ 0 0 , 1 0 ” “ 0 1 , 1 1 ” “01,11” WIT instruction System clock φ STP instruction T i m e r 2T i m e r 1 I n t e r r u p t r e q u e s t Reset System clock control bits Main clock division ratio selection bits Interrupt disable flag I STP instruction S y s t e m c l o c k c o n t r o l b i t s System clock control bits S y s t e m c l o c k c o n t r o l b i t s F r e q u e n c y d i v i d e r f o r T i m e r Frequency/8 mode Frequency/4 mode F r e q u e n c y / 2 m o d e “00” “ 0 0 , 1 0 , 1 1 ”“ 0 1 ” System clock control bits

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 53 State transitions of system clock XI N o s c i l l a t i o n , XC I N s t o p C M 7= C M 6= S y s t e m c l o c k φ : f ( XI N ) C M 5= M 4= T h r o u g h m o d e F r e q u e n c y / 2 m o d e S y s t e m c l o c k φ : f ( XI N ) / 2 C M 5= M 4= CM 7=“0” CM 6=“1” L o w - s p e e d m o d e S y s t e m c l o c k φ f XC I N ) XI N s t o p , XC I N o s c i l l a t i o n C M 7= C M 6= L o w - p o w e r d i s s i p a t i o n m o d e S y s t e m c l o c k φ f XC I N ) CM 7=“1” CM 7=“0” CM 6=“0” S y s t e m c l o c k = M a i n c l o c k f ( XI N ) R e s e t CM 5 CM 4 : Main clock division ratio selection bits 00: XIN/8 (frequency/8) 01: XIN/4 (frequency/4) 10: XIN/2 (frequency/2) 11: XIN (through mode) CM 7 CM 6 : System clock control bits 00: XIN stop, XCIN oscillation, system clock = XCIN 01: XIN oscillation, XCIN stop, system clock = XIN 10: XIN oscillation, XCIN oscillation, system clock = XCIN 11: XIN oscillation, XCIN oscillation, system clock = XIN CPU mode register (CPUM : address 003B16) b7 b4 1: When the mode is switched from through or frequency/2/4/8 to the low-speed mode, or the opposite is performed, change CM7 at first, and then, change CM6 after the oscillation of the changed mode is stabilized. 2: The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is ended. 3: Timer and LCD operate in the wait mode. 4: When the stop mode is ended, a delay time can be set by connecting timer 1 and timer 2. N o t e s Frequency/4 mode F r e q u e n c y / 8 m o d e S y s t e m c l o c k φ : f ( XI N ) / 4 C M 5= M 4= S y s t e m c l o c k φ : f ( XI N ) / 8 C M 5= M 4= CM 7=“1” XIN oscillation, XCIN oscillation CM 7=1, CM6=1 T h r o u g h m o d e F r e q u e n c y / 2 m o d e Frequency/4 mode F r e q u e n c y / 8 m o d e S y s t e m c l o c k φ : f ( XI N ) C M 5= M 4= System clock φ : f(XIN)/2 CM 5=1 CM 4=0 S y s t e m c l o c k φ : f ( XI N ) / 4 C M 5= M 4= System clock φ : f(XIN)/8 CM 5=0 CM 4=0 S y s t e m c l o c k S u b c l o c k f XC I N ) XI N o s c i l l a t i o n , XC I N o s c i l l a t i o n C M 7= C M 6=

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Oscillation External Output Function The 38C2 group has the oscillation external output function to output the rectangular waveform of the clock obtained by the oscillation cir- cuits from P4 1 and P40. In order to validate the oscillation external output function, set P40 or P41, or both to the output mode (set the corresponding direction reg- ister to “1”). The level of the XCOUT external output signal becomes “H ” by the P40/P41 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0FF016) in the following states;

the function to output the signal from the XCOUT pin externally is selected
the sub-clock (XCIN–XCOUT ) is in the oscillating or stop mode. Likewise, the level of the XOUT external output signal becomes “H ” by the P40/P41 oscillation output control bits (bits 0 and 1) of the oscillation output control register (address 0FF016) in the following states;
the function to output the signal from the XOUT pin externally is selected
the main clock (XIN–XOUT ) is in the oscillating or stop mode. Fig. 55 Block diagram of Oscillation output function Fig. 54 Structure of oscillation output control register Oscillation output control register P40/P41 oscillation output control bits b1b0 00: P41, P40 = Normal port 01: P41 = Normal port, P40 = XOUT 10: P41 = Normal port, P40 = XCOUT 11: P41 = XCOUT , P40 = XOUT Not used (return “0” when read) (Do not write to “1”) (OSCOUT : address 0FF016) b7 b0 STP instruction S R Q XI N XO U T I n t e r r u p t r e q u e s t I n t e r r u p t d i s a b l e f l a g I R e s e t Sy s t e m c l o c k c o n t r o l b i t s P61/XCIN P62/XCOUT System clock control bits “01” Sy s t e m c l o c k c o n t r o l b i t s P 41/ O O U T P 40/ O O U T P41 direction register P40 direction register OSCOUT control P41 output latch P40 output latch O s c i l l a t i o n o u t p u t s e l e c t i o n c i r c u i t “ 0 1 ” “ 0 0 ” I Note When the signal from the XOUT pin or XCOUT pin of the oscillation circuit is input directly to the circuit except this MCU and used, the system operation may be unstabilized. In order to share the oscillation circuit safely, use the clock output from P4 0 and P41 by this function for the circuits except this MCU.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1.” After a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immediately after they have been written. After writing to an interrupt request reg- ister, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations

To calculate in decimal notation, set the decimal mode flag (D) to “1,” then execute an ADC or SBC instruction. After executing an ADC or SBC instruction, execute at least one instruction before executing an SEC, CLC, or CLD instruction.
In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers
If a value n (between 0 and 255) is written to a timer latch, the frequency division ratio is 1/(n+1).
The timers share the one frequency divider to generate the count source. Accordingly, when each timer starts operating, initializing the frequency divider is not executed. Therefore, when the frequency divider is selected for the count source, the delay of the maximum one cycle of the count source is generated until the timer starts counting or the waveform is output from timer starts operating. Also, the count source cannot be checked externally. Multiplication and Division Instructions
The index X mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction.
The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The fol- lowing cannot be used:
The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction register as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instructions (ROR, CLB, or SEB, etc.) to a direction register. Use instructions such as LDM and STA, etc., to set the port direction registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an exter- nal clock and it is to output the S RDY signal, set the transmit enable bit, the receive enable bit, and the SRDY output enable bit to “1.” Serial I/O continues to output the final bit from the TXD pin after trans- mission is completed. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Therefore, make sure that f(X IN) is at least on 250 kHz (Note) during an A-D conversion. Note: When the frequency divided by 2/4/8 is selected by the AD conversion clock selection bits, the above frequency is multi- plied by 2/4/8. Also, when the STP instruction is executed dur- ing the A-D conversion, the A-D conversion is stopped imme- diately, the A-D conversion completion bit is set to “1”, and the interrupt request is generated. LCD When the LCD power input pin VL3 is not used, connect it to VCC . Instruction Execution Time The instruction execution time is obtained by multiplying the number of cycles shown in the list of machine instructions by the period of the internal clock φ.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.

ELECTRICAL CHARACTERISTICS

Table 11 Absolute maximum ratings (Mask ROM version) Parameter Power source voltage Input voltage P0 0–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P62 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN, CNVSS Output voltage P00–P07, P10–P17, P20–P27 Output voltage COM0–COM 3 Output voltage P30–P37, P40–P47, P50–P57, P60–P62 Output voltage XOUT Power dissipation Operating temperature Storage temperature Symbol V CC VI VI VI VI VI VO VO VO VO Pd Topr Tstg Conditions All voltages are based on Vss. Output transistors are cut off. At output port At segment output Ta = 25°C Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3+0.3 –0.3 to VL3+0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 Unit V V V V V V V V V V V mW Recommended Operating Conditions Table 12 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Power source voltage f( φ) = 8 MHz f(φ) = 2 MHz Low-speed mode Power source voltage A-D converter reference voltage Analog power source voltage Analog input voltage AN 0–AN 7 “H” input voltage P04–P07, P10–P17, P20–P27, P30, P32, P35, P36, P40–P47, P52, P53, P62 “H” input voltage P00–P03, P31, P33, P34, P37, P50, P51, P54–P57, P60, P61 “H” input voltage RESET “H” input voltage XIN, XCIN “L” input voltage P04–P07, P10–P17, P20–P27, P30, P32,P 35, P36, P40–P47, P52, P53, P62 “L” input voltage P00–P03, P31, P33, P34, P37, P50, P51, P54–P57, P60, P61, CNVSS “L” input voltage RESET “L” input voltage XIN, XCIN VCC VSS VREF AV SS VIA VIH VIH VIH VIH VIL VIL VIL VIL Limits V V V V V V V V V V V V V V V Parameter Min. 4.0 1.8 1.8 V CC –0.3 AV SS 0.7VCC 0.8VCC 0.9VCC 65 ✕ VCC –99 100 1.5 Typ. 5.0 5.0 5.0 Max. 5.5 5.5 5.5 V CC +0.3 VCC VCC VCC VCC VCC VCC 0.3VCC 0.2VCC 0.2VCC 65 ✕ VCC –99 100 0.4 Symbol Unit 2.2 V ≤ VCC ≤ 5.5 V VCC ≤ 2.2 V 2.2 V ≤ VCC ≤ 5.5 V VCC ≤ 2.2 V VCC –

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. “H” total peak output current (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 “H” total peak output current (Note 1) P40–P47, P50–P57, P60–P62 “L” total peak output current (Note 1) P00–P07, P10–P17, P20–P27 “L” total peak output current (Note 1) P40–P47, P50, P51, P54–P57, P60–P62 “L” total peak output current (Note 1) P30–P37, P52, P53 “H” total average output current (Note 1) P00–P07, P10–P17, P20–P27, P30–P37 “H” total average output current (Note 1) P40–P47, P50–P57, P60–P62 “L” total average output current (Note 1) P00–P07, P10–P17, P20–P27 “L” total average output current (Note 1) P40–P47, P50, P51, P54–P57, P60–P62 “L” total average output current (Note 1) P30–P37, P52, P53 “H” peak output current (Note 2) P00–P07, P10–P17, P20–P27 “H” peak output current (Note 2) P30–P37, P41–P47, P50–P57, P60–P62 “L” peak output current (Note 2) P00–P07, P10–P17, P20–P27 “L” peak output current (Note 2) P40–P47, P50, P51, P54–P57, P60–P62 “L” peak output current (Note 2) P30–P37, P52, P53 “H” average output current (Note 3) P00–P07, P10–P17, P20–P27 “H” average output current (Note 3) P40–P47, P50–P57, P60–P62 “L” average output current (Note 3) P00–P07, P10–P17, P20–P27 “L” average output current (Note 3) P40–P47, P50, P51, P54–P57, P60–P62 “L” average output current (Note 3) P30–P37, P52, P53 ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Limits mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Parameter Min. Typ. Max.Symbol Unit –20 –20 110 –10 –10 –1.0 –5.0 –0.5 –2.5 5.0 5.0 Table 13 Recommended operating conditions (Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is average value measured over 100 ms.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Table 14 Recommended operating conditions (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Timer X and Timer Y Input frequency (duty cycle 50%) System clock φ frequency Main clock input oscillation frequency (Note 1) Sub-clock input oscillation frequency (Notes 1, 2) f(CNTR f(CNTR1) f(φ) f(XIN) f(XCIN) Limits MHz MHz MHz MHz MHz MHz kHz Parameter Min. Typ. 32.768 Max. 4.0 (15✕ V CC –16)/11 8.0 (30✕ VCC –32)/11 8.0 20✕ VCC –32 Symbol Unit (VCC ≤ 4.0 V) (VCC ≤ 4.0 V) (VCC ≤ 2.0 V) Notes 1:When the oscillation frequency has a duty cycle of 50%. 2:When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. IOH = –1 mA IOH = –0.25 mA VCC = 1.8 V IOH = –5 mA IOH = –1.5 mA IOH = –1.25 mA VCC = 1.8 V IOL = 10 mA IOL = 3 mA IOL = 2.5 mA VCC = 1.8 V IOL = 15 mA IOL = 4 mA VCC = 1.8 V VI = VCC VI = VCC VI = VCC VI = VSS Pull-up “OFF” VCC = 5.0 V, VI = VSS Pull-up “ON” V CC = 1.8 V, VI = VSS Pull-up “ON” V I = VSS VI = VSS “H” output voltage P00–P07, P10–P17, P20–P27 “H” output voltage P30–P37, P40–P47, P50–P57, P60–P62 “L” output voltage P00–P07, P10–P17, P20–P27, P40–P47, P50, P51, P54–P57, P60–P62 “L” output voltage P30–P37, P52, P53 Hysteresis INT0–INT2, CNTR0, CNTR1, P00–P03, P54–P57 Hysteresis SCLK1 , SCLK2 , RxD1, RxD2 Hysteresis RESET “H” input current 0–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P62 “H” input current RESET “H” input current X IN “L” input current P00–P07, P10–P17, P20–P27, P30–P37, P40–P47, P50–P57, P60–P62 “L” input current RESET “L” input current X IN Limits V V V V V V V V V V V V V µA µA µA µA µA µA µA µA Parameter Min. V CC –2.0 VCC –0.8 VCC –2.0 VCC –0.5 VCC –0.8 –60 –5.0 Typ. 0.5 0.5 0.5 4.0 –120 –20 –4.0 Max. 2.0 0.5 0.8 2.0 0.8 5.0 5.0 –5.0 –240 –40 –5.0 Symbol UnitTest conditions V OH VOH VOL VOL VT+–VT- VT+–VT- VT+–VT- IIH IIH IIH IIL IIL IIL Table 15 Electrical characteristics (Mask ROM version) (Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. RAM hold voltage Power source current LimitsParameter Min. 1.8 Typ. 5.1 1.0 0.1 Max. 5.5 7.5 2.0 1.0 Symbol Unit When clock is stopped Through mode, Vcc = 5 V f(X IN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “OFF”, A-D converter in operating Through mode, Vcc = 5 V f(X IN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “OFF”, A-D converter stopped Low-speed mode, V CC = 5 V, Ta ≤ 55 °C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “OFF” Low-speed mode, VCC = 5 V, Ta = 25 °C f(X IN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “OFF” Low-speed mode, VCC = 3 V, Ta ≤ 55 °C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “OFF” Low-speed mode, VCC = 3 V, Ta = 25 °C f(X IN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “OFF” All oscillation stopped (in STP state) Output transistors “OFF” Test conditions V RAM ICC V mA mA µA µA µA µA µA µA Ta = 25 °C Ta = 85 °C Table 16 Electrical characteristics (Mask ROM version) (Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. A-D Converter Characteristics Table 17 A-D converter characteristics (Mask ROM version) (Vcc = 2.2 to 5.5 V, Vss = AVSS = 0 V, Ta = –20 to 85°C, Port state = stopped, unless otherwise noted) Resolution Differencial non-linearity error Non-linearity error Off-set error Full-scale error Differencial non-linearity error Non-linearity error Off-set error Full-scale error Conversion time Ladder resistor Reference input current Analog input current Unit Bits LSB LSB µs kΩ µA µA LimitsParameter Min. Typ. 150 Max. tc(X IN)✕121 (Note) 100 200 5.0 Symbol V CC = VREF = 5 V

VCC = VREF = 2.2 V, AD clock frequency = 250 kHz
VCC = VREF = 2.3 V, AD clock frequency = 500 kHz
VCC = VREF = 2.4 V, AD clock frequency = 1 MHz
VCC = VREF = 2.5 V, AD clock frequency = 2 MHz
VCC = VREF = 2.5 V, AD clock frequency = 4 MHz
VCC = VREF = 2.6 V, AD clock frequency = 8 MHz AD conversion clock selection bit :Frequency not divided, 10bitAD mode V REF = 5 V Test conditions Tconv R LADDER IVREF IIA Note: When “Frequency/2, 4 or 8” is selected by the AD conversion clock selection bit, the above conversion time is multiplied by 2, 4 or 8. LCD Power Supply Characteristics Table 18 LCD power supply characteristics (when connecting division resistors for LCD power supply) (Vcc = 1.8 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Division resistor for LCD power supply (Note) Unit kΩ LimitsParameter Min. Typ. 200 120 150 120 170 150 190 170 150 120 170 150 190 170 190 190 Max.Symbol RSEL = “10” RSEL = “11” LCD drive timing A LCD circuit division ratio = divided by 1 RSEL = “01” RSEL = “00” LCD circuit division ratio = divided by 2 RSEL = “01” RSEL = “00” LCD circuit division ratio = divided by 4 RSEL = “01” RSEL = “00” LCD circuit division ratio = divided by 8 RSEL = “01” RSEL = “00” LCD drive timing B LCD circuit division ratio = divided by 1 RSEL = “01” RSEL = “00” LCD circuit division ratio = divided by 2 RSEL = “01” RSEL = “00” LCD circuit division ratio = divided by 4 RSEL = “01” RSEL = “00” LCD circuit division ratio = divided by 8 RSEL = “01” RSEL = “00” Test conditions R LCD Note: The value is the average of each one division resistor.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. tw (RESET) tc(XIN) twH (XIN) twL (XIN) tc(CNTR) twH (CNTR) twL (CNTR) twH (INT) twL (INT) tc(SCLK ) twH (SCLK ) twL (SCLK ) tsu(RxD-SCLK ) th(SCLK -RxD) Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H ” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H ” pulse width CNTR 0, CNTR1 input “L” pulse width INT0–INT2 input “H ” pulse width INT0–INT2 input “L” pulse width Serial I/O1, 2 clock input cycle time (Note) Serial I/O1, 2 clock input “H ” pulse width (Note) Serial I/O1, 2 clock input “L” pulse width (Note) Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time tw (RESET) tc(XIN) twH (XIN) twL (XIN) tc(CNTR) twH (CNTR) twL (CNTR) twH (INT) twL (INT) tc(SCLK ) twH (SCLK ) twL (SCLK ) tsu(RxD-SCLK ) th(SCLK -RxD) Limits µs ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. 125 250 105 105 800 370 370 220 100 Typ. Max.Symbol Unit Limits µs ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. 125 11000/(15✕ V CC –16) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 Typ. Max.Symbol Unit Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H ” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H ” pulse width CNTR 0, CNTR1 input “L” pulse width INT0–INT2 input “H ” pulse width INT0–INT2 input “L” pulse width Serial I/O1, 2 clock input cycle time (Note) Serial I/O1, 2 clock input “H ” pulse width (Note) Serial I/O1, 2 clock input “L” pulse width (Note) Serial I/O1, 2 input setup time Serial I/O1, 2 input hold time Table 20 Timing requirements 2 (Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Timing Requirements And Switching Characteristics Table 19 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART). Note : When bit 6 of address 0FE016 or 0FE316 is “1” (clock synchronous). Divide this value by four when bit 6 of address 0FE016 or 0FE316 is “0” (UART).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. twH (SCLK ) twL (SCLK ) td(SCLK -TxD) tV(SCLK -TxD) tr(SCLK ) tf(SCLK ) tr(CMOS) tf(CMOS) twH (SCLK ) twL (SCLK ) td(SCLK -TxD) tV(SCLK -TxD) tr(SCLK ) tf(SCLK ) tr(CMOS) tf(CMOS) LimitsParameter Min. tc(SCLK )/2–30 tc(SCLK )/2–30 –30 Typ. Max. 140 Symbol Unit ns ns ns ns ns ns ns ns Notes 1:When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is “0.” 2:The XOUT , XCOUT pins are excluded. Serial I/O1, 2 clock output “H ” pulse width Serial I/O1, 2 clock output “L” pulse width Serial I/O1, 2 output delay time (Note 1) Serial I/O1, 2 output valid time (Note 1) Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Table 21 Switching characteristics 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Limits ns ns ns ns ns ns ns ns Parameter Min. t C (SCLK )/2–50 tC (SCLK )/2–50 –30 Typ. Max. 350 Symbol Unit Serial I/O1, 2 clock output “H ” pulse width Serial I/O1, 2 clock output “L” pulse width Serial I/O1, 2 output delay time (Note 1) Serial I/O1, 2 output valid time (Note 1) Serial I/O1, 2 clock output rising time Serial I/O1, 2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) Table 22 Switching characteristics 2 (Vcc = 1.8 to 4.0 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Notes 1:When the P-channel output disable bit (bit 4 of address 0FE116 or 0FE416) is “0.” 2:The XOUT , XCOUT pins are excluded. Fig. 56 Circuit for measuring output switching characteristics Measurement output pin 100pF C M O S o u t p u t Measurement output pin 100pF N-channel open-drain output (Note) kΩ Note: When bit 4 of the UART control register (address 0EF116 or 0FE416) is “ 1.” (N-channel open-drain output mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 57 Timing chart CNTR 0,CNTR 1 I N t o I N 0.2VCC td( SC L TXD tf 0.2VCC VC C VC C tr ts R XD SC L K)t h( SC L R XD tv(SCLK -TXD) tC (SCLK ) tW SC L K) tW H ( SC L TXD 1 TXD 2 R XD 1 R XD 2 SCLK1 SCLK2 VC C tWL (XIN) 0.8VCC tWH (XIN) tC ( XI N ) XIN 0.2VCC VC C tW ( R E S E T R E S E T VC C tWL (CNTR) 0.8VCC tWH (CNTR) tC ( C N T R VC C tWL (INT) 0.8VCC tWH (INT)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. PACKAGE OUTLINE QFP64-P-1414-0.80 1.11 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Alloy 42 64P6N-A Plastic 64pin 14✕ 14mm body QFP Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D A1 0.20.1 0.5 ––I2 1.3 ––M D 14.6 ––M E 14.6 10°0° 0.1 1.4 0.80.60.4 17.116.816.5 17.116.816.5 0.8 14.214.013.8 14.214.013.8 0.20.150.13 0.450.350.3 2.8 3.05 e e e E c H E 64 49 H D D M D M E A F A1 A2 L y Recommended Mount Pad Detail F x –– 0.2 b x M LQFP64-P-1010-0.50 – Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 64P6Q-A Plastic 64pin 10✕ 10mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 1.0 ––M D 10.4 ––M E 10.4 10°0° 0.1 1.0 0.70.50.3 12.212.011.8 12.212.011.8 0.5 10.110.09.9 10.110.09.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e E H E 64 49 3217 H D D M D M E A F y Recommended Mount Pad Lp 0.45 0.6 0.25 0.75 0.08 x b x M A1 A2 L Detail F Lp c e

0008 Printed in Japan (ROD) II

New publication, effective Aug. 2000. Specifications subject to change without notice. Notes regarding these materials

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Rev. Rev. No. date

1.0 First Edition 000830

1.1 P53 Table 12 Recommended operating condition 000901

Parameter of VIH, VIL : “XIN” (wrong) → “XIN, XCIN” (correct) REVISION DESCRIPTION LIST 38C2 GROUP DATA SHEET (1/1) Revision Description

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38C2 specifications and overview.

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER????

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER????

Source title 38C2 Datasheet(PDF) - Mitsubishi Electric Semiconductor

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