38C1

M38C13E6HP MITSUBISHI | Alldatasheet

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Technical content

DESCRIPTION

The 38C1 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 38C1 group has the LCD drive control circuit, an 8-channel A- D converter, and serial I/O as additional functions. The various microcomputers in the 38C1 group include variations of internal memory size and packaging. For details, refer to the section on part numbering.

FEATURES

(at 8 MHz oscillation frequency)

• Memory size (includes key input interrupt) (It can be used in the low-speed mode.)
• LCD drive control circuit (connect to external ceramic resonator or built-in ring oscillator) (connect to external quartz-crystal oscillator)
• Power source voltage In high-speed mode (f(X In middle-speed mode (Mask ROM version: f(XIN) ≤ 6.0 MHz) In middle-speed mode (One Time PROM version: f(XIN) ≤ 6.0 MHz)
• Power dissipation (Mask ROM version) CC = 5 V, f(XIN) = 8 MHz , Ta = 25 °C) (VCC = 2.5 V, f(XIN) = stop , f(XCIN) = 32 kHz , Ta = 25 °C)

APPLICATIONS

Household appliances, consumer electronics, etc. 38C1 Group MITSUBISHI MICROCOMPUTERS SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 1 Pin configuration of M38C1XMX-XXXFP/HP PIN CONFIGURATION (TOP VIEW) Outline 64P6U-A/64P6Q-A P 34( L E D 4) / ( K W 4) 6789 1 0 1 1 1 21 31 P 24/ S E G 2 C O M 1 C O M 0 P 02/ S E G 2 P 51/ I N T1 P56/SCLK P55/SOUT P54/SIN P 53/ C N T R 1 12345 M 3 8 C 1 X M X - X X X F P / H P P 32/ ( L E D 2) / ( K W 2) XO U T P 52/ C N T R 0 VL3 P47/AN7 P46/AN6 VS S P 50/ I N T0 A N 0/ A D K E Y0 C N VS S P 61/ XC O U T P 60/ XC I N VC C R E S E T P 57/ SR D Y P 31/ ( L E D 1) / ( K W 1) P 00/ S E G 0 P30/(LED0)/(KW0) VL VL P 04/ S E G 4 P 05/ S E G 5 P 06/ S E G 6 P 07/ S E G 7 S E G 8 S E G 9 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 S E G 1 XI N P 27/ S E G 2 P 25/ S E G 2 P 26/ S E G 2 3334353 8394041424 344454 A N 1/ A D K E Y1 A N 2/ A D K E Y2 P 20/ S E G 1 P 23/ S E G 2 P 21/ S E G 1 P 22/ S E G 1 P45/AN5 P44/AN4 AN 3/ADKEY 3 P 64 P 63/φO U T P 62/ T O U T S E G 1 C O M 3 C O M 2P 33( L E D 3) / ( K W 3) P 01/ S E G 1 P 3/ S E G 3

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group FUNCTIONAL BLOCK DIAGRAM Fig. 2 Functional block diagram I / O p o r t P P 5 I / O p o r t P I / O p o r t P P 3 I / O p o r t P P 2 P 4 I / O p o r t P P 6 2 0 2 1 2 2 3 1 3 2 3 3 3 4 2 3 2 4 2 5 2 6 2 7 2 8 2 9 3 0 1 5 1 6 1 7 1 8 1 9 5 5 5 6 5 7 5 8 5 9 5 3 5 4 4 3 4 2 4 1 4 0 3 9 3 8 3 7 3 6 6 3 6 2 A n a l o g i n p u t A N I n p u t p o r t P P 0 4 5 4 6 4 7 4 8 4 9 5 0 5 1 1 0 3 5 5 2 4 4 C l o c k g e n e r a t i n g c i r c u i t M a i n c l o c k i n p u t X I N M a i n c l o c k o u t p u t X O U T X C O U T S u b c l o c k o u t p u t X C I N S u b c l o c k i n p u t S I O A - D c o n v e r t e r T i m e r X T i m e r Y T i m e r T i m e r T i m e r L C D d r i v e c o n t r o l c i r c u i t V L V L V L C O M C O M C O M C O M S E G S E G S E G S E G φ 1 2 1 3 R i n g o s c i l l a t o r S E G S E G S E G S E G S E G D a t a b u s C P U A X Y S P C H P C L P SR E S E T V C C V S S R e s e t i n p u t ( 5 V ( 0 V ) R O M R A M 1 4 1 1 L C D d i s p l a y r e g i s t e r ( 1 b y t e s C N T R0, C N T TO U T I N T0, I N K e y o n w a k e u p X C I N X C O U T φ

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group PIN DESCRIPTION Table 1 Pin description FunctionPin Name Function except a port function

• Apply voltage of power source to VCC , and 0 V to VSS . (As for VCC , refer to the recommended operating condition)
• Connect to Vss.
• Reset input pin for active “L”.
• Input and output pins for the main clock generating circuit.
• Connect a ceramic resonator or a quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the X IN pin and leave the XOUT pin open. A feedback resistor is built-in.
• Input 0 ≤ V L1 ≤ VL2 < VL3 voltage.
• LCD common output pins.
• 8-bit input port.
• CMOS compatible input level. 1, 2, 4 or 8-bit input and 8-bit pull-down can be programmed.
• LCD segment output pin.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-down can be programmed.
• 5-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed.
• Analog input pins for A-D converter. When these pins are used as ADKEY pins, the input voltage of ADKEY pin which is input “L” level is A-D converted automatically.
• 4-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed.
• 8-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed.
• 5-bit I/O port.
• CMOS compatible input level.
• CMOS 3-state output structure.
• 1-bit input/output and pull-up can be programmed. Power source CNV SS Reset input Clock input VCC , VSS CNV SS RESET XIN XOUT VL1–VL3 COM 0–COM 3 P00/SEG 0– P07/SEG 7 SEG 8–/SEG 16 P20/SEG 17– P27/SEG 24 P30(LED)/KW0– P34(LED)/KW4 AN 0/ADKEY 0– AN 3/ADKEY3 P44/AN4– P47/AN7 P50/INT0, P51/INT1 P52/CNTR 0 P53/CNTR 1 P54/SIN P55/SOUT P56/SCLK P57/SRDY P60/XCIN P61/XCOUT P62/TOUT P63/φOUT P64 Clock output LCD power source Common output Input port P0 Segment output pin I/O port P2 I/O port P3 Analog input I/O port P4 I/O port P5 I/O port P6
• LCD segment output pins
• LCD segment output pins
• Key input (key-on wake-up) interrupt input pins
• ADKEY input pins
• Analog input pins for A-D converter
• Interrupt input pins
• Timer X, timer Y function pins
• Serial I/O function pins
• Sub-clock generating circuit I/O pins (Oscillator is connected. External clock cannot be input directly.) Timer 2 output pin System clock φ output

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group PART NUMBERING Fig. 3 Part numbering M 3 8 C 1 3M 6 - X X XF PP r o d u c t R O M / P R O M s i z e A B C D E F : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes : 36864 bytes : 40960 bytes : 45056 bytes : 49152 bytes : 53248 bytes : 57344 bytes : 61440 bytes T h e f i r s t 1 2 8 b y t e s a n d t h e l a s t 2 b y t e s o f R O M a r e r e s e r v e d a r e a s t h e y c a n n o t b e u s e d P a c k a g e t y p e F P H P : 64P6U-A package : 64P6Q-A package ROM num ber Omitted in One Time PROM version. M emory type M: Mask ROM version E: One Time PROM version R A M s i z e : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes : 1536 bytes : 2048 bytes

Mitsubishi plans to expand the 38C1 group as follows. Support for Mask ROM version, One Time PROM version. Currently products are listed below. Table 2. List of products As of May. 2002 Products under development or planning :the development schedule and specification may be revised without notice.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group FUNCTIONAL DESCRIPTION CENTRAL PROCESSING UNIT (CPU) The 38C1 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine instructions or the 740 Family Software Manual for details on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. [Accumulator (A)] The accumulator is an 8-bit register. Data operations such as data transfer, etc., are executed mainly through the accumulator. [Index Register X (X)] The index register X is an 8-bit register. In the index addressing modes, the value of the OPERAND is added to the contents of register X and specifies the real address. [Index Register Y (Y)] The index register Y is an 8-bit register. In partial instruction, the value of the OPERAND is added to the contents of register Y and specifies the real address. [Stack Pointer (S)] The stack pointer is an 8-bit register used during subroutine calls and interrupts. This register indicates start address of stored area (stack) for storing registers during subroutine calls and interrupts. The low-order 8 bits of the stack address are determined by the contents of the stack pointer. The high-order 8 bits of the stack address are determined by the stack page selection bit. If the stack page selection bit is “0” , the high-order 8 bits becomes “00 16”. If the stack page selection bit is “1”, the high-order 8 bits becomes “0116”. The operations of pushing register contents onto the stack and popping them from the stack are shown in Figure 6. Store registers other than those described in Figure 6 with pro- gram when the user needs them during interrupts or subroutine calls. [Program Counter (PC)] The program counter is a 16-bit counter consisting of two 8-bit registers PC H and PCL. It is used to indicate the address of the next instruction to be executed. Fig. 5 740 Family CPU register structure A Accumulator b7 b0 b7b15 b0 b7 b0 X Index register X Y Index register Y S Stack pointer PC L Program counterPC H N V T B D I Z C Processor status register (PS) Carry flag Zero flag Interrupt disable flag Decimal mode flag Break flag Index X mode flag Overflow flag Negative flag

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Table 3 Push and pop instructions of accumulator or processor status register Accumulator Processor status register Push instruction to stack PHA PHP Pop instruction from stack PLA PLP Fig. 6 Register push and pop at interrupt generation and subroutine call Note: Condition for acceptance of an interrupt Interrupt enable flag is “1” E x e c u t e J S R On-going Routine M (S) (PC H ) S S M S P C L) E x e c u t e R T S P C L)M S (S) (S)– 1 S S S S P C H )M S S u b r o u t i n e P O P re t u r n a d d r e s s f r o m s t a c k P u s h r e t u r n a d d r e s s o n s t a c k M S P S E x e c u t e R T I P S S (S) (S) – 1 (S) (S) + 1 I n t e r r u p t S e r v i c e R o u t i n e POP contents of processor status register from stack M (S) (PC H ) (S) (S) – 1 M (S) (PC L) (S) (S) – 1 (PCL)M ( S ) (S) (S) + 1 (S) (S) + 1 (PCH )M ( S ) POP return address from stack I Flag is set from “0” to “1” Fetch the jump vector Push return address on stack Push contents of processor status register on stack I n t e r r u p t r e q u e s t (Note) Interrupt disable flag is “0”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group [Processor status register (PS)] The processor status register is an 8-bit register consisting of 5 flags which indicate the status of the processor after an arithmetic operation and 3 flags which decide MCU operation. Branch opera- tions can be performed by testing the Carry (C) flag , Zero (Z) flag, Overflow (V) flag, or the Negative (N) flag. In decimal mode, the Z, V, N flags are not valid.

• Bit 0: Carry flag (C) The C flag contains a carry or borrow generated by the arith- metic logic unit (ALU) immediately after an arithmetic operation. It can also be changed by a shift or rotate instruction.
• Bit 1: Zero flag (Z) The Z flag is set if the result of an immediate arithmetic operation or a data transfer is “0”, and cleared if the result is anything other than “0”.
• Bit 2: Interrupt disable flag (I) The I flag disables all interrupts except for the interrupt gener- ated by the BRK instruction. Interrupts are disabled when the I flag is “1”.
• Bit 3: Decimal mode flag (D) The D flag determines whether additions and subtractions are executed in binary or decimal. Binary arithmetic is executed when this flag is “0”; decimal arithmetic is executed when it is “1”. Decimal correction is automatic in decimal mode. Only the ADC and SBC instructions can be used for decimal arithmetic.
• Bit 4: Break flag (B) The B flag is used to indicate that the current interrupt was gen- erated by the BRK instruction. The BRK flag in the processor status register is always “0”. When the BRK instruction is used to generate an interrupt, the processor status register is pushed onto the stack with the break flag set to “1”.
• Bit 5: Index X mode flag (T) When the T flag is “0”, arithmetic operations are performed be- tween accumulator and memory. When the T flag is “1”, direct arithmetic operations and direct data transfers are enabled be- tween memory locations.
• Bit 6: Overflow flag (V) The V flag is used during the addition or subtraction of one byte of signed data. It is set if the result exceeds +127 to -128. When the BIT instruction is executed, bit 6 of the memory location op- erated on by the BIT instruction is stored in the overflow flag.
• Bit 7: Negative flag (N) The N flag is set if the result of an arithmetic operation or data transfer is negative. When the BIT instruction is executed, bit 7 of the memory location operated on by the BIT instruction is stored in the negative flag. Table 4 Set and clear instructions of each bit of processor status register Set instruction Clear instruction C flag SEC CLC Z flag I flag SEI CLI D flag SED CLD B flag T flag SET CLT V flag CLV N flag

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group [CPU Mode Register (CPUM)] 003B16 The CPU mode register contains the stack page selection bit and the internal system clock selection bit. The CPU mode register is allocated at address 003B 16. After system is released from reset, the ring oscillator mode is se- lected, and the XIN–X OUT oscillation and the XCIN –X COUT oscillation are stopped. Fig. 7 Structure of CPU mode register N ot available Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 page 1 : 1 page Main clock selection bit 0 : X IN input signal (XIN–XOUT oscillating) 1 : Built-in ring oscillator (internal system clock: only frequency divided by 8 is valid.) Port Xc switch bit 0 : I/O port function (Oscillation stop) 1 : X CIN–XCOUT oscillating function XIN–XOUT oscillation stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit (this bit is invalid when ring oscillator is selected.) 0 : f(X IN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : Main clock selected (middle-/high-speed, ring oscillator mode) 1 : X CIN–XCOUT selected (low-speed mode) CPU mode register ( C P U M : a d d r e s s 0 0 3 B1 6, i n i t i a l v a l u e : 6 81 b 7 b 0 Fig. 8 Switching method of CPU mode register N Y A f t e r r e l e a s i n g r e s e t S t a r t t h e o s c i l l a t i o n b i t s a n d o f C P U M S w i t c h t h e m a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t s b i t o f C P U M M a i n r o u t i n e Start with a built-in ring oscillator. Initial value of CPUM is 6816. As for the details of condition for transition among each mode, refer to the state transition of system clock. O s c i l l a t o r s t a r t s o s c i l l a t i o n . D o n o t c h a n g e b i t b i t a n d b i t o f C P U M u n t i l o s c i l l a t i o n s t a b i l i z e s W a i t b y r i n g o s c i l l a t o r o p e r a t i o n u n t i l e s t a b l i s h m e n t o f o s c i l l a t o r c l o c k L o w - , m i d d l e - , o r h i g h - s p e e d m o d e S e l e c t i n t e r n a l s y s t e m c l o c k b i t o r b i t o f C P U M S y s t e m c a n o p e r a t e i n r i n g o s c i l l a t o r m o d e u n t i l o s c i l l a t i o n s t a b i l i z e S e l e c t i n t e r n a l s y s t e m c l o c k . D o n o t c h a n g e b i t a n d b i t o r b i t a n d b i t o f C P U M a t t h e s a m e t i m e S e l e c t m a i n c l o c k d i v i s i o n r a t i o . S w i t c h t o h i g h s p e e d m o d e h e r e i f n e c e s s a r y When the low-, middle- or high-speed mode is used after the XIN– XOUT oscillation and the XCIN–XCOUT oscillation are enabled, wait in the ring oscillator mode until oscillation stabilizes, and then, switch the operation mode. When the middle- and high-speed mode are not used (X IN-XOUT oscillation and external clock input are not performed), connect XIN to VCC through a resistor.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 9 Memory map diagram 1 9 2 00FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 063F16 083F16 R A M a r e a R A M s i z e b y t e s A d d r e s s X X X 4 0 9 6 F 0 0 01 E D C B A F 0 8 01 E D C B A ROM area ROM size (bytes) A d d r e s s Y Y Y A d d r e s s Z Z Z 010016 000016 004016 044016 FF0016 FFDC 16 F F F E1 FFFF 16 XXXX 16 YYYY 16 ZZZZ 16 RAM R O M R eserved area S F R a r e a N ot used (Note) I n t e r r u p t v e c t o r a r e a R eserved ROM area (128 bytes) Z e r o p a g e S p e c i a l p a g e R e s e r v e d R O M a r e a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 10 Memory map of special function register (SFR) 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 0 6 φ output control register 6 0 C 1 6 0 C 1 6 T e m p o r a r y d a t a r e g i s t e r T D 000D 16 002D 16 Temporary data register 2 (TD1) 6 0 6 T e m p o r a r y d a t a r e g i s t e r T D 6 0 6 R R F r e g i s t e r R R F

001016 LCD display register 0(LCD0) 003016

6 LCD display register 1(LCD1) 0

L C D d i s p l a y r e g i s t e r L C D 2) L C D d i s p l a y r e g i s t e r L C D 3) L C D d i s p l a y r e g i s t e r L C D 4) L C D d i s p l a y r e g i s t e r L C D 5) L C D d i s p l a y r e g i s t e r L C D 6) L C D d i s p l a y r e g i s t e r L C D 7) LCD display register 8(LCD8) LCD display register 9(LCD9) LCD display register 10(LCD10) LCD display register 11(LCD11) LCD display register 12(LCD12) P o r t P 0 ( P 0 ) Port P2 (P2) P o r t P 2 d i r e c t i o n r e g i s t e r ( P 2 D ) P o r t P 3 ( P 3 ) P o r t P 4 , A D K E Y p i n s e l e c t i o n ( P 4 ) P o r t P 4 d i r e c t i o n r e g i s t e r ( P 4 D ) P o r t P 5 ( P 5 ) P o r t P 5 d i r e c t i o n r e g i s t e r ( P 5 D ) P o r t P 6 ( P 6 ) P o r t P 6 d i r e c t i o n r e g i s t e r ( P 6 D ) Interrupt control register 2(ICON2) Timer 3 (T3) Timer X mode register (TXM) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Timer X (low) (TXL) Timer Y (low) (TYL) Timer 1 (T1) Timer 2 (T2) Timer X (high) (TXH) Timer Y (high) (TYH) Timer Y mode register (TYM) Timer 123 mode register (T123M) Segment output enable register (SEG) LCD mode register (LM) A-D control register (ADCON) A-D conversion register (AD) Port P3 direction register (P3D) S e r i a l I / O c o n t r o l r e g i s t e r ( S I O C O N ) S e r i a l I / O r e g i s t e r ( S I O ) PULL register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group I/O PORTS Direction Registers (Ports P2–P6) The I/O ports (P2–P6) have direction registers which determine the input/output direction of each individual pin. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Pull-up/Pull-down Control By setting the PULL register (address 003316), I/O ports can con- trol pull-up/pull-down (pins also used as segment output pin: pull- down, other pins: pull-up). Pull-up/pull-down of pins are performed by setting the PULL register to “1”. However, the contents of PULL register does not affect ports pro- grammed as the output ports. Input port P0 and I/O port P2 are pulled-down in the initial state. Also, the pull-down setting is invalid for pins set to segment output with the segment output enable register (address 0038 16). Fig. 11 Structure of PULL register b7 b P U L L r e g i s t e r P U L L a d d r e s s i n i t i a l v a l u e P20–P23 pull-down P24–P27 pull-down Note P30–P34 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60–P64 pull-up Note: These ports are invalid when selecting SEG. P00–P07 pull-down

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. No.Related SFRsInput/OutputNamePin Non-Port FunctionI/O Format Table 5 List of I/O port function COM 0–COM 3 P00/SEG 0– P07/SEG 7 SEG 8–/SEG 16 P20/SEG 17– P27/SEG 24 P30(LED)/KW0– P34(LED)/KW4 AN 0/ADKEY 0– AN 3/ADKEY3 P44/AN4– P47/AN7 P50/INT0, P51/INT1 P52/CNTR 0 P53/CNTR 1 P54/SIN P55/SOUT P56/SCLK P57/SRDY P60/XCIN P61/XCOUT P62/TOUT P63/φOUT P64 Common Input Port P0 Segment I/O Port P2 I/O Port P3 A-D conversion input I/O Port P4 I/O Port P5 I/O port P6 Output Input, individual bits Output Input/output individual bits Input/output individual bits Input Input/output individual bits Input/output individual bits Input/output individual bits LCD common output CMOS compatible input level CMOS 3-state output LCD segment output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output Analog input CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS 3-state output LCD segment output LCD segment output Key input (key-on wake-up) interrupt input ADKEY input A-D conversion input Interrupt input Timer X function input/output Timer Y function input Serial I/O function output Sub-clock generating circuit input/output Timer 2 output φ clock output LCD mode register PULL register Segment output enable register LCD0 –LCD3 LCD mode register LCD4 –LCD8 PULL register Segment output enable register LCD8 –LCD12 PULL register Interrupt control register A-D control register P4 data latch (ADKEY selected) PULL register A-D control register PULL register Interrupt edge selection register PULL register Timer X mode register PULL register Timer Y mode register PULL register Serial I/O control register PULL register CPU mode register PULL register Timer X mode register PULL register φ output control register PULL register (16) (1) (17) (2) (3) (15) (4) (3) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (18) Notes 1: For details of how to use double function ports as function I/O ports,refer to the applicable sections. 2: When an input level is at an intermediate potential,a current will flow from VCC to VSS through the input-stage gate. Especially, power source current may increase during execution of the STP and WIT instructions. Fix the unused input pins to “H ” or “L” through a resistor.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 12 Port block diagram (1) P o r t P Segment output enable bit P u l l d o w n c o n t r o l S e g m e n t o u t p u t e n a b l e b i t Data bus Port latch VL2/VL3 VL1/VSS P o r t P D a t a b u s VL VL VL1/VSS P o r t P 30– P 34, P 50, P Key input (key-on wakeup) interrupt input INT0, INT1 interrupt input D a t a b u s Port latch P u l l u p c o n t r o l P o r t P A n a l o g i n p u t p i n s e l e c t i o n b i t A D c o n v e r s i o n i n p u t Data bus Port latch Pull-up control P o r t P P o r t l a t c hD a t a b u s Timer output CNTR 0 interrupt input P u l l u p c o n t r o l T i m e r X o p e r a t i o n m o d e b i t P u l s e o u t p u t m o d e s e l e c t e d P o r t P Data bus Direction register P o r t l a t c h P u l l u p c o n t r o l CNTR 1 interrupt input P u l l d o w n c o n t r o l S e g m e n t o u t p u t e n a b l e b i t D i r e c t i o n r e g i s t e r D i r e c t i o n r e g i s t e rDirection register Direction register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 13 Port block diagram (2) S e r i a l I O t r a n s m i t e n d s i g n a l S y n c h r o n o u s c l o c k s e l e c t i o n b i t S e r i a l I O p o r t s e l e c t i o n b i t P 55/ SO U T P c h a n n e l o u t p u t d i s a b l e b i t Synchronous clock selection bit S e r i a l I O p o r t s e l e c t i o n b i t SR D Y o u t p u t s e l e c t i o n b i t P o r t P D a t a b u s Port Xc switch bit Port latch O s c i l l a t o r P o r t P P o r t X c s w i t c h b i t P o r t P D a t a b u s P o r t X c s w i t c h b i t P o r t l a t c h S u b c l o c k g e n e r a t i n g c i r c u i t i n p u t D i r e c t i o n r e g i s t e r Direction register P o r t s e l e c t i o n P u l l u p c o n t r o l Port selection • Pull-up control (8)Port P55 D a t a b u s Serial I/O output P o r t l a t c h (9)Port P56 D a t a b u s Serial I/O clock output S e r i a l I O c l o c k i n p u t P o r t l a t c h (10)Port P57 Data bus Serial I/O ready output Port latch P o r t P D a t a b u s S e r i a l I O i n p u t P o r t l a t c h P u l l u p c o n t r o l D i r e c t i o n r e g i s t e r D i r e c t i o n r e g i s t e r Direction register Direction register P u l l u p c o n t r o l Pull-up control Pull-up control Serial I/O port selection bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 14 Port block diagram (3) (13)Port P62 P o r t l a t c hD a t a b u s TO U T o u t p u t c o n t r o l b i t T i m e r o u t p u t D i r e c t i o n r e g i s t e r P u l l u p c o n t r o l C O M 0– C O M 3 VL3 VL2 VL1 S E G 8– S E G 1 VL VL VL VS S P o r t P φ φ output control bit P o r t l a t c hD a t a b u s Direction register P u l l u p c o n t r o l (15)AN0/ADKEY 0–AN 3/ADKEY 3 A D c o n v e r s i o n i n p u t A D K E Y s e l e c t i o n b i t A D K E Y e n a b l e b i t A n a l o g i n p u t s e l e c t i o n b i t (18)Port P64 Data bus P o r t l a t c h D i r e c t i o n r e g i s t e r Pull-up control The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. The voltage applied to the sources of P- channel and N-channel transistors is the controlled voltage by the bias value.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group INTERRUPTS Interrupts occur by thirteen sources: five external, seven internal, and one software. Interrupt Control Each interrupt is controlled by an interrupt request bit, an interrupt enable bit, and the interrupt disable flag except for the software in- terrupt set by the BRK instruction. An interrupt occurs if the corre- sponding interrupt request and enable bits are “1” and the inter- rupt disable flag is “0”. Interrupt enable bits can be set or cleared by software. Interrupt request bits can be cleared by software, but cannot be set by software. The BRK instruction cannot be disabled with any flag or bit. The I flag disables all interrupts except the BRK instruction interrupt. When several interrupts occur at the same time, the interrupts are received according to priority. Interrupt Operation By acceptance of an interrupt, the following operations are auto- matically performed: 1. The contents of the program counter and the processor status register are automatically pushed onto the stack. 2. The interrupt disable flag is set and the corresponding interrupt request bit is cleared. 3. The interrupt jump destination address is read from the vector table into the program counter. I Notes on Interrupts When the active edge of an external interrupt (INT0 , INT1, CNTR0 or CNTR 1) is set or an interrupt source where several interrupt source is assigned to the same vector address is switched, the corresponding interrupt request bit may also be set. Therefore, take following sequence: (1) Disable the interrupt. (2) Set the interrupt edge selection register (Timer X control regis- ter for CNTR0, Timer Y mode register for CNTR 1). (3) Clear the set interrupt request bit to “0.” (4) Enable the interrupt. Notes1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority. Table 6 Interrupt vector addresses and priority RemarksInterrupt Request Generating Conditions At reset At detection of either rising or falling edge of INT 0 input At detection of either rising or falling edge of INT 1 input At timer X underflow At timer Y underflow At timer 1 underflow At timer 3 underflow At detection of either rising or falling edge of CNTR 0 input At detection of either rising or falling edge of CNTR 1 input At timer 2 underflow At completion of serial I/O data transmission or reception At falling of conjunction of input level for port P3 (at input mode) At completion of A-D conversion At BRK instruction execution Interrupt Source LowHigh Priority Vector Addresses (Note 1) Reset (Note 2) INT0 INT1 Timer X Timer Y Timer 1 Timer 3 CNTR CNTR 1 Timer 2 Serial I/O Key input (Key-on wake-up) A-D conversion BRK instruction FFFD FFFB 16 FFF9 16 FFF3 16 FFF1 16 FFEF 16 FFED 16 FFEB 16 FFE9 16 FFE7 16 FFE3 16 FFE1 16 FFDF 16 FFDD 16 FFFC 16 FFFA 16 FFF8 16 FFF2 16 FFF0 16 FFEE 16 FFEC 16 FFEA 16 FFE8 16 FFE6 16 FFE2 16 FFE0 16 FFDE 16 FFDC 16 Non-maskable External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (active edge selectable) External interrupt (valid at falling) Valid when A-D interrupt is selected Non-maskable software interrupt

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 15 Interrupt control Fig. 16 Structure of interrupt-related registers I n t e r r u p t r e q u e s t b i t I n t e r r u p t e n a b l e b i t I n t e r r u p t d i s a b l e f l a g ( I ) B R K i n s t r u c t i o n R e s e t I n t e r r u p t r e q u e s t b 7 b0 I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r I N T0 i n t e r r u p t e d g e s e l e c t i o n b i t I N i n t e r r u p t e d g e s e l e c t i o n b i t N o t u s e d r e t u r n w h e n r e a d ( I N T E D G E : a d d r e s s 0 0 3 A1 6, i n i t i a l v a l u e : 0 01 Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Not used (return “0” when read) Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 3 interrupt request bit I n t e r r u p t c o n t r o l r e g i s t e r 1 INT0 interrupt enable bit INT1 interrupt enable bit Not used (Do not write “1” to these bits.) Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 3 interrupt enable bit 0 : N o i n t e r r u p t r e q u e s t i s s u e d I n t e r r u p t r e q u e s t i s s u e d (IREQ1 : address 003C 16, initial value: 0016) ( I C O N 1 : a d d r e s s 0 0 3 E1 6, i n i t i a l v a l u e : 0 01 I n t e r r u p t r e q u e s t r e g i s t e r 2 C N T R 0 i n t e r r u p t r e q u e s t b i t C N T R 1 i n t e r r u p t r e q u e s t b i t T i m e r i n t e r r u p t r e q u e s t b i t N o t u s e d r e t u r n s w h e n r e a d S e r i a l I O i n t e r r u p t r e q u e s t b i t K e y i n p u t i n t e r r u p t r e q u e s t b i t A D c o n v e r s i o n i n t e r r u p t r e q u e s t b i t N o t u s e d r e t u r n s w h e n r e a d (IREQ2 : address 003D 16, initial value: 0016) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 2 interrupt enable bit Not used (Do not write “1” to this bit) Serial I/O interrupt enable bit Key input interrupt enable bit AD conversion interrupt enable bit Not used (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F16, initial value: 0016) 0 : Falling edge active 1 : Rising edge active b7 b0 b 7 b 0 b7 b0 b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Key Input Interrupt (Key-on Wake Up) A Key-on wake up interrupt request is generated by applying “L” level voltage to any pin of port P3 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 17, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports P3 0–P33. Fig. 17 Connection example when using key input control register, key input interrupt and port P3 block diagram P o r t P l a t c h Port P30 direction register = “0” Port P31 latch Port P31 direction register = “0” Port P32 latch Port P32 direction register = “0” P o r t P l a t c h Port P33 direction register = “0” P o r t P l a t c h Port P34 direction register = “1” P i n p u t P31 input P i n p u t P i n p u t P o u t p u t PULL register Bit 3 = “1” Port P3 input read circuit Port PXx “L” level output K e y i n p u t i n t e r r u p t r e q u e s t P-channel transistor for pull-up CMOS output buffer ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽✽ ✽ ✽

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group TIMERS The 38C1 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “0”, an underflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high- and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct operation when reading during the write operation, or when writing during the read operation. Fig. 18 Timer block diagram "1" P53/CNTR 1 "0" "10" P 52/ C N T R 0 Q Q T S P52 direction register P u l s e o u t p u t m o d e P l a t c h "0" "1" "10" P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 e d g e s w i t c h b i t Q Q T S "0" P62 direction register P62 latch "0" "1" TO U T o u t p u t e d g e s w i t c h b i t "0" TOUT output control bit P 62/ TO U T f XC I N ) "0" "1" TO U T o u t p u t c o n t r o l b i t φS O U R C φS O U R C "0" Count source selection bit (Note 1) φS O U R C E φSOURCE /16 φSOURCE /16 f XI N ) N o t e T i m e r 1 c o u n t s o u r c e s e l e c t i o n b i t N o t e C N T R 1 a c t i v e e d g e s w i t c h b i t Timer Y stop control bit Falling edge detection Period measurement mode Timer Y interrupt request P u l s e w i d t h H L c o n t i n u o u s l y m e a s u r e m e n t m o d e Rising edge detection Timer Y operating mode bits (Note 1) T i m e r X i n t e r r u p t r e q u e s t P u l s e o u t p u t m o d e Timer X stop control bit Timer X write control bitTimer X operat- ing mode bits CNTR0 active edge switch bit Timer 2 write control bit T i m e r 3 c o u n t s o u r c e s e l e c t i o n b i t N o t e Timer 2 interrupt request Timer 3 interrupt request Timer 2 count source selection bit (Note 1) Timer 1 interrupt request D a t a b u s Timer Y (low) (8) Timer Y (high) (8) T i m e r 3 l a t c h ( 8 ) Timer 3 (8) Timer 1 latch (8) T i m e r 1 ( 8 ) Timer 2 latch (8) Timer 2 (8) T i m e r X ( l o w ) ( 8 ) Timer X (high) (8) T i m e r X ( l o w ) l a t c h ( 8 ) Timer X (high) latch (8) T i m e r Y ( l o w ) l a t c h ( 8 )T i m e r Y ( h i g h ) l a t c h ( 8 ) Timer Y operating mode bits CNTR 0 interrupt request C N T R 1 i n t e r r u p t r e q u e s t φS O U R C E: r e p r e s e n t s t h e s u p p l y s o u r c e o f i n t e r n a l c l o c k φ. I t i s t h e o s c i l l a t i o n f r e q u e n c y o f XI N i n p u t i n t h e m i d d l e a n d h i g h s p e e d m o d e b u i l t i n r i n g o s c i l l a t o r i n t h e r i n g o s c i l l a t o r m o d e a n d s u b c l o c k i n t h e l o w s p e e d m o d e N o t e s 1 : I n t e r n a l c l o c k i n t h e l o w - s p e e d m o d e i s t h e s u b - c l o c k o s c i l l a t i o n / 2 . I n t e r n a l c l o c k i n t h e r i n g o s c i l l a t o r m o d e i s t h e i n t e r n a l r i n g o s c i l l a t o r o s c i l l a t i o n E x c e p t C N T R i n p u t t i m e r a n d t i m e r c o u n t s o u r c e s t h e c l o c k e x c e p t s y s t e m c l o c k c a n n o t b e u s e d a s t h e c o u n t s o u r c e : φS O U R C E c a n b e s e l e c t e d a s t h e t i m e r X c o u n t s o u r c e o n l y i n t h e p u l s e o u t p u t m o d e W r i t e t o t h e c o u n t s o u r c e s e l e c t i o n b i t e x c e p t i n t h e p u l s e o u t p u t m o d e

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. (1) Timer mode The timer counts the followings;

• f(XIN) (input frequency to XIN pin) divided by 16 in middle-, or high-speed mode
• f(XCIN ) (sub-clock oscillation frequency) divided by 16 in low- speed mode
• f(XROSC ) (built-in ring oscillator oscillation frequency) divided by 16 in ring oscillator mode (2) Pulse output mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted and f(XIN), f(ROSC ) or f(XCIN) can be selected for the count source. Except for them, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P5 2 direction register to output mode. (3) Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P52 direction register to input mode. (4) Pulse width measurement mode The count source is f(XIN)/16 in the middle-, or high-speed mode, f(ROSC )/16 in ring oscillator mode, and f(XCIN)/16 in the low-speed mode. If CNTR0 active edge switch bit is “0”, the timer counts while the input signal of CNTR0 pin is at “H ”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P52 direction regis- ter to input mode. Fig. 19 Structure of timer X mode register T i m e r X m o d e r e g i s t e r T X M a d d r e s s i n i t i a l v a l u e T i m e r X w r i t e c o n t r o l b i t W r i t e v a l u e i n l a t c h a n d t i m e r W r i t e v a l u e i n l a t c h o n l y C o u n t s o u r c e s e l e c t i o n b i t N o t e φS O U R C φS O U R C E t h i s c a n b e u s e d o n l y i n p u l s e o u t p u t m o d e N o t u s e d D o n o t w r i t e t o t h e s e b i t s T i m e r X o p e r a t i n g m o d e b i t s b b T i m e r m o d e P u l s e o u t p u t m o d e E v e n t c o u n t e r m o d e P u l s e w i d t h m e a s u r e m e n t m o d e C N T R 0 a c t i v e e d g e s w i t c h b i t C o u n t a t r i s i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m H o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e H p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e F a l l i n g e d g e a c t i v e f o r i n t e r r u p t C o u n t a t f a l l i n g e d g e i n e v e n t c o u n t e r m o d e S t a r t f r o m L o u t p u t i n p u l s e o u t p u t m o d e M e a s u r e L p u l s e w i d t h i n p u l s e w i d t h m e a s u r e m e n t m o d e R i s i n g e d g e a c t i v e f o r i n t e r r u p t T i m e r X s t o p c o n t r o l b i t C o u n t s t a r t C o u n t s t o p b7 b0 N o t e : φS O U R C E r e p r e s e n t s t h e o s c i l l a t i o n f r e q u e n c y o f XI N i n p u t i n t h e m i d d l e - a n d h i g h - s p e e d m o d e , b u i l t i n r i n g o s c i l l a t o r i n t h e r i n g o s c i l l a t o r m o d e a n d s u b c l o c k i n t h e l o w s p e e d m o d e D o n o t w r i t e t o t h e c o u n t s o u r c e s e l e c t i o n b i t e x c e p t t h e p u l s e o u t p u t m o d e G Timer X Write Control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, when the value is written in latch at the timer underflow, the value is loaded in the timer X and the latch at the same time. Also, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. I Note on CNTR0 interrupt active edge selection CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. I Note on count source selection bit Except the pulse output mode, write “0” to the count source selec- tion bit. When the timer X count source selection bit is set to “1”, as for the recommended operating condition of the main clock input fre- quency f(X IN), the rating value at the high-speed mode is applied. I Note on interrupt in pulse output mode When the count source selection bit is “1” in the pulse output mode, the timing when the timer X interrupt request occurs may be early or lately for one instruction cycle.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. (1) Timer mode The timer counts the followings;

• f(XIN)/16 in middle-, or high-speed mode
• f(XCIN)/16 in low-speed mode
• f(XROSC ) divided by 16 in ring oscillator mode (2) Period measurement mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. Ex- cept for the above-mentioned, the operation in period measure- ment mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corre- sponding port P53 direction register to input mode. (3) Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P53 direction register to input mode. (4) Pulse width HL continuously measure- ment mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P5 3 direction register to input mode. I Note on CNTR1 interrupt active edge selection CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 20 Structure of timer Y mode register Timer Y mode register (TYM : address 002816, initial value: 0016) b 7 b 0 N ot used (returns “0” when read) (Do not write “1” to these bits.) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR 1 active edge switch bit 0 : Count at rising edge in event counter mode Measure the falling edge to falling edge period in period measurement mode Falling edge active for CNTR 1 interrupt 1 : Count at falling edge in event counter mode Measure the rising edge period in period measurement mode Rising edge active for CNTR 1 interrupt Timer Y stop control bit 0 : Count start 1 : Count stop

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvert- ent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. G Timer 2 Write Control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. G Timer 2 Output Control When the timer 2 (T OUT ) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P62 shared with the port TOUT to the out- put mode. I Note on Timer 1 to Timer 3 When the count source of timers 1 to 3 is changed, the timer counting value may be changed large because a thin pulse is gen- erated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large be- cause a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 21 Structure of timer 123 mode register TO U T o u t p u t a c t i v e e d g e s w i t c h b i t S t a r t a t H o u t p u t S t a r t a t L o u t p u t TO U T o u t p u t c o n t r o l b i t TO U T o u t p u t d i s a b l e d TO U T o u t p u t e n a b l e d T i m e r w r i t e c o n t r o l b i t W r i t e d a t a i n l a t c h a n d c o u n t e r W r i t e d a t a i n l a t c h o n l y T i m e r c o u n t s o u r c e s e l e c t i o n b i t N o t e T i m e r o u t p u t φS O U R C T i m e r c o u n t s o u r c e s e l e c t i o n b i t T i m e r o u t p u t f XI N ) T i m e r c o u n t s o u r c e s e l e c t i o n b i t N o t e φS O U R C f XC I N ) N o t u s e d D o n o t w r i t e t o t h e s e b i t s T i m e r 1 2 3 m o d e r e g i s t e r T M a d d r e s s i n i t i a l v a l u e N ote: φSOURCE represents the oscillation frequency of XIN input in the middle- and high-speed mode, built-in ring oscillator in the ring oscillator mode, and sub-clock in the low-speed mode. b7 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Serial I/O The serial I/O function can be used only for clock synchronous se- rial I/O. For clock synchronous serial I/O, the transmitter and the receiver must use the same clock. When the internal clock is used, transfer is started by a write signal to the serial I/O register. [Serial I/O Control Register (SIOCON)] 001D16 The serial I/O control register contains 8 bits which control various serial I/O functions. I Notes on Serial I/O Write data to the serial I/O register only when the S CLK pin is “H”. Fig. 22 Structure of serial I/O control register Fig. 23 Block diagram of serial I/O function S e r i a l I / O c o n t r o l r e g i s t e r S I O C O N a d d r e s s D 1 i n i t i a l v a l u I n t e r n a l s y n c h r o n o u s c l o c k s e l e c t b i t s f XI N ) f XI N ) f XI N ) f XI N ) f XI N ) f XI N ) S e r i a l I O p o r t s e l e c t i o n b i t I O p o r t SO U SC L K s i g n a l o u t p u t P 55/ SO U T P c h a n n e l o u t p u t d i s a b l e b i t C M O S o u t p u t i n o u t p u t m o d e N c h a n n e l o p e n d r a i n o u t p u t i n o u t p u t m o d e T r a n s f e r d i r e c t i o n s e l e c t i o n b i t L S B f i r s t M S B f i r s t S y n c h r o n o u s c l o c k s e l e c t i o n b i t E x t e r n a l c l o c k I n t e r n a l c l o c k SR D Y o u t p u t s e l e c t i o n b i t I O p o r t P SR D Y s i g n a l o u t p u t b 2 b 1 b 0 D o n o t s e t N o t e : φS O U R C E r e p r e s e n t s t h e o s c i l l a t i o n f r e q u e n c y o f XI N i n p u t i n t h e m i d d l e a n d h i g h s p e e d m o d e b u i l t i n r i n g o s c i l l a t o r i n t h e r i n g o s c i l l a t o r m o d e a n d s u b c l o c k i n t h e l o w s p e e d m o d e " 1 " " 0 " " 0 " " 1 " " 0 " " 1 " SC L K 1 / 1 6 1 / 3 2 1 / 6 4 1 / 1 2 8 1 / 2 5 6 P 54/ SI N P 56/ SC L K P 55/ SO U T P 57/ SR D Y ( N o t e ) φS O U R C E D a t a b u s S e r i a l I / O i n t e r r u p t r e q u e s t Serial I/O port selection bit S e r i a l I / O c o u n t e r ( 3 ) S e r i a l I / O r e g i s t e r ( 8 ) S y n c h r o n o u s c i r c u i t S y n c h r o n o u s c l o c k s e l e c t i o n b i t E x t e r n a l c l o c k Internal synchronous clock select bits D i v i d e r P 56 l a t c h P 55 l a t c h N o t e : I t i s s e l e c t e d b y t h e s y n c h r o n o u s c l o c k s e l e c t i o n b i t , t h e SR D Y o u t p u t s e l e c t i o n b i t a n d t h e s e r i a l I O p o r t s e l e c t i o n b i t P 57 l a t c h ( N o t e )

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 24 Timing of serial I/O function D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 T r a n s f e r c l o c k ( N o t e 1 ) S e r i a l I / O o u t p u t SO U T S e r i a l I / O i n p u t SI N S e r i a l I / O r e g i s t e r w r i t e s i g n a l (Note 2) Serial I/O interrupt request bit set 1 : W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k , t h e d i v i d e r a t i o c a n b e s e l e c t e d b y s e t t i n g b i t s 0 t o 2 o f t h e s e r i a l I O c o n t r o l r e g i s t e r W h e n t h e i n t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k t h e SO U T p i n g o e s t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n W h e n t h e e x t e r n a l c l o c k i s s e l e c t e d a s t h e t r a n s f e r c l o c k a c o n t e n t o f t h e s e r i a l I O s h i f t r e g i s t e r i s c o n t i n u e d t o s h i f t d u r i n g i n p u t t i n g a t r a n s f e r c l o c k T h e SO U T p i n d o e s n o t g o t o h i g h i m p e d a n c e a f t e r t r a n s f e r c o m p l e t i o n N o t e s

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group A-D CONVERTER The functional blocks of the A-D converter are described below. G A-D Converter The conversion method of this A-D converter is the 8-bit resolution successive comparison method. This A-D converter has the ADKEY function for A-D conversion of “L” level analog input to ADKEY pin automatically. [A-D Conversion Register (AD)] 003516 The A-D conversion register is a read-only register that contains the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. After power on or system is released from reset, the value is unde- fined. [A-D Control Register (ADCON)] 003416 The A-D control register controls the A-D conversion process. Bits 0 to 2 of this register select specific analog input pins. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, then changes to “1” when the A- D conversion is completed. Writing “0” to this bit starts the A-D conversion. Bit 4 enables the ADKEY function. Writing “1” to this bit enables the ADKEY function. When this function is set to be valid, the analog input pin selection bits are invalid. Also, when the bit 4 is “1”, do not write “0” to bit 3 by program. Resistor ladder The resistor ladder divides the voltage between VCC and VSS by 256, and outputs the comparison voltages to the comparator. Channel Selector The channel selector selects one of the input ports AN7–AN 0. Comparator and Control Circuit The comparator and control circuit compare an analog input volt- age with the comparison voltage and store the result in the A-D conversion register. When an A-D conversion is completed, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. The comparator is constructed linked to a capacitor. The conver- sion accuracy may be low because the charge is lost if the conver- sion speed is not enough. Accordingly, set f(X IN) to at least 500kHz during A-D conversion in the middle- or high-speed mode. Also, do not execute the STP and WIT instructions during the A-D conversion. In the low-speed mode, since the A-D conversion is executed by the built-in self-oscillation circuit, the minimum value of f(X IN) fre- quency is not limited. Fig. 26 A-D converter block diagram Fig. 25 Structure of A-D control register A - D c o n t r o l r e g i s t e r A D C O N a d d r e s s i n i t i a l v a l u e A D c o n v e r s i o n c o m p l e t i o n b i t C o n v e r s i o n i n p r o g r e s s C o n v e r s i o n c o m p l e t e d A n a l o g i n p u t p i n s e l e c t i o n b i t s A N 0 A N 1 A N 2 A N 3 A N 4 A N 5 A N 6 A N 7 A D K E Y e n a b l e b i t ( N o t e ) D i s a b l e d E n a b l e d b 7 b 0 N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) D o n o t w r i t e t o t h e s e b i t s N o t e : W h e n t h e A D K E Y e n a b l e b i t i s “ 1 ” , a n a l o g i n p u t s e l e c t i o n b i t i s i n v a l i d . D o n o t e x e c u t e t h e A D c o n v e r s i o n w h i l e A D K E Y i s e n a b l e d E v e n i f A D K E Y i s e n a b l e d v a l u e s o f b i t s t o o f A D C O N a r e n o t a f f e c t e d VSS b 7b 0 A N 0/ A D K E A N 1/ A D K E AN 2/ADKEY 2 A N 3/ A D K E P 44/ A N 4 P 45/ A N 5 P 46/ A N 6 P 47/ A N 7 A D K E Y c o n t r o l c i r c u i t Comparator A-D control circuit A-D interrupt request D a t a b u s A-D control register A - D c o n v e r s i o n r e g i s t e r R e s i s t o r l a d d e r C h a n n e l s e l e c t o r VCC

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 27 Structure of ADKEY pin selection bits b P d a t a r e g i s t e r A d d r e s s i n i t i a l v a l u e N o t e A D K E Y p i n i s s e l e c t e d b y p o r t P d a t a r e g i s t e r T h e p r i o r i t y o f A D K E Y A D K E Y i s a s f o l l o w s A D K E Y0> A D K E Y1> A D K E Y2> A D K E A D K E s e l e c t i o n b i t I n v a l i d V a l i d A D K E s e l e c t i o n b i t I n v a l i d V a l i d A D K E s e l e c t i o n b i t I n v a l i d V a l i d A D K E s e l e c t i o n b i t I n v a l i d V a l i d P 44– P d a t a l a t c h ADKEY Control Circuit The ADKEY function is the function for A-D conversion of the “L” level analog input voltage input to the ADKEY pin automatically. This function can be used also in the state of STP and WIT.

• ADKEY Selection Two or more ADKEY pins can be selected by the low-order 4 bits of P4 data register. If “L” level input to an ADKEY pin is detected, other bits are set to “0” and only the corresponding ADKEY selection bit is set to “1”. As a result, the pin with “L” level input can be recognized.
• ADKEY Enable The ADKEY function is enabled by writing “1” to the ADKEY en- able bit. Surely, in order to enable ADKEY functin, set “1” to the ADKEY enable bit, after selecting the ADKEY pin. ADKEY becomes disabled automatically after the A-D conversion end by the ADKEY function. When the ADKEY enable bit of the A- D control register is “1”, the analog input pin selection bits become invalid. Please do not write “0” in the AD conversion completion bit by the program during ADKEY enabled state. [ADKEY Control Circuit] The pins which performs A-D conversion is selected with the rank- ing of ADKEY0, ADKEY1, ADKEY2, and ADKEY3 when there is an “L” level input simultaneously to two or more valid ADKEY pins. In order to obtain a more exact conversion result, by the A-D con- version with ADKEY, execute the following; ➀ set the input to the ADKEY pin into a steep falling waveform, ➁ stabilize the input voltage within 8 clock cycle (1 µs at f(X IN) = 8MHz) after the input voltage is under VIL, and ➂ maintain the input voltage until the completion of the A-D con- version. The threshold voltage with an actual ADKEY pin is the voltage be- tween VIH-VIL. In order not to make ADKEY operation perform superfluously in a noise etc., in the state of the waiting for an input, set the voltage of an ADKEY pin to V IH (0.9VCC ) or more. When the following operations are performed, the A-D conversion operation cannot be guaranteed.
• When the CPU mode register is operated during A-D conversion operation,
• When the AD conversion control register is operated during A-D conversion operation,
• When STP or WIT instructin is executed during A-D conversion operation,
• When the ADKEY pin selection bit is operated during A-D con- version operation at selecting ADKEY function, and
• Return operation by reset, STOP or WIT under A-D conversion operation at selecting ADKEY function is performed.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Definition of A-D converter accuracy The A-D conversion accuracy is defined below (refer to Figure 28).

• Relative accuracy ➀ Zero transition voltage (V0T) This means an analog input voltage when the actual A-D con- version output data changes from “0” to “1.” ➁ Full-scale transition voltage (V FST ) This means an analog input voltage when the actual A-D con- version output data changes from “255” to ”254.” ➂ Linearity error This means a deviation from the line between V 0T and VFST of a converted value between V0T and VFST . ➃ Differential non-linearity error This means a deviation from the input potential difference re- quired to change a converter value between V 0T and VFST by 1 LSB at the relative accuracy.
• Absolute accuracy This means a deviation from the ideal characteristics between 0 to VREF (VCC in 38C1 Group) of actual A-D conversion characteristics. VREF (VCC ) V254VnV1V0 Vn+1 n n 255 b a c O u t p u t d a t a Differential non-linearity error = Linearity error = [LSB] c a b–a a [ L S B ] Actual A-D conversion characteristics a : 1 L S B b y r e l a t i v e a c c u r a c y b Vn Vn c D i f f e r e n c e b e t w e e n i d e a l Vn a n d a c t u a l Vn Zero transition voltage (V0T) Analog voltage Full-scale transition voltage (VFST ) Ideal line of A-D conversion between V0–V254 Fig. 28 Definition of A-D conversion accuracy VFST –V0T 254 VREF* 256 Vn: Analog input voltage when the output data changes from “n” to
• 1LSB at relative accuracy → (V)
• 1LSB at absolute accuracy → (V) * VREF = VCC in the 38C1 Group.

control circuit consisting of the following.

• LCD display register
• Segment output enable register
• LCD mode register
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit A maximum of 25 segment output pins and 4 common output pins can be used. Up to 100 pixels can be controlled for LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, Fig. 29 Structure of segment output enable register and LCD mode register the segment output enable register and the LCD display register, the LCD drive control circuit starts reading the display data auto- matically, performs the bias control and the duty ratio control, and displays the data on the LCD panel.

Table 7. Maximum number of display pixels at each duty ratio N otes 1: Set the direction register of the port which is also used as the segment output enabled pin to “1”. 2: When “1 duty” is selected by the duty ratio selection bit, set the bias control bit to “1”. 3: LCDCK is a clock for a LCD timing controller. built-in ring oscillator in the ring oscillator mode, and sub-clock in the low-speed mode.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 30 Block diagram of LCD controller/driver f ( XC I C O M C O M C O M C O M VS S VL VL VL P 03/ S E G P 02/ S E G P 01/ S E G P 00/ S E G " 1 " 0 L C D C K D a t a b u s T i m i n g c o n t r o l l e r L C D d i v i d e r A d d r e s s A d d r e s s L C D C K c o u n t s o u r c e s e l e c t i o n b i t L C D c i r c u i t d i v i d e r d i v i s i o n r a t i o s e l e c t i o n b i t s B i a s c o n t r o l b i tL C D e n a b l e b i t D u t y r a t i o s e l e c t i o n b i t s S e l e c t o r C o m m o n d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r B i a s c o n t r o l C o m m o n d r i v e r C o m m o n d r i v e r C o m m o n d r i v e r L C D d i s p l a y r e g i s t e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e g m e n t d r i v e r S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r S e l e c t o r φs o u r c N o t e A c c o r d i n g t o t h e o p e r a t i o n m o d e φs o u r c e i n d i c a t e s t h e o s c i l l a t i o n f r e q u e n c y s h o w n b e l o w

• I n m i d d l e o r h i g h s p e e d m o d e XI N i n p u t
• I n r i n g o s c i l l a t o r m o d e b u i l t i n r i n g o s c i l l a t o r a n d
• I n l o w s p e e d m o d e o s c i l l a t i o n f r e q u e n c y o f s u b c l o c k S E G P 26/ S E G P 27/ S E G

Table 8. Bias control and applied voltage to VL1–VL3 in Table 8 according to the bias value. Table 9. Duty ratio control and common pins used Notes 1: Set COM 1, COM 2 and COM 3 to be open. 2: Set COM 2 and COM 3 to be open.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group (frequency of count source for LCDCK) (divider division ratio for LCD)f(LCDCK)= f(LCDCK) duty ratioFrame frequency= Fig. 32 LCD display register map LCD Display register Address 001016 to 001C16 is the LCD display register. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated in- ternally and the frame frequency can be determined with the fol- lowing equation; COM3 C O M O M 1C O M 0C O M 3C O M 2C O M 1C O M 0 C 1 001816 001516 001616 001716 001116 001216 001316 SEG 11 S E G 1 S E G 2 S E G 2 SEG 13 SEG 15 SEG 17 S E G 1 SEG 3 SEG 5 SEG 7 S E G 9 S E G 0 SEG 10 SEG 12 SEG 14 SEG 16 S E G 1 S E G 2 S E G 2 S E G 2 SEG 2 SEG 4 SEG 6 S E G 8 Bits Address 765 21

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 33 LCD drive waveform (1/2 bias, 1/1 bias) VL3 VL2=VL1 VSS VL3 VSS C O M 0 C O M 1 C O M 2 C O M 3 SEG 0 C O M 3 C O M 2 C O M 1 C O M 0 COM 3 C O M 2 C O M 1 COM 0 VL3 VL2=VL1 VSS VL3 VSS C O M 0 C O M 1 C O M 2 SEG 0 C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 1 C O M 0 C O M 2 C O M 0 C O M 1 S E G 0 VL VL 2= VL VS S VL VS S C O M 1 C O M 0 COM 1 COM 0 C O M 1 COM 0 COM 1 COM 0 C O M 0 S E G 0 VL VL 2= VL 1= VS S VL VS S I n t e r n a l l o g i c L C D C K t i m i n g 1 / 4 d u t y Voltage level O F FO NO F FO N 1 / 3 d u t y O F FO NO N O F FO NO F F 1 / 2 d u t y O F FON O F FO NO F FON OFF O N 1 / 1 d u t y ( 1 / 1 b i a s ) O F F O N

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 34 LCD drive waveform (1/3 bias) VL3 VS S C O M 0 C O M 1 C O M 2 C O M 3 S E G 0 COM 3 C O M 2 COM 1 COM 0 C O M 3 C O M 2 COM 1 C O M 0 C O M 0 C O M 1 C O M 2 S E G 0 C O M 0 C O M 1 S E G 0 VL VL VS S VL VL VL VS S VL VL VSS VL VL VS S VL VL VS S COM 0 C O M 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 C O M 0 COM 1 COM 0 COM 1 C O M 0 C O M 1 COM 0 I n t e r n a l l o g i c L C D C K t i m i n g 1/4 duty Voltage level O F FO N O F FO N 1/3 duty OFFO NO NO F FO NO F F 1/2 duty OFFO NO F F O N O F FON O F FO N

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 35 Structure of clock output control register OTHER FUNCTION REGISTERS G φ clock output function The internal clock φ can be output from port P63 by setting the φ output control register. At φ clock output, set “1” to the bit 3 of the port P6 direction regis- ter. b φ output control register (CKOUT: address 002A16, initial value: 0016) φ output control bit 00 : 01 : 10 : 11 : P o r t f u n c t i o n φ fr e q u e n c y s i g n a l o u t p u t X C I N f r e q u e n c y s i g n a l o u t p u t N o t a v a i l a b l e N o t u s e d ( r e t u r n s “ 0 ” w h e n r e a d ) D o n o t w r i t e t o t h i s b i t b7 b0 DB 0 data stored DB 1 data stored DB 2 data stored DB 3 data stored DB 4 data stored DB 5 data stored DB 6 data stored DB 7 data stored b 7b 0 RRF register (RRFR: address 002F16, initial value: 0016) D d a t a s t o r e d D d a t a s t o r e d D d a t a s t o r e d D d a t a s t o r e d D d a t a s t o r e d D d a t a s t o r e d D d a t a s t o r e d D d a t a s t o r e d Temporary data registers 0, 1, 2 (TD0, TD1, TD2: address 002C16, 002D16, 002E16, initial value: 0016) G Temporary data register The temporary data register (addresses 002C16 to 002E16) is the 8-bit register and does not have the control function. It can be used to store data temporarily. It is initialized after reset. G RRF register The RRF register (address 002F 16) is the 8-bit register and does not have the control function. As for the value written in this register, high-order 4 bits and low- order 4 bits interchange. It is initialized after reset. Fig. 36 Structure of temporary data register, RRF register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 37 Example of reset circuit RESET CIRCUIT To reset the microcomputer, RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H ” level (the power source voltage should be between VCC (min.) and 5.5 V), reset is released. After the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC16 (low-order byte). Make sure that the re- set input voltage is less than 0.2 VCC for VCC of VCC (min.). Fig. 38 Reset Sequence P o w e r o n P o w e r s o u r c e v o l t a g e Reset input voltage P o w e r s o u r c e v o l t a g e d e t e c t i o n c i r c u i t

0.2 VCC

N o t e : R e s e t r e l e a s e v o l t a g e VC C = 3 . 0 V (Note) R E S E T S Y N C φ ROSC F F F C FFFD AD H, AD L AD L ???? AD H R O S C : a b o u t 3 5 c l o c k c y c l e s Notes 1 : f(ROSC) and φ are in the relationship : f(ROSC) = 8•f(φ) 2 : A question mark (?) indicates an undefined status that depends on the previous status. Reset address from vector table Internal reset Address D a t a

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 39 Internal state of microcomputer immediately after reset N ote: The contents of all other registers and RAM are undefined after reset, so they must be initialized by software. ✕ : Undefined R e g i s t e r c o n t e n t sAddress 0 0 0 51 0 0 0 71 0 0 0 91 0 0 0 B1 0 0 0 D 1 0 0 1 D 1 0 0 2 01 0 0 2 11 0 0 2 21 0 0 2 31 002416 002516 0 0 2 61 002716 002816 0 0 2 91 0 0 2 A1 0 0 2 C 1 0 0 2 D 1 0 0 2 E1 0 0 2 F1 0 0 3 31 0 0 3 41 0 0 3 81 0 0 3 91 0 0 3 A1 003B16 0 0 3 C 1 003D 16 ( P S ) ( P C H ) (PCL) ( 1 0 ) (11) ( 1 2 ) ( 1 3 ) ( 1 4 ) (15) (16) (17) (18) ( 1 9 ) ( 2 0 ) ( 2 1 ) ( 2 2 ) ( 2 3 ) ( 2 4 ) ( 2 5 ) ( 2 6 ) ( 2 7 ) ( 2 8 ) (29) ( 1 ) ( 2 ) ( 3 ) ( 4 ) ( 5 ) ( 6 ) ( 7 ) ( 8 ) ( 9 ) T i m e r Y l o w P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r T i m e r Y h i g h S e r i a l I O c o n t r o l r e g i s t e r T i m e r X h i g h T i m e r X l o w T i m e r X m o d e r e g i s t e r Timer Y mode register T i m e r m o d e r e g i s t e r A-D control register Segment output enable register L C D m o d e r e g i s t e r I n t e r r u p t e d g e s e l e c t i o n r e g i s t e r C P U m o d e r e g i s t e r I n t e r r u p t r e q u e s t r e g i s t e r Interrupt request register 2 I n t e r r u p t c o n t r o l r e g i s t e r Interrupt control register 2 P r o c e s s o r s t a t u s r e g i s t e r Program counter P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r P o r t P d i r e c t i o n r e g i s t e r Timer 1 T i m e r T i m e r 0 01 6816 0016 0716 0 81 0 01 0 01 0 01 F F1 101 F F1 F F1 F F1 0 01 0 01 0 01 0 01 0 01 0 01 F F1 F F1 0016 C o n t e n t s o f a d d r e s s F F F D 1 C o n t e n t s o f a d d r e s s F F F C 1 T e m p o r a r y d a t a r e g i s t e r φ output control register T e m p o r a r y d a t a r e g i s t e r 0 01 0016 0016 0 01 0016 (30) ( 3 1 ) (32) ( 3 3 ) 0016 0016 0016 0016 Temporary data register 2 R R F r e g i s t e r PULL register 003E16 0 0 3 F1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group CLOCK GENERATING CIRCUIT The oscillation circuit of 38C1 group can be formed by connecting an oscillator, capacitor and resistor between XIN and XOUT (XCIN and XCOUT ). To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The clocks that are externally generated cannot be directly input to XCIN . Use the circuit con- stants in accordance with the oscillator manufacturer's recom- mended values. No external resistor is needed between X IN and XOUT since a feed-back resistor exists on-chip. However, a 10 MΩ external feed-back resistor is needed between XCIN and XCOUT . Immediately after reset is released, only the built-in ring oscillator starts oscillating, X IN -XOUT oscillation stops oscillating, and XCIN and XCOUT pins function as I/O ports. Operation mode (1) Ring oscillator mode The internal clock φ is the built-in ring oscillator oscillation divided by 8. (2) Middle-speed mode The internal clock φ is the frequency of XIN divided by 8. (3)High-speed mode The internal clock φ is half the frequency of XIN. (4) Low-speed mode The internal clock φ is half the frequency of XCIN. After reset release and when system returns from the stop mode, the ring oscillator mode is selected. Refer to the clock state transition diagram for the setting of transi- tion to each mode. The X IN–X OUT oscillation is controlled by the bit 5 of CPUM, and the sub-clock oscillation is controlled by the bit 4 of CPUM. When the mode is switched to the ring oscillator mode, set the bit 3 of CPUM to “1”. In the ring oscillator mode, the oscillation by the oscillator can be stopped. In the low-speed mode, the power consumption can be reduced by stopping the X IN–XOUT oscillation. When the mode is switched from the ring oscillator mode to the low-speed mode, the built-in ring oscillator is stopped. Set enough time for oscillation to stabilize by programming to re- start the stopped oscillation and switch the operation mode. Also, set enough time for oscillation to stabilize by programming to switch the timer count source . Note: If you switch the mode between ring oscillator mode, middle/high-speed mode and low-speed mode, stabilize both X IN and XCIN oscillations. Especially be careful imme- diately after power-on and at returning from stop mode. Re- fer to the clock state transition diagram for the setting of transition to each mode. Set the frequency in the condition that f(X IN) > 3•f(XCIN). When the middle- and high-speed mode are not used (XIN- X OUT oscillation and external clock input are not performed), connect XIN to VCC through a resistor. Fig. 40 Oscillator circuit Fig. 41 External clock input circuit Oscillation Control (1) Stop mode Set the timer 1 interrupt enable bit to disabled (“0”) before execut- ing the STP instruction. If the STP instruction is executed, the in- ternal clock φ stops at an “H ” level, and main clock, ring oscillator and sub-clock oscillators stop. In this time, “01 16” is set to timer 1 and the ring oscillator is con- nected forcibly for the system clock and the timer 1 count source. Also, the bits of the timer 123 mode register except bit 4 are cleared to “0”. When an external interrupt is received, the clock oscillated before stop mode and the ring oscillator start oscillating. However, bit 3 of CPUM is set to “1” forcibly and system returns to the ring oscillator mode. Tthe internal clock φ is supplied to the CPU after timer 1 underflows. However, when the system clock is switched from the ring oscillator to main clock and sub-clock, generate the wait time enough for oscillation stabilizing by program. (2) Wait mode If the WIT instruction is executed, only the internal clock φ stops at an “H ” level. The states of main clock, ring oscillator and sub-clock are the same as the state before the executing the WIT instruction and the oscillation does not stop. Since the internal clock φ re- starts when an interrupt is received, the instruction is executed im- mediately. XC I N C IN C OUTC C I N C COUT R f R d XO U TXI NXC O U T E x t e r n a l o s c i l l a t i o n c i r c u i t O p e n VC C VS S C C I N R f R d C C O U T XC I N XOUTXI NXC O U T

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 42 Clock generating circuit block diagram S R Q XI N - XO U T o s c i l l a t i o n s t o p b i t C P U M B I T XI N XO U T XC O U TXC I N Port Xc switch bit CPUM BIT4 “ 0 ” “ 1 ” M a i n c l o c k s e l e c t i o n b i t C P U M B I T Ring oscillator 1 / 2 1/4 1 / 2 M a i n c l o c k d i v i s i o n r a t i o s e l e c t i o n b i t C P U M B I T Main clock selection bit CPUM BIT3 S R Q Timer 1 S R Q WIT instruction T i m i n g φ I n t e r n a l c l o c k STP instruction Interrupt request Reset Timer 1 count source selection bit T123M BIT 5 Internal system clock selection bit CPUM BIT7 N o t e : W h e n X c o s c i l l a t i o n i s s e l e c t e d f o r i n t e r n a l s y s t e m c l o c k , s e t t h e p o r t X c s w i t c h b i t t o “ 1 ” . I n t e r r u p t d i s a b l e f l a g I S T P i n s t r u c t i o n I n t e r n a l s y s t e m c l o c k s e l e c t i o n b i t N o t e C P U M B I T 7“0” “ 1 ” “1”“ 0” “ 1 ” “0” “0” “1” “ 0 ” “ 1 ” “ 0 ” “ 1 ”

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group Fig. 43 State transitions of system clock R e s e t r e l e a s e XIN stop XCIN stop φ=f(ROSC)/8 CM 7=0 CM 6=1 (Note 5) CM 5=1 CM 4=0 CM 3=1 XIN stop XCIN oscillation φ=f(ROSC)/8 CM 7=0 CM 6=1 (Note 5) CM 5=1 CM 4=1 CM 3=1 XI N o s c i l l a t i o n XC I N s t o p f R O S C C M 7= C M 6= N o t e C M 5= C M 4= C M 3= XI N o s c i l l a t i o n XC I N o s c i l l a t i o n φ=f(ROSC)/8 CM 7=0 CM 6=1(Note 5) CM 5=0 CM 4=1 CM 3=1 C M 4 C M 4 C M 4 C M 5C M 5 C M 5 XI N s t o p XC I N o s c i l l a t i o n k H z C M 7= C M 6= C M 5= C M 4= C M 3= N o t e XI N o s c i l l a t i o n XC I N o s c i l l a t i o n k H z C M 7= C M 6= N o t e C M 5= C M 4= C M 3= N o t e CM 6 C M 6 C M 5 CM 5 XIN oscillation XCIN stop M H z C M 7= C M 6= C M 5= C M 4= C M 3= XIN oscillation XCIN oscillation φ=1MHz CM 7=0 CM 6=1 CM 5=0 CM 4=1 CM 3=0 C M 4 XI N o s c i l l a t i o n XC I N s t o p M H z C M 7= C M 6= N o t e C M 5= C M 4= C M 3= XI N o s c i l l a t i o n XC I N o s c i l l a t i o n φ=4MHz CM 7=0 CM 6=0 (Note 5) CM 5=0 CM 4=1 CM 3=0 CM 4 C M 7 CM 7 C M 7 XI N o s c i l l a t i o n XC I N o s c i l l a t i o n k H z C M 7= C M 6= C M 5= C M 4= C M 3= N o t e R i n g o s c i l l a t o r m o d e L o w - s p e e d m o d e Middle-speed mode High-speed mode C M 3 b7 b 3 C M 3 C M 6 CM 6 C M 7 N o t e s 1 : S w i t c h t h e m o d e b y t h e a r r o w s s h o w n b e t w e e n t h e m o d e b l o c k s . T h e a l l m o d e s c a n b e s w i t c h e d t o t h e s t o p m o d e o r t h e w a i t m o d e T i m e r a n d L C D o p e r a t e i n t h e w a i t m o d e S y s t e m i s r e t u r n e d t o t h e s o u r c e m o d e w h e n t h e w a i t m o d e i s e n d e d C M 4, C M 5 a n d C M 6 a r e r e t a i n e d i n t h e s t o p m o d e S y s t e m i s r e t u r n e d t o t h e r i n g o s c i l l a t o r m o d e C M 3= C M 7= W h e n t h e s t o p m o d e i s e n d e d s e t t h e o s c i l l a t i o n s t a b i l i z i n g w a i t t i m e i n t h e r i n g o s c i l l a t o r m o d e W h e n t h e s t o p m o d e i s e n d e d s e t t h e i n i t i a l v a l u e t o C M 6 C M 6= E x e c u t e t h e t r a n s i t i o n a f t e r t h e o s c i l l a t i o n u s e d i n t h e d e s t i n a t i o n m o d e i s s t a b i l i z e d W h e n s y s t e m g o e s t o r i n g o s c i l l a t o r m o d e t h e o s c i l l a t i o n s t a b i l i z i n g w a i t t i m e i s n o t n e e d e d D o n o t g o t o t h e h i g h s p e e d m o d e f r o m t h e r i n g o s c i l l a t o r m o d e W r i t e t h e p r o p e r v a l u e s f o r d e s t i n a t i o n m o d e b e f o r e h a n d T h e e x a m p l e a s s u m e s t h a t M H z i s b e i n g a p p l i e d t o t h e XI N p i n a n d k H z t o t h e XC I N p i n f R O S C i n d i c a t e s t h e o s c i l l a t i o n f r e q u e n c y o f r i n g o s c i l l a t o r Main clock selection bit 0: XIN input signal 1: Ring oscillator Port Xc switch bit 0: I/O port function (Oscillation stop) 1: X CIN, XCOUT function XIN–XOUT oscillation stop bit 0: Oscillating 1: Stopped Main clock division ratio selection bit 0: f(X IN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0: Main clock selected (middle-/high-speed and ring oscillator mode) 1: X CIN–XCOUT selected (low-speed mode) C P U m o d e r e g i s t e r C P U M a d d r e s s i n i t i a l v a l u e

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupt The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt re- quest register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:

• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit en- able bit, the receive enable bit, and the SRDY output enable bit to “1”. In serial I/O, the SOUT pin goes to high impedance state after transmission is completed. A-D Converter The comparator is constructed linked to a capacitor. The conver- sion accuracy may be low because the charge is lost if the conver- sion speed is not enough. Accordingly, set f(X IN) to at least 500kHz during A-D conversion in the middle- or high-speed mode. Also, do not execute the STP or WIT instruction during an A-D conversion. In the low-speed mode, since the A-D conversion is executed by the built-in self-oscillation circuit, the minimum value of f(X IN) fre- quency is not limited. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group NOTES ON USE VL3 pin When LCD drive control circuit is not used, connect VL3 to VCC . Countermeasures against noise (1) Shortest wiring length ➀ Wiring for RESET pin Make the length of wiring which is connected to the RESET pin as short as possible. Especially, connect a capacitor across the RESET pin and the V SS pin with the shortest possible wiring (within 20mm). G Reason The width of a pulse input into the RESET pin is determined by the timing necessary conditions. If noise having a shorter pulse width than the standard is input to the RESET pin, the reset is released before the internal state of the microcomputer is com- pletely initialized. This may cause a program runaway. Fig. 45 Wiring for clock I/O pins (2) Connection of bypass capacitor across V SS line and VCC line In order to stabilize the system operation and avoid the latch-up, connect an approximately 0.1 µF bypass capacitor across the VSS line and the VCC line as follows:

• Connect a bypass capacitor across the VSS pin and the VCC pin at equal length.
• Connect a bypass capacitor across the VSS pin and the VCC pin with the shortest possible wiring.
• Use lines with a larger diameter than other signal lines for VSS line and VCC line.
• Connect the power source wiring via a bypass capacitor to the VSS pin and the VCC pin. Fig. 44 Wiring for the RESET pin ➁ Wiring for clock input/output pins
• Make the length of wiring which is connected to clock I/O pins as short as possible.
• Make the length of wiring (within 20 mm) across the grounding lead of a capacitor which is connected to an oscillator and the V SS pin of a microcomputer as short as possible.
• Separate the VSS pattern only for oscillation from other VSS patterns. G Reason If noise enters clock I/O pins, clock waveforms may be de- formed. This may cause a program failure or program runaway. Also, if a potential difference is caused by the noise between the V SS level of a microcomputer and the VSS level of an oscil- lator, the correct clock will not be input in the microcomputer. Fig. 46 Bypass capacitor across the VSS line and the VCC line RESETReset circuit Noise VSSVSS Reset circuit VSS RESET VSS N.G. O.K. Noise XIN XOUT VSS XIN XOUT VSS N.G. O.K. VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines VSS VCC /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines /LiteDiagLines/LiteDiagLines N.G. O.K.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 38C1 Group (3) Oscillator concerns In order to obtain the stabilized operation clock on the user system and its condition, contact the oscillator manufacturer and select the oscillator and oscillation circuit constants. Be careful espe- cially when range of voltage or/and temperature is wide. Also, take care to prevent an oscillator that generates clocks for a microcomputer operation from being affected by other signals. ➀ Keeping oscillator away from large current signal lines Install a microcomputer (and especially an oscillator) as far as possible from signal lines where a current larger than the toler- ance of current value flows. G Reason In the system using a microcomputer, there are signal lines for controlling motors, LEDs, and thermal heads or others. When a large current flows through those signal lines, strong noise oc- curs because of mutual inductance. ➁ Installing oscillator away from signal lines where potential levels change frequently Install an oscillator and a connecting pattern of an oscillator away from signal lines where potential levels change frequently. Also, do not cross such signal lines over the clock lines or the signal lines which are sensitive to noise. G Reason Signal lines where potential levels change frequently (such as the CNTR pin signal line) may affect other lines at signal rising edge or falling edge. If such lines cross over a clock line, clock waveforms may be deformed, which causes a microcomputer failure or a program runaway. ➀ Keeping oscillator away from large current signal lines ➁ Installing oscillator away from signal lines where potential levels change frequently Fig. 48 Wiring for the VPP pin of One Time PROM Fig. 47 Wiring for a large current signal line/Wiring of signal lines where potential levels change frequently XI N XO U T VS S M M i c r o c o m p u t e r Mutual inductance Large current GND XI N XO U T VS S C N T RD o n o t c r o s s N.G. (4) Analog input The analog input pin is connected to the capacitor of a voltage comparator. Accordingly, sufficient accuracy may not be obtained by the charge/discharge current at the time of A-D conversion when the analog signal source of high-impedance is connected to an analog input pin. In order to obtain the A-D conversion result stabilized more, please lower the impedance of an analog signal source, or add the smoothing capacitor to an analog input pin. (5) Difference of memory type and size When Mask ROM and PROM version and memory size differ in one group, actual values such as an electrical characteristics, A-D conversion accuracy, and the amount of -proof of noise incorrect operation may differ from the ideal values. When these products are used switching, perform system evalua- tion for each product of every after confirming product specification. (6) Wiring to V PP pin of One Time PROM version Connect an approximately 5 kΩ resistor to the VPP pin the shortest possible in series and also to the VSS pin. Note: Even when a circuit which included an approximately 5 kΩ resistor is used in the Mask ROM version, the microcom- puter operates correctly. G Reason The V PP pin of the One Time PROM version is the power source input pin for the built-in PROM. When programming in the built-in PROM, the impedance of the V PP pin is low to allow the electric current for writing flow into the built-in PROM. Because of this, noise can enter easily. If noise enters the VPP pin, abnormal in- struction codes or data are read from the built-in PROM, which may cause a program runaway. C N VS S/ VP P VSS About 5kΩ

Table 10. Programming adapter Figure 49 is recommended to verify programming. expose to 150 °C exceeding 100 hours.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change.

ELECTRICAL CHARACTERISTICS

Table 11 Absolute maximum ratings Parameter Power source voltage Input voltage P0 0–P07, P20–P27, P30–P34, P44–P47, P50–P57, P60–P64 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Input voltage AN0–AN 3 Input voltage CNVSS (Mask ROM version) Input voltage CNVSS (One Time PROM version) Output voltage P20–P27 Output voltage P30–P34, P44–P47, P50–P57, P60–P64 Output voltage SEG0–SEG 24 Output voltage XOUT Power dissipation Operating temperature Storage temperature Symbol V CC VI VI VI VI VI VI VI VI VO VO VO VO Pd Topr Tstg Conditions All voltages are based on Vss. Output transistors are cut off. At output port At segment output Ta = 25°C Ratings –0.3 to 6.5 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to 6.5 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 13 –0.3 to VCC +0.3 –0.3 to VL3+0.3 –0.3 to VCC +0.3 –0.3 to VL3+0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 Unit V V V V V V V V V V V V V V mW

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Recommended Operating Conditions Table 12 Recommended operating conditions (Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted) Power source voltage High-speed mode f(X IN) ≤ 8 MHz (Note 1) f(X IN) ≤ 6 MHz Mask ROM version High-speed mode f(X IN) ≤ 4 MHz Middle-speed mode f(XIN) ≤ 8 MHz f(XIN) ≤ 6 MHz Low-speed, ring oscillator operation mode One Time PROM version High-speed mode f(X IN) ≤ 4 MHz Middle-speed mode f(XIN) ≤ 8 MHz f(XIN) ≤ 6 MHz Low-speed, ring oscillator operation mode When oscillation starts Mask ROM version (Note 2) One Time PROM version Power source voltage LCD power source voltage Analog input voltage AN0–AN 7 “H” input voltage P00–P07, P20–P27, P44–P47, P55, P57, P62–P64 “H” input voltage P6 0, P61 (CM4=0) “H” input voltage P3 0–P34, P50–P54, P56 “H” input voltage RESET “H” input voltage X IN “L” input voltage P00–P07, P20–P27, P44–P47, P55, P57, P62–P64 “L” input voltage P6 0, P61 (CM4=0) “L” input voltage P3 0–P34, P50–P54, P56 “L” input voltage RESET “L” input voltage X IN VCC VSS CNV SS VL3 V IA VIH VIH VIH VIH VIH VIL VIL VIL VIL VIL Limits V V V V V V V V V V V V V V V V V V V V V V V V V V Parameter Min. 4.0 3.0 2.0 2.0 1.8 1.8 2.5 2.5 2.2 2.2 2.2 2.5 2.5 V SS 0.7VCC 0.7VCC 0.8VCC 0.8VCC 0.8VCC Typ. 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 5.0 Max. 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 5.5 0.2V CC VCC VCC VCC VCC VCC VCC 0.3VCC 0.3VCC 0.2VCC 0.2VCC 0.2VCC Symbol Unit Notes 1: When the A-D converter is used, refer to the recommended operating condition for A-D conversion. 2: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially, be careful that an oscillation start of the high-frequency oscillator may be difficult at low-voltage. Until the oscillation is stabilized, wait in the ring oscillator mode.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. “H” total peak output current (Note 1) P20–P27, P30–P34 “H” total peak output current (Note 1) P44–P47, P50–P57, P60–P64 “L” total peak output current (Note 1) P20–P27, P30–P34 “L” total peak output current (Note 1) P44–P47, P50–P57, P60–P64 “H” total average output current (Note 1) P20–P27, P30–P34 “H” total average output current (Note 1) P44–P47, P50–P57, P60–P64 “L” total average output current (Note 1) P20–P27, P30–P34 “L” total average output current (Note 1) P44–P47, P50–P57, P60–P64 “H” peak output current (Note 2) P20–P27 “H” peak output current (Note 2) P30–P34 “H” peak output current (Note 2) P44–P47, P50–P57, P60–P64 “L” peak output current (Note 2) P20–P27 “L” peak output current (Note 2) P30–P34 “L” peak output current (Note 2) P44–P47, P50–P57, P60–P64 “H” average output current (Note 3) P20–P27 “H” average output current (Note 3) P30–P34 “H” average output current (Note 3) P44–P47, P50–P57, P60–P64 “L” average output current (Note 3) P20–P27 “L” average output current (Note 3) P30–P34 “L” average output current (Note 3) P44–P47, P50–P57, P60–P64 ΣIOH(peak) ΣIOH(peak) ΣIOL(peak) ΣIOL(peak) ΣIOH(avg) ΣIOH(avg) ΣIOL(avg) ΣIOL(avg) IOH(peak) IOH(peak) IOH(peak) IOL(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOH(avg) IOL(avg) IOL(avg) IOL(avg) Limits mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA Parameter Min. Typ. Max.Symbol Unit –40 –60 –20 –30 –1.0 –2.5 –2.5 2.5 Table 13 Recommended operating conditions (Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an average value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is average value measured over 100 ms.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Table 14 Recommended operating conditions (Vcc = 1.8 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted) Timer X and Timer Y Input frequency (duty cycle 50%) Main clock input frequency (duty cycle 50%) (Note 1) Sub-clock input oscillation frequency (Note 2) (Note 4) (duty cycle 50%) f(CNTR f(CNTR1) f(XIN) f(XCIN) Limits MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz MHz kHz Parameter Min. Typ. 32.768 Max. 4.0 V CC 5✕ VCC –8 2✕ VCC –3 10✕ VCC –19 8.0 2✕ VCC 4✕ VCC –6 8.0 6.0 Symbol Unit (Mask ROM version: 2.0V ≤ VCC ≤ 4.0 V) (One Time PROM version: 3.0 V ≤ VCC ≤ 4.0 V) (Mask ROM version: VCC ≤ 2.0 V) (One Time PROM version: 2.5 V ≤ VCC ≤ 3.0 V) (One Time PROM version: VCC ≤ 2.5 V) High-speed mode (4.0 V < VCC ≤ 5.5 V) High-speed mode (Mask ROM version: 2.0V ≤ V CC ≤ 4.0 V) (One Time PROM version: 3.0 V ≤ VCC ≤ 4.0 V) High-speed mode (One Time PROM version: 2.5 V ≤ VCC ≤ 3.0 V) Middle-speed mode (Note 3) (Note 4) (Mask ROM version: 2.0 V ≤ VCC ≤ 5.5 V) (One Time PROM version: 2.5 V ≤ VCC ≤ 5.5 V) Middle-speed mode (Note 3) (Note 4) Notes 1:When the A-D converter is used, refer to the recommended operating condition for A-D conversion. 2: When using the microcomputer in low-speed mode, set the clock input oscillation frequency on condition that f(XCIN) < f(XIN)/3. 3: When the timer X count source selection bit is set to “1”, as for the recommended operating condition of the main clock input frequency f(XIN), the rating value at the high-speed mode is applied. 4: Oscillation start voltage and oscillation start time depend on the oscillator, the circuit constant and temperature. Especially, be careful that an oscillation start of the high-frequency oscillator may be difficult at low-voltage. Until the oscillation is stabilized, wait in the ring oscillator mode. Condition

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. IOH = –1.0 mA IOH = –0.2 mA VCC = 1.8 to 5.5 V (Note) IOH = –2.5 mA IOH = –0.5 mA VCC = 1.8 to 5.5 V (Note) IOL = 2.5 mA IOL = 0.5 mA VCC = 1.8 to 5.5 V (Note) IOL = 5 mA IOL = 1 mA VCC = 1.8 to 5.5 V (Note) IOL = 15 mA IOL = 3 mA VCC = 1.8 to 5.5 V (Note) VI = VCC VI = VSS Pull-down “OFF” VCC = 5.0 V, VI = VCC Pull-down “ON” V CC = 3.0 V, VI = VCC Pull-down “ON” V I = VCC VI = VCC VI = VSS VI = VSS Pull-up “OFF” V CC = 5.0 V, VI = VSS Pull-up “ON” V CC = 3.0 V, VI = VSS Pull-up “ON” V I = VSS VI = VSS At clock stop At clock stop V CC = 5.0 V, Ta = 25 °C “H” output voltage P20–P27 “H” output voltage P30–P34, P44–P47, P50–P57, P60–P64 “L” output voltage P20–P27 “L” output voltage P44–P47, P50–P57, P60–P64 “L” output voltage P30–P34 Hysteresis INT0, INT1, CNTR0, CNTR1, P30–P34 Hysteresis SCLK , SIN Hysteresis RESET “H” input current 0–P34, P44–P47, P50–P57, P60–P64 “H” input current P00–P07, P20–P27 “H” input current RESET, AN0–AN 3 “H” input current XIN “L” input current P00–P07, P20–P27 “L” input current P30–P34, P44–P47, P50–P57, P60–P64 “L” input current RESET, CNVSS , AN0–AN 3 “L” input current XIN RAM hold voltage (Mask ROM version) RAM hold voltage (One Time PROM version) Ring oscillator oscillation frequency Limits V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA µA V V kHz Parameter Min. V CC –2.0 VCC –0.8 VCC –2.0 VCC –0.8 –60 –25 1.8 2.2 2500 Typ. 0.5 0.5 0.5 120 4.0 –120 –50 –4.0 5000 Max. 2.0 0.8 2.0 0.8 2.0 0.8 5.0 5.0 240 100 5.0 –5.0 –5.0 –240 –100 –5.0 5.5 5.5 7500 Symbol UnitTest conditions V OH VOH VOL VOL VOL VT+–VT- VT+–VT- VT+–VT- IIH IIH IIH IIH IIL IIL IIL IIL VRAM R OSC Table 15 Electrical characteristics (Vcc = 4.0 to 5.5 V, Ta = –20 to 85°C, unless otherwise noted) Note: One Time PROM version: 2.2 to 5.5 V.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Power source current LimitsParameter Min. Typ. 3.0 0.8 1.5 4.7 0.9 2.5 0.6 0.3 0.4 0.9 0.3 0.6 1.2 0.8 0.8 1.8 0.9 1.0 0.5 0.3 0.3 0.7 0.4 0.4 5.5 6.5 7.0 3.5 3.5 600 0.1 0.5 0.5 0.4 Max. 6.0 1.6 3.0 9.4 1.8 5.0 1.2 0.6 0.8 1.8 0.6 1.2 2.4 1.6 1.6 3.6 1.8 2.0 1.0 0.6 0.6 1.4 0.8 0.8 7.0 1200 270 1.0 Symbol Unit f(X IN) = 8 MHz f(XIN) = 8 MHz (in WIT state) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 8 MHz (in WIT state) f(XIN) = 4 MHz f(XIN) = 4 MHz f(XIN) = 4 MHz (in WIT state) f(XIN) = 2 MHz f(XIN) = 4 MHz f(XIN) = 4 MHz (in WIT state) f(XIN) = 2 MHz f(XIN) = 8 MHz f(XIN) = 8 MHz (in WIT state) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 8 MHz (in WIT state) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 8 MHz (in WIT state) f(XIN) = 4 MHz f(XIN) = 8 MHz f(XIN) = 8 MHz (in WIT state) f(XIN) = 4 MHz f(XIN) = stop WIT instruction executed f(XIN) = stop WIT instruction executed f(XIN) = stop WIT instruction executed f(XIN) = stop WIT instruction executed VCC = 5 V VCC = 2.5 V VCC = 2.5 V (in WIT state) Ta = 25 °C Ta = 85 °C f(XIN) = 8 MHz, VCC = 5 V at middle-, high-speed mode f(X IN) = stop, VCC = 5 V at ring oscillator operation mode f(X IN) = stop, VCC = 5 V at low-speed mode Test conditions ICC mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA µA µA µA µA µA µA µA µA µA µA µA µA µA mA mA mA Table 16 Electrical characteristics stopped, unless otherwise noted) High-speed mode Middle-speed mode Low-speed mode Ring oscillator mode f(XCIN) = stop All oscillations stop (STP instruction executed) Current increased when AD converter is operating Vcc = 5 V Mask ROM version Vcc = 5 V One Time PROM version Vcc = 2.5 V Mask ROM version Vcc = 2.5 V One Time PROM version Vcc = 5 V Mask ROM version Vcc = 5 V One Time PROM version Vcc = 2.5 V Mask ROM version Vcc = 2.5 V One Time PROM version Vcc = 5 V Mask ROM version Vcc = 5 V One Time PROM version Vcc = 2.5 V Mask ROM version Vcc = 2.5 V One Time PROM version

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. A-D Converter Characteristics Table 17 A-D converter recommended operating condition (Vcc = 2.0 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted) Power source voltage “H” input voltage ADKEY 0–ADKEY 3 “L” input voltage ADKEY 0–ADKEY 3 AD converter control clock (low-speed mode and ring oscillator mode excluded) Unit V V V V MHz MHz MHz LimitsParameter Min. 2.0 2.2 0.9V CC Typ. 5.0 5.0 Max. 5.5 5.5 V CC 0.7VCC ✕ –0.5 20✕ VCC –38 20✕ VCC –26 40✕ VCC –82 10✕ VCC –19 8.0 Symbol Mask ROM version One Time PROM version Mask ROM version V CC ≤ 2.2 V 2.2 < VCC ≤ 2.5 V One Time PROM version V CC ≤ 2.5 V 2.5 < VCC ≤ 2.7 V Mask ROM version 2.5 < V CC ≤ 5.5 V One Time PROM version 2.7 < V CC ≤ 5.5 V Conditions VDD VIH VIL f(XIN) Table 18 A-D converter characteristics (Vcc = 2.0 to 5.5 V (One Time PROM version: 2.2 to 5.5 V), Ta = –20 to 85°C, unless otherwise noted) Resolution Linearity error Differential non-linearity error Zero transition voltage Full-scale transition voltage Absolute accuracy (quantification error excluded) Conversion time (Note) Analog input current Unit BIT LSB LSB mV mV mV mV LSB LSB LSB LSB tc(φAD) µA LimitsParameter Min. 5070 2535 106 Typ. 5100 2550 Max. ±0.9 5120 2560 109 Symbol CC ≤ 5.5 V Ta = 25 °C, 2.5 ≤ VCC ≤ 5.5 V VCC = 5.12 V, Ta = 25 °C VCC = 2.56 V, Ta = 25 °C VCC = 5.12 V, Ta = 25 °C VCC = 2.56 V, Ta = 25 °C 2.2 < VCC ≤ 5.5 V (2.7 < VCC ≤ 5.5 V for One Time PROM version), f(XIN) ≤ 8.0 MHz, or low-speed or ring oscillator mode 2.2 < VCC ≤ 2.5 V (2.5 < VCC ≤ 2.7 V for One Time PROM version), f(XIN) ≤ 2.0 MHz, or low-speed or ring oscillator mode 2.2 ≤ VCC < 2.3 V for One Time PROM version Low-speed or ring oscillator mode excluded Condition except above Test conditions LIN DIF V0T VFST ABS T conv IIA Note: The operation clock is XIN in the middle- or high-speed mode, or the ring oscillator in the other modes. When the A-D conversion is executed in the middle- or high-speed mode, set f(XIN) ≥ 500 kHz. tc(φAD): One cycle of control clock for A-D converter. XIN input is used in the middel- or high-speed mode, and ring oscillator is used in the low- or ring oscillator mode for the control clock.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O input setup time Serial I/O input hold time tw (RESET) tc(XIN) twH (XIN) twL (XIN) tc(CNTR) twH (CNTR) twL (CNTR) twH (INT) twL (INT) tc(SCLK ) twH (SCLK ) twL (SCLK ) tsu(SIN-SCLK ) th(SCLK -SIN) Limits µs ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. 125 250 105 105 1000 400 400 200 200 Typ. Max.Symbol Unit Table 20 Timing requirements 2 (Vcc =1.8 to 4.0 V (2.2 to 4.0 V for One Time PROM version), Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Timing Requirements And Switching Characteristics Table 19 Timing requirements 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) tw (RESET) tc(XIN) twH (XIN) twL (XIN) tc(CNTR) twH (CNTR) twL (CNTR) twH (INT) twL (INT) tc(SCLK ) twH (SCLK ) twL (SCLK ) tsu(RxD-SCLK ) th(SCLK -RxD) Limits µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Parameter Min. 125 166 1000/V CC 1000/(5✕ VCC –8) tc(CNTR)/2–20 tc(CNTR)/2–20 230 230 2000 950 950 400 200 Typ. Max.Symbol Unit Reset input “L” pulse width Main clock input cycle time (X IN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0, INT1 input “H” pulse width INT0, INT1 input “L” pulse width Serial I/O clock input cycle time Serial I/O clock input “H” pulse width Serial I/O clock input “L” pulse width Serial I/O input setup time Serial I/O input hold time 2.0 V (One Time PROM version: 2.5 V) ≤ VCC ≤ 4.0 V VCC ≤ 2.0 V (One Time PROM version: 2.5 V) 2.0 V (One Time PROM version: 2.5 V) ≤ VCC ≤ 4.0 V VCC ≤ 2.0 V (One Time PROM version: 2.5 V) 2.0 V (One Time PROM version: 2.5 V) ≤ VCC ≤ 4.0 V VCC ≤ 2.0 V (One Time PROM version: 2.5 V) 2.0 V (One Time PROM version: 2.5 V) ≤ VCC ≤ 4.0 V VCC ≤ 2.0 V (One Time PROM version: 2.5 V)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. twH (SCLK ) twL (SCLK ) td(SCLK -SOUT ) tV(SCLK -SOUT ) tr(SCLK ) tf(SCLK ) tr(CMOS) tf(CMOS) twH (SCLK ) twL (SCLK ) td(SCLK -SOUT ) tV(SCLK -SOUT ) tr(SCLK ) tf(SCLK ) tr(CMOS) tf(CMOS) LimitsParameter Min. tc(SCLK )/2–30 tc(SCLK )/2–30 –30 Typ. Max. 140 200 Symbol Unit ns ns ns ns ns ns ns ns ns Notes 1:When the P55/SOUT P-channel output disable bit of the serial I/O control register (bit 4 of address 001D16) is “0.” 2:The XOUT , XCOUT pins are excluded. Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time P2 0–P27 CMOS output rising time P30–P34, P44–P47, P50–P57, P60–P64 (Note 2) CMOS output falling time (Note 2) Table 21 Switching characteristics 1 (Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Limits ns ns ns ns ns ns ns ns ns Parameter Min. t C (SCLK )/2–80 tC (SCLK )/2–80 –30 Typ. Max. 350 400 120 120 Symbol Unit Serial I/O clock output “H” pulse width Serial I/O clock output “L” pulse width Serial I/O output delay time (Note 1) Serial I/O output valid time (Note 1) Serial I/O clock output rising time Serial I/O clock output falling time CMOS output rising time P2 0–P27 CMOS output rising time P30–P34, P44–P47, P50–P57, P60–P64 (Note 2) CMOS output falling time (Note 2) Table 22 Switching characteristics 2 (Vcc = 1.8 to 4.0 V (2.2 to 4.0 V for One Time PROM version), Vss = 0 V, Ta = –20 to 85°C, unless otherwise noted) Notes 1:When the P55/SOUT P-channel output disable bit of the serial I/O control register (bit 4 of address 001D16) is “0.” 2:The XOUT , XCOUT pins are excluded. Fig. 50 Circuit for measuring output switching characteristics M easurement output pin 1 0 0 p F C M O S o u t p u t N ote: Wh en bit 4 of the serial I/O control register (address 001D 16) is “1” (N-channel open-drain output mode). N - c h a n n e l o p e n - d r a i n o u t p u t ( N o t e ) kΩ 0 0 p F M easurement output pin

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. Fig. 51 Timing chart 0 . 2 VC C td( SC L K- SO U tf 0.2VCC 0 . 8 VC C 0.8VCC tr ts u( SI N - SC L K)t h( SC L K- SI N ) tv( SC L K- SO U tC (SCLK ) tWL (SCLK ) tW H ( SC L SO U T SI N SC L K 0 . 2 VC C tW L( XI N ) 0 . 8 VC C tWH (XIN) tC (XIN) XI N 0.2VCC 0.8VCC tW (RESET) R E S E T 0 . 2 VC C tW L( C N T R ) 0 . 8 VC C tWH (CNTR) tC (CNTR) 0 . 2 VC C tW L( I N T ) 0 . 8 VC C tWH (INT) C N T R 0, C N T R 1 I N T0 I N T1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS PRELIMINAR Y Notice: This is not a final specification. Some parametric limits are subject to change. PACKAGE OUTLINE LQFP64-P-1010-0.50 – Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 64P6Q-A Plastic 64pin 10✕ 10mm body LQFP 0.1 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 1.0 ––M D 10.4 ––M E 10.4 10°0° 0.1 1.0 0.70.50.3 12.212.011.8 12.212.011.8 0.5 10.110.09.9 10.110.09.9 0.1750.1250.105 0.280.180.13 1.4 1.7 e e E H E 64 49 3217 H D D M D M E A F y Recommended Mount Pad Lp 0.45 0.6 0.25 0.75 0.08 x b x M A1 A2 L Detail F Lp c e MMP LQFP64-P-1414-0.8 Weight(g) JEDEC CodeEIAJ Package Code Lead Material Cu Alloy 64P6U-A Plastic 64pin 14✕ 14mm body LQFP 0.1 0.8 0.2 Symbol Min Nom Max A b c D E H E L y Dimension in Millimeters H D 0.225 ––I2 ––M D 14.4 ––M E 14.4 0° 8° 0.1 0.2 1.0 0.70.50.3 16.215.8 14.113.9 16.215.8 14.0 14.113.9 14.0 16.0 16.0 0.1750.1250.105 0.450.370.32 1.4 1.7 e Lp 0.45 0.95 0.6 0.25 0.75 x Recommended Mount Pad Detail F MMP E H E 17 32 64 49 H D D A y b x M e F M D M E e A1 A2 L Lp c

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• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. HEAD OFFICE: 2-2-3, MARUNOUCHI, CHIYODA-KU, TOKYO 100-8310, JAPAN SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER 38C1 Group MITSUBISHI MICROCOMPUTERS

REVISION HISTORY 38C1 GROUP DATA SHEET Rev. Date Description Page Summary (1/2) 1.0 01/16/02 2.0 03/28/02 2.1 05/09/02 First Edition 1 FEATURES; • Interrupts and • Power dissipation revised.

4 PIN DESCRIPTION; V

L1–VL3 0 ≤ VL1 ≤ VL2 ≤ VL3 → 0 ≤ VL1 ≤ VL2 < VL3 6 Table 2; Date revised. Jan. → Mar. 10 Fig. 7; Bits 3 and 6 Description added. 12 Fig. 10; Address 0007

16 Port P3 direction register (P3D)

Address 000816 “ADKEY pin selection” added. 14 Table 5; Note 2 revised. INTERRUPTS; fourteen sources → thirteen sources, eight internal → seven internal 20 Fig. 17; PULL register A Bit 2 = “1” → PULL register Bit 3 = “1” 27 G A-D Converter description added. 28 A-DKEY Control Circuit; Description revised all. Fig. 27; Figure title and note “pin” added. 32 Common Pin and Duty Ratio Control; Description added. Table 9; Note revised. 36 Fig. 35; Bits 0 and 1 Functional description revised. G RRF register; Description revised. 41 Fig. 43; Low-speed mode CM 3 = 1 → CM 3 = * (Note 9) 44 (3) line 5; voltage and temperature → voltage or/and temperature 47 to 54 ELECTRICAL CHARACTERISTICS ; Most contents revised. 47 Table 12; V CC revised, VL3 and Notes added. 49 Table 14; Note revised. 51 Table 16; Most contents revised. 52 Table 17; Added. Table 18; Most contents revised. 53 Table 20; “(2.2 to 4.0 V for One Time PROM version)” added. 54 Table 22; “(2.2 to 4.0 V for One Time PROM version)” added. 56 PACKAGE OUTLINE revised. 6 Fig. 4 and Table 2; Revised. 10 [CPU Mode Register (CPUM)]; Description revised. 16 Fig. 13; Revised. 22 G Timer X, I Note on count source selection bit; Description revised. 25 Fig. 23; Note revised. 39 Clock generating circuit; Note revised.

47 Table 12;

“H” input voltage ADKEY0–ADKEY3, “L” input voltage ADKEY0–ADKEY3 eliminated. 49 Table 14; Note 3 added. Table 17; “H” input voltage ADKEY0–ADKEY3, “L” input voltage ADKEY0–ADKEY3 added.

REVISION HISTORY 38C1 GROUP DATA SHEET Rev. Date Description Page Summary (2/2) 2.2 07/11/02 25 I Notes on Serial I/O added. 27 [A-D Control Register (ADCON)] 003416 Also, when the bit 4 is “1”, do not write “0” to bit 3 by program.

28 Please do not write “0” in the AD conversion completion bit

5th item; Return operation by reset, STOP or WIT under A-D conversion operation at selecting ADKEY function is performed.

46 Table 11 Absolute Maximum Ratings

VI Input voltage CNVSS (Mask ROM version) → –0.3 to VCC +0.3 47 V CC when oscillation starts revised. Note 2 revised.

49 Table 14 Recommended operating conditions;

f(CNTR0), f(CNTR1) and f(XIN) revised. Note 4 added. 51 Table 16 Electrical characteristics revised.

52 Table 17 A-D characteristics recommended operating condition; f(X

IN) revised. Table 18 A-D converter characteristics; ABS revised. 54 Table 21, 22 Switching characteristics; tr(CMOS) revised.