3820

M38207E8FP MITSUBISHI | Alldatasheet

Document overview

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Technical content

DESCRIPTION

The 3820 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 3820 group has the LCD drive control circuit and the serial I/ O as additional functions. The various microcomputers in the 3820 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3820 group, re- fer to the section on group expansion.

FEATURES

(at 8MHz oscillation frequency)

• Memory size
• Software pull-up/pull-down resistors (Ports P0-P7 except Port P40) (includes key input interrupt)
• LCD drive control circuit
• 2 Clock generating circuit Clock (X (connect to external ceramic resonator or quartz-crystal oscillator)
• Power source voltage (at 8MHz oscillation frequency and high-speed selected) (at 8MHz oscillation frequency and middle-speed selected) (Extended operating temperature version: 3.0 V to 5.5 V)
• Power dissipation (at 8 MHz oscillation frequency) (at 32 kHz oscillation frequency, at 3 V power source voltage) (Extended operating temperature version: –40 to 85°C)

APPLICATIONS

Household appliances, consumer electronics, etc. MITSUBISHI MICROCOMPUTERS

3820 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) P30/SEG 16 P31/SEG 17 P32/SEG 18 P33/SEG 19 P34/SEG 20 P35/SEG 21 P36/SEG 22 P37/SEG 23 P00/SEG 24 P03/SEG 27 P04/SEG 28 P05/SEG 29 P06/SEG 30 P07/SEG 31 P11/SEG 33 P12/SEG 34 P13/SEG 35 P14/SEG 36 P15/SEG 37 P16/SEG 38 P17/SEG 39 P10/SEG 32 P01/SEG 25 P02/SEG 26 SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 VCC SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 0 COM 3 COM 2 COM 1 VL3 VL2 VL1 P60/INT3/RTP0 P57/INT2 P56/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 P42/INT0 COM 0 P50/SIN2 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P55/CNTR 1 P61/RTP1 P41/φ P40 XIN XOUT VSS P27 P26 P25 P24 P23 P22 P21 P20 RESET P70/XCOUT P71/XCIN M38203M4-XXXFP 123456789 1 0 1 1 1 2 1 3 1 4 1 5 1 6 1 7 1 8 1 9 2 0 2 1 2 2 2 3 2 4 414243444546474849505152535455565758596061626364 M38203M4-XXXFP Package type : 80P6N-A 80-pin plastic molded QFP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) Package type : 80P6S-A/80P6D-A 80-pin plastic-molded QFP P30/SEG 16 P31/SEG 17 P32/SEG 18 P33/SEG 19 P34/SEG 20 P35/SEG 21 P36/SEG 22 P37/SEG 23 P00/SEG 24 P03/SEG 27 P04/SEG 28 P05/SEG 29 P06/SEG 30 P07/SEG 31 P11/SEG 33 P12/SEG 34 P13/SEG 35 P14/SEG 36 P15/SEG 37 P16/SEG 38 P17/SEG 39 P10/SEG 32 P01/SEG 25 P02/SEG 26 SEG 1 SEG 2 SEG 3 SEG 4 SEG 6 SEG 5 SEG 7 VCC SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 0 COM 3 COM 2 COM 1 VL3 VL2 VL1 P60/INT3/RTP0 P57/INT2 P56/TOUT P47/SRDY1 P46/SCLK1 P45/TXD P44/RXD P43/INT1 P42/INT0 COM 0 P50/SIN2 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P55/CNTR 1 P61/RTP1 P41/f P40 XIN XOUT VSS P27 P26 P25 P24 P23 P22 P21 P20 RESET P70/XCOUT P71/XCIN 1 2 3 4 7 8 9 1 01 11 21 31 41 51 61 71 81 9 2 056 4142434445464748495051525354555657585960 M38203M4-XXXGP M38203M4-XXXHP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL BLOCK DIAGRAM (Package : 80P6N-A) INT2 CNTR 0,CNTR 1 TOUT CPU A X Y S PC H PC L PS ROM P0(8)P7(2) 27 73 32 28 29 91 0 28 29 SI/O1(8) VL1 VL2 VL3 COM 0 COM 1 COM 2 COM 3 SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 XCIN XCOUT 30 31 49 50 51 52 53 54 55 56 P1(8) 41 42 43 44 45 46 47 48 P2(8) 33 34 35 36 37 38 39 40 P4(8) 21 22 23 24 25 2619 20 P5(8) 12 13 14 15 16 17 1811 f LCD drive control circuit RAM LCD display RAM (20 bytes) Timer X(16) Timer Y(16) Timer 1(8) Timer 2(8) Timer 3(8) Data bus Clock generating circuit Clock input XIN Clock output X OUT XCOUT Sub- clock output XCIN Sub- clock input VCC VSS Reset input (5V) (0V) RESET I/O port P7 P6(2) I/O port P6 Watchdog timer P3(8) 57 58 59 60 61 62 63 64 P0(8) I/O port P0I/O port P1 Key-on wake up I/O port P2 Real time port function Input port P3 f I/O port P4 INT0,INT1 SI/O2(8) I/O port P5 SEG 12 SEG 13 SEG 14 SEG 15 RESET RTP 0,RTP1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Function

• Apply voltage of 2.5 V to 5.5 V to VCC , and 0 V to VSS . (Extended operating temperature version : 3.0 V to 5.5 V)
• Reset input pin for active “L”
• Input and output pins for the main clock generating circuit.
• Feedback resistor is built in between XIN pin and XOUT pin.
• Connect a ceramic resonator or a quartz-crystal oscillator between the XIN and XOUT pins to set the oscillation frequency.
• If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
• This clock is used as the oscillating source of system clock.
• Input 0 ≤ VL1 ≤ VL2 ≤ VL3 ≤ VCC voltage
• Input 0 – VL3 voltage to LCD
• LCD common output pins
• COM 2 and COM 3 are not used at 1/2 duty ratio.
• COM 3 is not used at 1/3 duty ratio.
• LCD segment output pins
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each port to be individually programmed as either input or output.
• Pull-down control is enabled.
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each port to be individually programmed as either input or output.
• Pull-down control is enabled.
• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 8-bit Input port
• CMOS compatible input level
• Pull-down control is enabled.
• 1-bit input pin
• CMOS compatible input level
• 7-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled. Pin V CC VSS RESET XIN XOUT VL1 – VL3 COM 0 – COM 3 SEG 0 – SEG15 P00/SEG 24 – P07/SEG 31 P10/SEG 32 – P17/SEG 39 P20 – P27 P30/SEG 16 – P37/SEG 23 P40 P41/ φ P42/INT0, P43/INT1 P44/RX D, P45/TX D, P46/SCLK1, P47/SRDY1 Name Power source Reset input Clock input Clock output LCD power source Common output Segment output I/O port P0 I/O port P1 I/O port P2 Input port P3 Input port P4 I/O port P4 Function except a port function
• LCD segment pins
• Key input (key-on wake up) interrupt input pins
• LCD segment pins
• φ clock output pin
• Interrupt input pins
• Serial I/O1 function pins PIN DESCRIPTION

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Function

• 8-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 2-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled.
• 2-bit I/O port
• CMOS compatible input level
• CMOS 3-state output structure
• I/O direction register allows each pin to be individually programmed as either input or output.
• Pull-up control is enabled. Pin 0/SIN2, P51/SOUT2 , P52/SCLK2 , P53/SRDY2 P54/CNTR 0, P55/CNTR 1 P56/TOUT P57/INT2 P60/INT3/RTP0 P61/RTP1 P70/XCOUT , P71/XCIN PIN DESCRIPTION Name I/O port P5 I/O port P6 I/O port P7 Function except a port function
• Serial I/O2 function pins
• Timer function pins
• Timer output pin
• Interrupt input pin
• Interrupt input pins(P6
• Real time port function pin
• Sub-clock generating circuit input pins (Connect a resonator. External clock cannot be used.)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING M3820 3 M 4 - XXX FPProduct ROM/PROM size : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type M E : Mask ROM version : EPROM or One Time PROM version RAM size : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes Package type FP GP HP FS ROM number Omitted in some types. Normally, using hyphen When electrical characteristic, or division of quality identification code using alphanumeric character – : standard D : Extended operating temperature version : 80P6N-A package : 80P6S-A package : 80P6D-A package : 80D0 package

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION Mitsubishi plans to expand the 3820 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions (3) Packages Memory Expansion Plan M38207M8/E8 N ew product M38203M4/E4 Mass product ROM size (bytes) 32K 28K 24K 20K 16K 12K 192 256 384 512 640 768 896 1024 RAM size (bytes) Currently supported products are listed below. As of May 1996 RAM size (bytes) 512 1024 Remarks Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version Package 80P6N-A 80P6S-A 80P6D-A 80D0 80P6N-A 80P6S-A 80P6D-A 80D0 Product M38203M4-XXXFP M38203E4-XXXFP M38203E4FP M38203M4-XXXGP M38203E4-XXXGP M38203E4GP M38203M4-XXXHP M38203E4-XXXHP M38203E4HP M38203E4FS M38207M8-XXXFP M38207E8-XXXFP M38207E8FP M38207M8-XXXGP M38207E8-XXXGP M38207E8GP M38207M8-XXXHP M38207E8-XXXHP M38207E8HP M38207E8FS 16384 (16254) (P) ROM size (bytes) ROM size for User in ( ) 32768 (32638)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER M38 207M8D New product M38 203M4D New product ROM size (bytes) 32K 28K 24K 20K 16K 12K 192 256 384 512 640 768 896 1024 RA M size (bytes) GROUP EXPANSION (EXTENDED OPERATING TEMPERATURE VERSION) Mitsubishi plans to expand the 3820 group (extended operating temperature version) as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions (3) Packages Memory Expansion Plan Currently supported products are listed below. RAM size (bytes) 512 1024 1024 16384(16254) 32768(32638) 32768(32638) Remarks Mask ROM version Mask ROM version Mask ROM version As of May 1996 Package 80P6N-A 80P6N-A 80P6S-A Product M38203M4DXXXFP M38207M8DXXXFP M38207M8DXXXGP ROM size (bytes) ROM size for User in ( )

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Package 80P6N-A 80P6S-A 80P6D-A 80P6N-A 80P6S-A 80P6D-A RAM size (bytes) Product M38203M2LXXXFP M38203M2LXXXGP M38203M2LXXXHP M38203M4LXXXFP M38203M4LXXXGP M38203M4LXXXHP GROUP EXPANSION (LOW POWER SOURCE VOLTAGE VERSION) Mitsubishi plans to expand the 3820 group (low power source volt- age version) as follows: (1) Support for mask ROM version (3) Packages Memory Expansion Plan Currently supported products are listed below. 8192 (8062) As of May 1996 ROM size (bytes) ROM size for User in ( ) 16384 (16254) M38 203M 2L New product ROM size (bytes) 32K 28K 24K 20K 16K 12K 192 256 384 512 640 768 896 1024 RA M size (bytes) M38 203M 4L New product 512

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3820 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. CPU Mode Register The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit and the internal system clock selection bit. Fig. 1 Structure of CPU mode register CPU mode register (CPUM (CM) : address 003B16) 7 0 Not available Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : 1 0 : 1 1 : Stack page selection bit 0 : 0 RAM in the zero page is used as stack area 1 : 1 RAM in page 1 is used as stack area Not used (returns “1” when read) (Do not write “0” to this bit) Port X C switch bit 0 : I/O port 1 : XCIN, XCOUT Main clock ( XIN–XOUT ) stop bit 0 : Oscillating 1 : Stopped Main clock division ratio selection bit 0 : f(X IN)/2 (high-speed mode) 1 : f(XIN)/8 (middle-speed mode) Internal system clock selection bit 0 : X IN-XOUT selected (middle-/high-speed mode) 1 : XCIN-XCOUT selected (low-speed mode)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MEMORY Special Function Register (SFR) Area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt Vector Area The interrupt vector area contains reset and interrupt vectors. Zero Page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special Page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 2 Memory map diagram 010016 000016 004016 044016 FF0016 FFDC 16 FFFE 16 FFFF 16 192 256 384 512 640 768 896 1024 XXXX 00FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 4096 8192 12288 16384 20480 24576 28672 32768 F000 E00016 D000 16 C000 16 B00016 A00016 900016 800016 F08016 E08016 D080 16 C080 16 B08016 A08016 908016 808016 YYYY 16 ZZZZ 16 RAM ROM 005416 Reserved area SFR area Not used Interrupt vector area ROM area Reserved ROM area (128 bytes) Zero page Special page RAM area RAM size (bytes) Address XXXX 16 ROM size (bytes) Address YYYY 16 LCD display RAM area Address ZZZZ 16 Reserved ROM area

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig.3 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Serial I/O2 register (SIO2) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Port P7 (P7) Port P7 direction register (P7D) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) Interrupt control register 2(ICON2) Timer 3 (T3) Timer X mode register (TXM) Watchdog timer control register (WDTCON) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Timer X (low-order) (TXL) Timer Y (low-order) (TYL) Timer 1 (T1) Timer 2 (T2) Timer X (high-order) (TXH) Timer Y (high-order) (TYH) PULL register A (PULLA) PULL register B (PULLB) Timer Y mode register (TYM) Timer 123 mode register (T123M) f output control register (CKOUT) Segment output enable register (SEG) LCD mode register (LM)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER I/O PORTS Direction Registers (ports P2, P41–P4 7, and P5–P7) The 3820 group has 43 programmable I/O pins arranged in seven I/O ports (ports P0–P2 and P4–P7). The I/O ports P2, P41–P4 7, and P5–P7 have direction registers which determine the input/out- put direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating. Direction Registers (ports P0 and P1) Ports P0 and P1 have direction registers which determine the in- put /output direction of each individual port. Each port in a direction register corresponds to one port, each port can be set to be input or output. When “0” is written to the bit 0 of a direction register, that port be- comes an input port. When “1” is written to that port, that port be- comes an output port. Bits 1 to 7 of ports P0 and P1 direction registers are not used. Ports P3 and P40 These ports are only for input. Pull-up/Pull-down Control By setting the PULL register A (address 001616) or the PULL reg- ister B (address 001716), ports except for port P40 can control ei- ther pull-down or pull-up (pins that are shared with the segment output pins for LCD are pull-down; all other pins are pull-up) with a program. However, the contents of PULL register A and PULL register B do not affect ports programmed as the output ports. Fig. 4 Structure of PULL register A and PULL register B PULL register A (PULLA : address 001616) 0 : Disable 1 : Enable Note : The contents of PULL register A and PULL register B do not affect ports programmed as the output ports. PULL register B (PULLB : address 0017 16) P00–P07 pull-down P10–P17 pull-down P20–P27 pull-up P30–P37 pull-down P70, P71 pull-up Not used (return "0" when read) P41–P43 pull-up P44–P47 pull-up P50–P53 pull-up P54–P57 pull-up P60, P61 pull-up Not used (return "0" when read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Related SFRs PULL register A Segment output enable register PULL register A Segment output enable register PULL register A Interrupt control register 2 PULL register A Segment output enable register PULL register B φ output control register PULL register B Interrupt edge selection register PULL register B Serial I/O1 control register Serial I/O1 status register UART control register PULL register B Serial I/O2 control register PULL register B Timer X mode register PULL register B Timer Y mode register PULL register B Timer 123 mode register PULL register B Interrupt edge selection register PULL register B Timer X mode register Interrupt edge selection register PULL register B Timer X mode register PULL register A CPU mode register LCD mode register Pin P00/SEG 24– P07/SEG 31 P10/SEG 32– P17/SEG 39 P20 – P27 P30/SEG 16– P37/SEG 23 P40 P41/ φ P42/INT0, P43/INT1 P44/RX D P45/TX D P46/SCLK1 P47/SRDY1 P50/SIN2 P51/SOUT2 P52/SCLK2 P53/SRDY2 P54/CNTR 0 P55/CNTR 1 P56/TOUT P57/INT2 P60/INT3/RTP0 P61/RTP1 P70/XCOUT P71/XCIN COM 0-COM 3 SEG 0-SEG 15 Name Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P7 Common Segment Input/Output Input/output, individual ports Input/output, individual ports Input/output, individual bits Input Input Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits output output I/O Format CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS compatible input level CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output LCD common output LCD segment output Non-Port Function LCD segment output LCD segment output Key input(Key-on wake up) interrupt input LCD segment output φ clock output External interrupt input Serial I/O1 function I/O Serial I/O2 function I/O Timer I/O Timer I/O Timer output External interrupt input External interrupt input Real time port function output Real time port function output Sub-clock generating circuit I/O Diagram No. (1) (2) (3) (4) (5) (2) (6) (7) (8) (9) (10) (11) (12) (13) (14) (10) (15) (2) (16) (17) (18) (19) (20) Note : Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 5 Port block diagram (1) (3)Ports P30–P37 VL2/VL3 VL1/VSS (1)Ports P0,P1 Segment output enable bit VL2/VL3 VL1/VSS (Note) (5)Port P41 Data bus Pull-down control Segment output enable bit Data bus Direction register Port latch Pull-down control Segment output enable bit Note. Bit 0 of port P0 direction register and port P1 direction register. f f output control bit Direction register Pull-up control Data bus Port latch Direction register Pull-up control Data bus Port latch Direction register Pull-up control Data bus Port latch (7)Port P45 Serial I/O1 output Serial I/O1 enable bit Transmission enable bit VL2/VL3 P45/TXD P-channel output disable bit (6)Port P44 (4)Port P40 (2)Ports P2,P42,P43,P57 Direction register Direction register Data bus Port latch Pull-up control Key input (Key-on wake up) interrupt input INT0–INT2 interrupt input Pull-up control Reception enable bit Serial I/O1 enable bit Serial I/O1 input Data bus Port latch Data bus (8)Port P46 Serial I/O1 clock input Direction register Pull-up control Data bus Port latch Serial I/O1 clock output Serial I/O1 mode selection bit Serial I/O1 enable bit Serial I/O1 synchronization clock selection bit Serial I/O1 enable bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 6 Port block diagram (2) Serial I/O2 output Direction register Port latchData bus Pull-up control Serial I/O1 ready output (11) Port P51 (9) Port P47 Serial I/O1 mode selection bit Serial I/O1 enable bit Direction register Port latchData bus Pull-up control SRDY1 output enable bit Serial I/O2 transmit completion signal Serial I/O2 port selection bit Direction register Port latchData bus Pull-up control SRDY2 output enable bit Direction register Port latchData bus Pull-up control Timer output TOUT output control bit Serial I/O2 ready output (10) Ports P50,P55 (12) Port P52 Direction register Port latchData bus Pull-up control Serial I/O2 input CNTR 1 interrupt input Serial I/O2 clock output Serial I/O2 clock input Direction register Port latchData bus Pull-up controlInternal synchronization clock select bits Serial I/O2 port selection bit Timer X operating mode bit Timer output CNTR 0 interrupt input (Pulse output mode selection) Direction register Port latchData bus Pull-up control Real time port control bit INT3 interrupt input Except P61 Data for real time port Direction register Port latchData bus Pull-up control (14) Port P54 (16) Ports P60, P61(15) Port P56 (13) Port P53

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 7 Port block diagram (3) (17) Port P70 Data bus Direction register Port latch Port selection/Pull-up control Port XC switch bit Oscillation circuit Port P71 Port XC switch bit VL3 VL2 VL1 (19) COM0 –COM 3 The gate input signal of each transistor is controlled by the LCD duty ratio and the bias value. VSS (18) Port P71 Data bus Direction register Port latch Port XC switch bit Port selection/Pull-up control Sub-clock generating circuit input (20) SEG0 – SEG 15 The voltage applied to the sources of P-channel and N-channel transistors is the controlled voltage by the bias value. VL2/VL3 VL1/VSS

Interrupt enable bits can be set or cleared by software. table into the program counter. (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to “0”. (4) Enable the external interrupt which is selected. Table 1. Interrupt vector addresses and priority Notes 1 : Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 8 Interrupt control Fig. 9 Structure of interrupt-related registers Interrupt request bit Interrupt enable bit Interrupt disable flag (I) BRK instruction Reset Interrupt request 7 0 7 0 7 0 7 0 7 0 Interrupt edge selection register INT0 interrupt edge selection bit INT1 interrupt edge selection bit INT2 interrupt edge selection bit INT3 interrupt edge selection bit Not used (return “0” when read) (INTEDGE : address 003A16) Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 2 interrupt request bit Timer 3 interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 2 interrupt enable bit Timer 3 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C 16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Timer 1 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit Key input interrupt request bit Serial I/O2 interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D 16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Timer 1 interrupt enable bit INT 2 interrupt enable bit INT3 interrupt enable bit Key input interrupt enable bit Serial I/O2 interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F 16) 0 : Falling edge active 1 : Rising edge active

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Key Input Interrupt (Key-on Wake Up) A key input interrupt request is generated by applying “L” level to any pin of port P3 that have been set to input mode. In other words, it is generated when AND of input level goes from “1” to “0”. An example of using a key input interrupt is shown in Figure 9, where an interrupt request is generated by pressing one of the keys consisted as an active-low key matrix which inputs to ports 0–P2 3. Fig. 10 Connection example when using key input interrupt and port P2 block diagram Port P20 latch Port P20 direction register = "0" Port P21 latch Port P21 direction register = "0" Port P22 latch Port P22 direction register = "0" Port P23 latch Port P23 direction register = "0" Port P24 latch Port P24 direction register = "1" Port P25 latch Port P25 direction register = "1" Port P26 latch Port P26 direction register = "1" Port P27 latch Port P27 direction register = "1" P20 input P21 input P22 input P23 input P24 output P25 output P26 output P27 output PULL register A Bit 2 = "1" Port P2 Input reading circuit Port PXx "L" level output ] P-channel transistor for pull-up ] ] CMOS output buffer Key input interrupt request ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] ] ]] ] ]]

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER TIMERS The 3820 group has five timers: timer X, timer Y, timer 1, timer 2, and timer 3. Timer X and timer Y are 16-bit timers, and timer 1, timer 2, and timer 3 are 8-bit timers. All timers are down count timers. When the timer reaches “00 16”, an underflow occurs at the next count pulse and the correspond- ing timer latch is reloaded into the timer and the count is contin- ued. When a timer underflows, the interrupt request bit corre- sponding to that timer is set to “1”. Read and write operation on 16-bit timer must be performed for both high and low-order bytes. When reading a 16-bit timer, read the high-order byte first. When writing to a 16-bit timer, write the low-order byte first. The 16-bit timer cannot perform the correct op- eration when reading during the write operation, or when writing during the read operation. Fig. 11 Timer block diagram Timer 1 count source selection bit Real time port control bit "0" "1" P55/CNTR 1 "0" f(XIN)/16 (f(XCIN)/16 in low-speed mode*) CNTR 1 active edge switch bit "10" Timer Y stop control bit Falling edge detection Period measurement mode Timer Y interrupt request Pulse width HL continuously measurement mode Rising edge detection Timer Y operating mode bit Timer X interrupt request Timer X mode register write signal P54/CNTR 0 Timer X (low) (8) Timer X (low) latch (8) Timer X (high) latch (8) Q Q T S P54 direction register Pulse output mode P54 latch Timer X stop control bit "0" "1" Timer X write control bit Q D Latch Q D Latch "1" "0" "1" "10" Timer X operat- ing mode bit f(XIN)/16 (f(XCIN)/16 in low-speed mode*) Pulse width measurement mode CNTR 0 active edge switch bit CNTR 0 active edge switch bit Pulse output mode Timer 2 latch (8) Timer 2 (8) Q Q T S "0" P56 direction register P56 latch "1" TOUT output active edge switch bit "0" Timer 2 write control bit "0" "1" T OUT output control bit "1" P56/TOUT XCIN Timer 3 count source selection bit "0" "1" Timer 2 interrupt request Timer 3 interrupt request TOUT output control bit Timer 2 count source selection bit Timer 1 latch (8) Timer 1 (8) Timer 1 interrupt request Data bus f(XIN)/16 (f(XCIN)/16 in low-speed mode*) f(XIN)/16 (f(XCIN)/16 in low-speed mode*) f(XIN)/16(f(XCIN)/16 in low-speed mode*) * Internal clock f = XCIN/2. CNTR 0 interrupt request CNTR 1 interrupt request Timer Y operating mode bit "11" P60 direction register "0" Real time port control bit "1" P60 P60 latch P61 direction register "0" Real time port control bit "1" P61 P61 latch P60 data for real time port P61 data for real time port Timer Y (low) (8) Timer Y (low) latch (8) Timer Y (high) latch (8) Timer 3 latch (8) Timer 3 (8) Timer X (high) (8) Timer Y (high) (8)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X Timer X is a 16-bit timer that can be selected in one of four modes and can be controlled the timer X write and the real time port by setting the timer X mode register. Timer mode The timer counts f(X IN)/16 (or f(XCIN)/16 in low-speed mode). Pulse output mode Each time the timer underflows, a signal output from the CNTR0 pin is inverted. Except for this, the operation in pulse output mode is the same as in timer mode. When using a timer in this mode, set the corresponding port P5 4 direction register to output mode. Event counter mode The timer counts signals input through the CNTR0 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P5 4 direction register to input mode. Pulse width measurement mode The count source is f(XIN)/16 (or f(XCIN)/16 in low-speed mode. If CNTR 0 active edge switch bit is “0”, the timer counts while the in- put signal of CNTR0 pin is at “H”. If it is “1”, the timer counts while the input signal of CNTR0 pin is at “L”. When using a timer in this mode, set the corresponding port P54 direction register to input mode. Timer X Write Control If the timer X write control bit is “0”, when the value is written in the address of timer X, the value is loaded in the timer X and the latch at the same time. If the timer X write control bit is “1”, when the value is written in the address of timer X, the value is loaded only in the latch. The value in the latch is loaded in timer X after timer X underflows. If the value is written in latch only, unexpected value may be set in the high-order counter when the writing in high-order latch and the underflow of timer X are performed at the same timing. Note on CNTR 0 Interrupt Active Edge Selec- tion CNTR 0 interrupt active edge depends on the CNTR0 active edge switch bit. Real Time Port Control While the real time port function is valid, data for the real time port are output from ports P6 0 and P6 1 each time the timer X underflows. (However, after rewriting a data for real time port, if the real time port control bit is changed from “0” to “1”, data is output without the timer X.) If the data for the real time port is changed while the real time port function is valid, the changed data are out- put at the next underflow of timer X. Before using this function, set the corresponding port direction registers to output mode. Fig. 12 Structure of timer X mode register Timer X mode register (TXM : address 002716) Timer X write control bit 0 : Write value in latch and counter 1 : Write value in latch only Real time port control bit 0 : Real time port function invalid 1 : Real time port function valid P60 data for real time port 0 : "L" level output 1 : "H" level output P61 data for real time port 0 : "L" level output 1 : "H" level output Timer X operating mode bits b5 b4 0 0 : Timer mode 0 1 : Pulse output mode 1 0 : Event counter mode 1 1 : Pulse width measurement mode CNTR 0 active edge switch bit

• CNTR0 interrupt 0 : Falling edge active 1 : Rising edge active
• Pulse output mode 0 : Start at initial level "H" output 1 : Start at initial level "L" output
• Event counter mode 0 : Rising edge active 1 : Falling edge active
• Pulse width measurement mode 0 : Measure "H" level width 1 : Measure "L" level width Timer X stop control bit 0 : Count start 1 : Count stop

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer Y Timer Y is a 16-bit timer that can be selected in one of four modes. Timer mode The timer counts f(XIN)/16 (or f(XCIN)/16 in low-speed mode). Period measurement mode CNTR 1 interrupt request is generated at rising/falling edge of CNTR 1 pin input signal. Simultaneously, the value in timer Y latch is reloaded in timer Y and timer Y continues counting down. /Ex- cept for the above-mentioned, the operation in period measure- ment mode is the same as in timer mode. The timer value just before the reloading at rising/falling of CNTR pin input signal is retained until the timer Y is read once after the reload. The rising/falling timing of CNTR 1 pin input signal is found by CNTR 1 interrupt. When using a timer in this mode, set the corre- sponding port P55 direction register to input mode. Event counter mode The timer counts signals input through the CNTR1 pin. Except for this, the operation in event counter mode is the same as in timer mode. When using a timer in this mode, set the corre- sponding port P5 5 direction register to input mode. Pulse width HL continuously measurement mode CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal. Except for this, the operation in pulse width HL continuously measurement mode is the same as in period measurement mode. When using a timer in this mode, set the corresponding port P5 5 direction register to input mode. Note on CNTR 1 Interrupt Active Edge Selec- tion CNTR 1 interrupt active edge depends on the CNTR1 active edge switch bit. However, in pulse width HL continuously measurement mode, CNTR 1 interrupt request is generated at both rising and falling edges of CNTR1 pin input signal regardless of the setting of CNTR 1 active edge switch bit. Fig. 13 Structure of timer Y mode register Timer Y mode register (TYM : address 002816) Not used (return "0" when read) Timer Y operating mode bits b5 b4 0 0 : Timer mode 0 1 : Period measurement mode 1 0 : Event counter mode 1 1 : Pulse width HL continuously measurement mode CNTR 1 active edge switch bit

• CNTR1 interrupt 0 : Falling edge active 1 : Rising edge active
• Period measurement mode 0 : Measure falling edge to falling edge 1 : Measure rising edge to rising edge
• Event counter mode 0 : Rising edge active 1 : Falling edge active Timer Y stop control bit 0 : Count start 1 : Count stop

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer 1, Timer 2, Timer 3 Timer 1, timer 2, and timer 3 are 8-bit timers. The count source for each timer can be selected by timer 123 mode register. The timer latch value is not affected by a change of the count source. How- ever, because changing the count source may cause an inadvert- ent count down of the timer. Therefore, rewrite the value of timer whenever the count source is changed. Timer 2 Write Control If the timer 2 write control bit is “0”, when the value is written in the address of timer 2, the value is loaded in the timer 2 and the latch at the same time. If the timer 2 write control bit is “1”, when the value is written in the address of timer 2, the value is loaded only in the latch. The value in the latch is loaded in timer 2 after timer 2 underflows. Timer 2 Output Control When the timer 2 (TOUT ) is output enabled, an inversion signal from pin TOUT is output each time timer 2 underflows. In this case, set the port P56 shared with the port TOUT to the out- put mode. Note on Timer 1 to Timer 3 When the count source of timer 1 to 3 is changed, the timer count- ing value may be changed large because a thin pulse is generated in count input of timer. If timer 1 output is selected as the count source of timer 2 or timer 3, when timer 1 is written, the counting value of timer 2 or timer 3 may be changed large because a thin pulse is generated in timer 1 output. Therefore, set the value of timer in the order of timer 1, timer 2 and timer 3 after the count source selection of timer 1 to 3. Fig. 14 Structure of timer 123 mode register TOUT output active edge switch bit 0 : Start at "H" output 1 : Start at "L" output TOUT output control bit 0 : TOUT output disabled 1 : TOUT output enabled Timer 2 write control bit 0 : Write value in latch and counter 1 : Write value in latch only Timer 2 count source selection bit 0 : Timer 1 underflow 1 : f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) Timer 3 count source selection bit 0 : Timer 1 underflow 1 : f(XIN)/16 (Middle-/high-speed mode) f(XCIN)/16 (Low-speed mode)(Note) Timer 1 count source selection bit 0 : f(XIN)/16 (Middle-/high-speed mode) f(X CIN)/16 (Low-speed mode)(Note) 1 : f(XCIN) Not used (return "0" when read) Timer 123 mode register (T123M :address 002916) Note : Internal clock f is f (XCIN)/2 in the low-speed mode.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O1. A dedicated timer (baud rate generator) is also provided for baud rate generation. Clock Synchronous Serial I/O1 Mode Clock synchronous serial I/O1 mode can be selected by setting the mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 0018 16). Fig. 15 Block diagram of clock synchronous serial I/O1 Fig. 16 Operation of clock synchronous serial I/O1 function 1/4XIN F/F P46/SCLK1 Serial I/O1 status register Serial I/O1 control register P47/SRDY1 P44/RXD P45/TXD f(XIN) Receive buffer register (RB) Address 001816 Receive shift register Receive buffer full flag (RBF) Serial I/O receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronization clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 BRG count source selection bit Clock control circuitFalling-edge detector Data bus Address 001816 Shift clock Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Serial I/O transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit shift register Transmit buffer register (TB) D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxDWrite signal to receive/transmit buffer register (address 001816) Overrun error (OE) detection Notes 1 : The serial I/O1 transmit interrupt (TI) can be selected to occur either when the transmit buffer register has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The serial I/O1 receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous Serial I/O1 (UART) Mode Clock asynchronous serial I/O1 mode (UART) can be selected by clearing the serial I/O1 mode selection bit of the serial I/O1 control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer regis- ter, but the two buffers have the same address in memory. Since the shift register cannot be written to or read from directly, transmit data is written to the transmit buffer register, and receive data is read from the receive buffer register. The transmit buffer register can also hold the next data to be transmitted, and the receive buffer register can hold a character while the next character is being received. Fig. 17 Block diagram of UART serial I/O1 Fig. 18 Operation of UART serial I/O1 function f(XIN) OE PE FE Data bus Receive buffer register(RB) Address 001816 Receive shift register Receive buffer full flag (RBF) Serial I/O receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer register(TB) Data bus Transmit shift register Address 001816 Transmit shift register shift completion flag (TSC) Transmit buffer empty flag (TBE) Serial I/O1 status register Address 001916 STdetector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronization clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 control register P46/SCLK1 Serial I/O1 status register P44/RXD P45/TXD TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer register write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bits 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 3: The serial I/O1 receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer register read signal

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O1 Control Register (SIO1CON) 001A16 The serial I/O1 control register contains eight control bits for the serial I/O1 function. UART Control Register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TXD pin. Serial I/O1 Status Register (SIO1STS) 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer reg- ister, and the receive buffer full flag is set. A write to the serial I/O status register clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, respectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, including the error flags. All bits of the serial I/O1 status register are initialized to “0” at re- set, but if the transmit enable bit (bit 4) of the serial I/O control reg- ister has been set to “1”, the transmit shift register shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit Buffer/Receive Buffer Register (TB/ RB) 001816 The transmit buffer register and the receive buffer register are lo- cated at the same address. The transmit buffer register is write- only and the receive buffer register is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer regis- ter is “0”. Baud Rate Generator (BRG) 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift register shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: OE U PE U FE =0 1: OE U PE U FE =1 Not used (returns “1” when read) Serial I/O1 status register (SIO1STS : address 0019 16) Serial I/O1 control register (SIO1CON : address 001A16) 0 0 BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronization clock selection bit (SCS)

• In clock synchronous mode 0 : BRG output/4 1 : External clock input
• In UART mode 0 : BRG output/16 1 : External clock input/16 S RDY1 output enable bit (SRDY) 0: P47 SRDY1 pin operates as I/O port P47 1: P47 SRDY1 pin operates as signal output pin SRDY1 (SRDY1 signal indicates receive enable state) Transmit interrupt source selection bit (TIC) 0: When transmit buffer has emptied 1: When transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Clock asynchronous serial I/O1 (UART) mode 1: Clock synchronous serial I/O1 mode Serial I/O1 enable bit (SIOE) 0: Serial I/O1 disabled (pins P4 4–P4 7 operate as I/O pins) 1: Serial I/O1 enabled (pins P44–P4 7 operate as serial I/O1 pins) UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) Not used (return“1” when read) Fig. 19 Structure of serial I/O1 control registers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER SERIAL I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O2 the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Serial I/O2 Control Register (SIO2CON) 001D16 The serial I/O2 control register contains 7 bits which control vari- ous serial I/O functions. Fig. 20 Structure of serial I/O2 control register Fig. 21 Block diagram of serial I/O2 function Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronization clock select bits 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 0 0: 1 0 1: 1 1 0: f(X IN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit 0: I/O port 1: S OUT2 ,SCLK2 signal output SRDY2 output enable bit 0: I/O port 1: S RDY2 signal output Transfer direction selection bit 0: LSB first 1: MSB first Synchronization clock selection bit 0: External clock 1: Internal clock Not used (returns “0” when read) b2 b1 b0 Do not set XIN "1" "0" "0" "1" "0" "1" SRDY2 SCLK2 "0" "1" Data bus Serial I/O2 interrupt request Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O shift register 2 (8) Synchronization circuit Serial I/O2 port selection bit Synchronization clock selection bit SRDY2 output enable bit External clock Internal synchronization clock select bits Divider P53 latch P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P52 latch P51 latch

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 22 Timing of serial I/O2 function D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 register write signal (Note 2) Serial I/O2 interrupt request bit set 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Notes

control circuit consisting of the following.

• LCD display RAM
• Segment output enable register
• LCD mode register
• Selector
• Timing controller
• Common driver
• Segment driver
• Bias control circuit A maximum of 40 segment output pins and 4 common output pins can be used. Up to 160 pixels can be controlled for LCD display. When the LCD enable bit is set to “1” after data is set in the LCD mode register, Fig. 23 Structure of segment output enable register and LCD mode register Segment output enable register (SEG : address 003816) LCD mode register (LM : address 003916) Duty ratio selection bits 0 0 : Not available 0 1 : 2 (use COM0,COM 1) 1 0 : 3 (use COM0–COM 2) 1 1 : 4 (use COM0–COM 3) Bias control bit 0 : 1/3 bias 1 : 1/2 bias LCD enable bit 0 : LCD OFF 1 : LCD ON Not used (returns "0" when read) (Do not write "1" to this bit) LCD circuit divider division ratio selection bits 0 0 : LCDCK count source 0 1 : 2 division of LCDCK count source 1 0 : 4 division of LCDCK count source 1 1 : 8 division of LCDCK count source LCDCK count source selection bit (Note) 0 : f(XCIN)/32 1 : f(XIN)/8192 Segment output enable bit 0 0 : Input ports P30–P37 1 : Segment output SEG16–SEG 23 Segment output enable bit 1 0 : I/O ports P00, P01 1 : Segment output SEG24,SEG 25 Segment output enable bit 2 0 : I/O ports P02–P07 1 : Segment output SEG26–SEG 31 Segment output enable bit 3 0 : I/O ports P10,P11 1 : Segment output SEG32,SEG 33 Segment output enable bit 4 0 : I/O port P12 1 : Segment output SEG34 Segment output enable bit 5 0 : I/O ports P13–P17 1 : Segment output SEG35–SEG 39 Not used (return "0" when read) (Do not write "1" to this bit) Note : LCDCK is a clock for a LCD timing controller. the segment output enable register and the LCD display RAM, the LCD drive control circuit starts reading the display data automati- cally, performs the bias control and the duty ratio control, and dis- plays the data on the LCD panel.

Table 2. Maximum number of display pixels at each

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 24 Block diagram of LCD controller/driver Data bus Timing controller LCD divider f(XCIN) f(XIN)/ 256 Common driverBias controlSegment driver Segment driver COM 0 COM 1 COM 2 COM 3 VSS VL1 VL2 VL3SEG 3SEG 2SEG 1SEG 0 Address 004016 Address 004116 “1” “0” LCDCK LCDCK count source selection bit LCD circuit divider division ratio selection bits Bias control bit LCD enable bit Duty ratio selection bits 2 2 Selector Selector Selector Selector SelectorSelector LCD display RAM Segment driver Segment driver Segment driver Segment driver Address 005316 Common driver Common driver Common driver P16/SEG 38P30/SEG 16 P17/SEG 39

Table 3 according to the bias value. Table 3. Bias control and applied voltage to VL1–VL3 Table 4. Duty ratio control and common pins used

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER LCD Display RAM Address 004016 to 005316 is the designated RAM for the LCD dis- play. When “1” are written to these addresses, the corresponding segments of the LCD display panel are turned on. LCD Drive Timing The LCDCK timing frequency (LCD drive timing) is generated in- ternally and the frame frequency can be determined with the fol- lowing equation; (frequency of count source for LCDCK) (divider division ratio for LCD)f(LCDCK)= f(LCDCK) duty ratioFrame frequency= Fig. 26 LCD display RAM map Bit Address 004616 004716 004816 004916 004A16 004B16 004C 16 004D 16 004E16 004F16 005016 005116 005216 005316 COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 SEG 13 SEG 15 SEG 17 SEG 19 SEG 21 SEG 23 SEG 25 SEG 27 SEG 29 SEG 31 SEG 33 SEG 35 SEG 37 SEG 39 SEG 12 SEG 14 SEG 16 SEG 18 SEG 20 SEG 22 SEG 24 SEG 26 SEG 28 SEG 30 SEG 32 SEG 34 SEG 36 SEG 38 004016 004116 004216 004316 004416 004516 SEG 1 SEG 3 SEG 5 SEG 7 SEG 9 SEG 11 SEG 0 SEG 2 SEG 4 SEG 6 SEG 8 SEG 10

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 27 LCD drive waveform (1/2 bias) Internal logic LCDCK timing 1/4 duty Voltage level VL3 VL2=VL1 VSS VL3 VSS COM 0 COM 1 COM 2 COM 3 SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1/3 duty VL3 VL2=VL1 VSS VL3 VSS OFFON ON OFF ON OFF 1/2 duty COM 0 COM 1 COM 2 SEG 0 COM 0 COM 1 SEG 0 VL3 VL2=VL1 VSS VL3 VSS OFFON OFFON OFFON OFFON COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 28 LCD drive waveform (1/3 bias) Internal logic LCDCK timing 1/4 duty Voltage level VL3 VSS COM 0 COM 1 COM 2 COM 3 SEG 0 OFF ON OFF ON COM 3 COM 2 COM 1 COM 0 COM 3 COM 2 COM 1 COM 0 1/3 duty OFFON ON OFF ON OFF 1/2 duty COM 0 COM 1 COM 2 SEG 0 COM 0 COM 1 SEG 0 OFFON OFFON OFFON OFFON VL3 VL2 VSS VL1 VL3 VL2 VSS VL1 VL3 VSS VL3 VL2 VSS VL1 VL3 VSS COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 2 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0 COM 1 COM 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER WATCHDOG TIMER The watchdog timer gives a mean of returning to the reset status when a program cannot run on a normal loop (for example, be- cause of a software run-away). The watchdog timer consists of an 8-bit watchdog timer L and a 6- bit watchdog timer H. Initial Value of Watchdog Timer At reset or when writing data into the watchdog timer control reg- ister, the watchdog timer H is set to “3F 16” and the watchdog timer L is set to “FF16”. As a write instruction, it is possible to use any in- struction that can cause a write signal such as STA, LDM and CLB. Write data except bit 7 has no significance and the above value is set independently. Watchdog Timer Operation The watchdog timer stops at reset and starts a countdown by writ- ing to the watchdog timer control register. When the watchdog timer H underflows, an internal reset occurs, and the reset status is released after waiting the reset release time. Then the program executes from the reset vector address. Usually, a program is designed so that data can be written into the watchdog timer control register before the watchdog timer H underflows. If data is not written once into the watchdog timer con- trol register, the watchdog timer does not function. At execution of the STP instruction, both clock and watchdog timer stops. At the same time that the stop mode is released, the watch- dog timer restarts a count (Note). On the other hand, at execution of the WIT instruction, the watchdog timer does not stop. The time from execution of writing to the watchdog timer control register until an underflow of the watchdog timer register H is as follows: (When bit 7 of the watchdog timer control register is “0”) Note: During the stop release wait time [XIN (or XCIN) : about 8200 clock cycles], the watchdog timer counts. Accordingly, does not underflow the watchdog timer H. Fig. 30 Structure of watchdog timer control register Fig. 29 Watchdog timer block diagram XIN Data bus XCIN “1” “0” Internal system clock selection bit (Note) “0” “1”1/16 Watchdog timer H count source selection bit Reset circuit Undefined instruction Reset Watchdog timer H (6) When writing to watchdog timer control register set “3F16” Internal resetRESET Watchdog timer L (8) When writing to watchdog timer control register set “FF 16” Note: This bit is bit 7 of CPU mode register. It selects the mode (middle/high-speed or low-speed) Reset release wait time (about 8200 XIN clock cycles) Watchdog timer H bits (read only) Not used (returns “1” when read) Watchdog timer H count source selection bit 0 : Underflow from watchdog timer L 1 : f(XIN)/16 or f(XCIN)/16 Watchdog timer control register (WDTCON : address 003716) 7 0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER φ CLOCK OUTPUT FUNCTION The internal system clock φ can be output from port P41 by setting the φ output control register. Set bit 1 of the port P4 direction reg- ister to when outputting φ clock. Fig. 31 Structure of φ output control register 7 0 φ output control register (CKOUT : address 002A16) φ output control bit 0 : Port function 1 :φ clock output Not used (return “0” when read)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Register contents (000116) • • • Timer Y (low-order) Port P0 direction register Port P1 direction register Port P2 direction register PULL register B Timer Y (high-order) Serial I/O1 control register UART control register Serial I/O2 control register Timer X (high-order) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (0003 16) • • • (000516) • • • (001716) • • • (001A16) • • • (001B16) • • • (001D16) • • • (002016) • • • (002116) • • • (002216) • • • (002316) • • • (002416) • • • (002516) • • • (002616) • • • (002716) • • • (002816) • • • (002916) • • • (002A16) • • • Address Timer X (low-order) Timer 1 Timer 2 Timer 3 Timer X mode register Timer Y mode register Timer 123 mode register φ output control register 0016 0016 0016 FF16 0116 FF16 FF16 FF16 FF16 FF16 0016 0016 0016 Port P7 direction register(000F16) • • • 0016 111000 0 0 Serial I/O1 status register(001916) • • • 100000 0 0 Port P4 direction register Port P5 direction register Port P6 direction register (000916) • • • (000B16) • • • 0016 0016 0016 0016 0016 (25) (26) (27) (0037 16) • • • (003816) • • • (003916) • • • Watchdog timer control register Segment output enable register LCD mode register 0016 PULL register A (001616) • • • 000010 1 1 Note. 5 : Undefined The contents of all other registers and RAM are undefined at poweron reset, so they must be initialized by software. (28) (29) (30) (31) (32) (33) (34) (35) (003A 16) • • • (003B16) • • • (003C16) • • • (003D16) • • • (003E16) • • • Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter 0016 0016 0016 0016 010010 0 0 0016 Contents of address FFFC16 55555 1 55(PS) (PCH ) (PCL) Contents of address FFFD16 (003F16) • • • 0016 011111 1 1 0016 RESET CIRCUIT T o reset the microcomputer, RESET pin should be held at an “L” level for 2 µ s or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 2.5 V and 5.5 V, and the oscillation should be stable), reset is released. In or- der to give the X IN clock time to stabilize, internal operation does not begin until after 8200 XIN clock cycles (timer 1 and timer 2 are connected together and 512 cycles of f(XIN)/16) are complete. Af- ter the reset is completed, the program starts from the address contained in address FFFD 16 (high-order byte) and address FFFC 16 (low-order byte). Make sure that the reset input voltage is less than 0.5 V for VCC of

2.5 V (Extended operating temperature version: the reset input

voltage is less than 0.6V for V CC of 3.0V). Fig. 33 Internal state of microcomputer immediately after re- set Fig. 32 Example of reset circuit (Note) 0.2VCC Note. Reset release voltage : VCC = 2.5V (Extended operating temperature version : 3.0V) Power on VCCRESET VCCRESET Power source voltage detection circuit Reset input voltage Power source voltage

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 34 Reset sequence FFFC FFFD AD H, AD L?? ? ? XIN : about 8200 clock cycles Notes 1 : XIN and f are in the relation : f(XIN) = 8• f(f) Notes 2 : A question mark (?) indicates an undefined status that depens on the previous status. Reset address from vector table RESET Internal reset Address Data SYNC f XIN AD L AD H

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER CLOCK GENERATING CIRCUIT The 3820 group has two built-in oscillation circuits. An oscillation circuit can be formed by connecting a resonator between XIN and XOUT (XCIN and XCOUT ). Use the circuit constants in accordance with the resonator manufacturer's recommended values. No exter- nal resistor is needed between X IN and XOUT since a feed-back re- sistor exists on-chip. However, an external feed-back resistor is needed between X CIN and XCOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. The sub-clock XCIN-XCOUT oscillation circuit cannot directly input clocks that are externally generated. Accord- ingly, be sure to cause an external resonator to oscillate. Immediately after poweron, only the X IN oscillation circuit starts oscillating, and XCIN and XCOUT pins function as I/O ports. The pull-up resistor of XCIN and XCOUT pins must be made invalid to use the sub-clock. Frequency Control Middle-speed mode The internal clock φ is the frequency of X IN divided by 8. After reset, this mode is selected. High-speed mode The internal clock φ is half the frequency of XIN. Low-speed mode

• The internal clock φ is half the frequency of XCIN.
• A low-power consumption operation can be realized by stopping the main clock XIN in this mode. To stop the main clock, set bit 5 of the CPU mode register to “1”. When the main clock X IN is restarted, set enough time for oscil- lation to stabilize by programming. Note: If you switch the mode between middle/high-speed and low- speed, stabilize both XIN and XCIN oscillations. The suffi- cient time is required for the sub-clock to stabilize, espe- cially immediately after poweron and at returning from stop mode. When switching the mode between middle/high- speed and low-speed, set the frequency on condition that f(X IN)>3f(XCIN). Fig. 35 Ceramic resonator circuit Fig. 36 External clock input circuit XCIN XCOUT XIN XOUT C IN C OUTC CIN C COUT Rf Rd XIN XOUT External oscillation circuit Open VCC VSS C CIN C COUT Rf Rd XCIN XCOUT Oscillation Control Stop mode If the STP instruction is executed, the internal clock φ stops at an “H” level, and XIN and XCIN oscillators stop. Timer 1 is set to “FF16” and timer 2 is set to “0116”. Either XIN or XCIN divided by 16 is input to timer 1 as count source, and the output of timer 1 is connected to timer 2. The bits of the timer 123 mode register except bit 4 are cleared to “0”. Set the timer 1 and timer 2 interrupt enable bits to disabled (“0”) before executing the STP instruction. Oscillator restarts at reset or when an external interrupt is re- ceived, but the internal clock φ is not supplied to the CPU until timer 2 underflows. This allows time for the clock circuit oscillation to stabilize. Wait mode If the WIT instruction is executed, the internal clock φ stops at an “H” level. The states of X IN and XCIN are the same as the state be- fore the executing the WIT instruction. The internal clock restarts at reset or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 37 Clock generating circuit block diagram WIT instruction STP instruction Timing f (Internal system clock) S R Q STP instruction S R Q Main clock stop bit S R Q Timer 2Timer 11/2 1/4 XIN XOUT XCOUTXCIN Interrupt request Interrupt disable flag I Reset Port XC switch bit "1" "0" "1" "0" Timer 1 count source selection bit "0" "1" Timer 2 count source selection bit Low-speed mode Middle/High-speed mode Internal system clock selection bit (Note 1) Middle-speed mode High-speed mode or Low-speed mode Note : When using the low-speed mode, set the port XC switch bit to "1" . Main clock division ratio selection bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 38 State transitions of internal clock φ CM 4 : Port Xc switch bit 0: I/O port 1: XCIN, XCOUT CM 5 : Main clock (XIN–XOUT ) stop bit 0: Oscillating 1: Stopped CM 6: Main clock division ratio selection bit 0: f(XIN)/2 (high-speed mode) 1: f(XIN)/8 (middle-speed mode) CM 7: Internal system clock selection bit 0: XIN–XOUT selected (middle-/high-speed mode) 1: X CIN–XCOUT selected (low-speed mode) Notes ResetCM 4 CM 7 CM 4CM 5 CM 6 CM 6 CPU mode register (CPUM : address 003B16) 7 4 CM 7CM 5 CM 6 CM 6 "0""1" "0""1" "0""1" "0""1" CM 4CM 6 "1" "0" "0" "1"CM CM 6 "0" "1" "0" "1" CM 5CM 6 "1" "0" "0" "1"CM CM 6 "0" "1" "0" "1" CM 7=0(8MHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=0(32kHz stopped) CM 7=0(8MHz selected) CM 6=0(High-speed) CM 5=0(8MHz oscillating) CM 4=0(32kHz stopped) CM 7=0(8MHz selected) CM 6=0(High-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=0(High-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=0(High-speed) CM 5=1(8MHz stopped) CM 4=1(32kHz oscillating) CM 7=0(8MHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=1(Middle-speed) CM 5=0(8MHz oscillating) CM 4=1(32kHz oscillating) CM 7=1(32kHz selected) CM 6=1(Middle-speed) CM 5=1(8MHz stopped) CM 4=1(32kHz oscillating) Low-speed mode (f(φ) =16 kHz)Low-speed mode (f(φ) =16 kHz) Low-speed mode (f(φ) =16 kHz) Low-speed mode (f(φ) =16 kHz) High-speed mode (f(φ) =4MHz)Middle-speed mode (f(φ) =1 MHz) Middle-speed mode (f(φ) =1 MHz) High-speed mode (f(φ) =4MHz) t XIN before the switching from the low-speed mode to middle-/high- 1: Switch the mode by the allows shown between the mode blocks. (Do not switch between the mode directly without an allow.) 2: The all modes can be switched to the stop mode or the wait mode and returned to the source mode when the stop mode or the wai mode is released. 3: Timer and LCD operate in the wait mode. 4: In middle-/high-speed mode, when the stop mode is released, a delay of approximately 1 ms occurs automatically by timer 1 and timer 2. 5: In low-speed mode, when the stop mode is released, a delay of approximately 0.25 s occurs automatically by timer 1 and timer 6: Wait until oscillation stabilizes after oscillating the main clock speed mode. 7: The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin. φ indicates the internal clock.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt re- quest register, execute at least one instruction before performing a BBC or BBS instruction. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index mode (T) and the decimal mode (D) flags do not affect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:

• The data transfer instruction (LDA, etc.)
• The operation instruction when the index X mode flag (T) is “1”
• The addressing mode which uses the value of a direction regis- ter as an index
• The bit-test instruction (BBC or BBS, etc.) to a direction register
• The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY signal, set the transmit en- able bit, the receive enable bit, and the SRDY output enable bit to “1”. Serial I/O1 continues to output the final bit from the T X D pin after transmission is completed. The SOUT2 pin from serial I/O2 goes to high impedance after transmission is completed. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: (1) Mask ROM Order Confirmation Form (2) Mark Specification Form (3) Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built- in EPROM version can be read or programmed with a general- purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 39 is recommended to verify programming. Fig. 39 Programming and testing of One Time PROM version Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Caution : Package 80P6N-A 80P6S-A 80P6D-A 80D0 Name of Programming Adapter PCA4738F-80A PCA4738G-80 PCA4738H-80 PCA4738L-80A

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS RECOMMENDED OPERATING CONDITIONS ABSOLUTE MAXIMUM RATINGS Power source voltage Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60, P61, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00–P07, P10–P1 7 Output voltage P30–P3 7 Output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 Output voltage SEG0–SEG 15 Output voltage XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VI VO VO VO VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 125 V V V V V V V V V V V V mW Unit All voltages are based on VSS . Output transistors are cut off. At output port At segment output At segment output T a = 25 °C (VCC = 2.5 to 5.5 V , Ta = –20 to 85 °C, unless otherwise noted.) 5.5 5.5 5.5 V CC VCC VCC VCC

0.3 VCC

0.2 VCC

High-speed mode f(XIN)=8 MHz Power source voltage Middle-speed mode f(X IN)=8 MHz Low-speed mode Power source voltage “H” input voltage P0 0–P0 7, P10–P1 7, P30–P3 7, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “H” input voltage P2 0–P2 7, P42–P4 4, P46, P50, P52, P54, P55, P57, P60 “H” input voltage RESET “H” input voltage X IN “L” input voltage P0 0–P0 7, P10–P1 7, P30–P3 7, P40, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “L” input voltage P2 0–P2 7, P42–P4 4, P46, P50, P52, P54, P55, P57, P60 “L” input voltage RESET “L” input voltage X IN VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL Symbol Parameter Limits Min. V V V V V V V V V V Unit 4.0 2.5 2.5 0.7 V CC

0.8 VCC

5.0 5.0 5.0 Typ. Max.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS RECOMMENDED OPERATING CONDITIONS (VCC = 2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av erage value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:When the oscillation frequency has a duty cycle of 50 %. 5:When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than f(XIN)/3. –40 –40 –20 –20 –1.0 –2.5 2.5 5.0 8.0 (4XVCC )–8 8.0 “H” total peak output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “H” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L” total peak output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “L” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” total average output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “H” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L” total average output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “L” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 2) “L” peak output current P00–P07, P10–P17 (Note 2) “L” peak output current P2 0–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 2) “H” average output current P00–P0 7, P10–P1 7 (Note 3) “H” average output current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 3) “L” average output current P00–P0 7, P10–P1 7 (Note 3) “L” average output current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 3) Clock input frequency for timers X and Y (duty cycle 50 %) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) Σ IOH(peak) Σ IOH(peak) Σ IOL(peak) Σ IOL(peak) Σ IOH(avg) Σ IOH(avg) Σ IOL(avg) Σ IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR 0) f(CNTR 1) f(XIN) f(XCIN) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz Unit Typ. Max. 4.0 V ≤ VCC ≤ 5.5 V VCC ≤ 4.0 V 32.768 High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode 4.0 (2XVCC )–4 MHz MHz

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. “H” output voltage P00–P0 7, P10–P1 7, P30–P3 7 “H” output voltage P20–P2 7, P41–P4 7,P50–P57, P60, P61, P70, P71 (Note 1) “L” output voltage P00–P0 7, P10–P1 7, P30–P3 7 “L” output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 1) Hysteresis CNTR 0, CNTR1, INT0–INT3, P20–P2 7 Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P30–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P5 7, P60, P61, P70, P71 “H” input current RESET “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P30–P3 7, P40, P70 “L” input current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P71 “L” input current RESET “L” input current XIN RAM hold voltage Symbol Parameter Limits Min. V V V V V V V V V V V V V V µ A µ A µ A µ A µ A µ A µ A µ A µ A µ A µ A µ A V Unit 0.5 0.5 0.5 4.0 –70 –25 –4.0 Typ. Max. IOH = –0.1 mA IOH = –25 µA VCC = 2.5 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.5 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.5 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.5 V RESET: VCC =2.5 V to 5.5 V VI = VCC Pull-downs “off” V CC = 5.0 V, VI = VCC Pull-downs “on” V CC = 3.0 V, VI = VCC Pull-downs “on” VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” V CC = 3.0 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS When clock is stopped Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIH IIL IIL IIL IIL VRAM VOH VOH VOL VOL VCC –2.0 VCC –1.0 VCC –2.0 VCC –0.5 VCC –1.0 6.0 –30 2.0 2.0 0.5 1.0 2.0 0.5 1.0 5.0 140 5.0 5.0 –5.0 –5.0 –140 –45 –5.0 5.5 ELECTRICAL CHARACTERISTICS (VCC =4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. Unit ELECTRICAL CHARACTERISTICS (VCC =2.5 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.) Typ. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC mA mA µA µA µA µA µA Power source current

• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off”
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, T a = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V , T a ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3V, T a = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” 6.4 1.6 7.0 4.5 0.1 3.2 14.0 9.0 1.0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R X D) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–SCLK2 ) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) 125 250 105 105 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R X D) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–SCLK2 ) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit TIMING REQUIREMENTS 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) 125 500/ CC –2) 250/ (VCC –2)–20 250/ (VCC –2)–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 0.25t C (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) tc(SCLK1 )/2–30 tc(SCLK1 )/2–30 –30 tc(SCLK2 )/2–160 tc(SCLK2 )/2–160 Typ. Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 0.25 t C (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit SWITCHING CHARACTERISTICS 2 (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) tc(SCLK1 )/2–50 tc(SCLK1 )/2–50 –30 tc(SCLK2 )/2–240 tc(SCLK2 )/2–240 Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes1:When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Typ.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS ABSOLUTE MAXIMUM RATINGS (Extended Operating Temperature Version) RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version) Power source voltage Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60, P61, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00–P07, P10–P1 7 Output voltage P30–P3 7 Output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 Output voltage SEG0–SEG 15 Output voltage XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VI VO VO VO VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 300 –40 to 85 –65 to 150 V V V V V V V V V V V V mW Unit All voltages are based on VSS . Output transistors are cut off. At output port At segment output At segment output T a = 25 °C 5.5 5.5 5.5 5.5 High-speed mode f(X IN)=8 MHz Middle-speed mode Power source voltage f(X IN)=8 MHz Low-speed mode Power source voltage “H” input voltage P0 0–P0 7, P10–P1 7, P30–P3 7, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “H” input voltage P2 0–P2 7, P42–P4 4, P46, P50,P 52, P54, P55, P57, P60 “H” input voltage RESET “H” input voltage X IN “L” input voltage P0 0–P0 7, P10–P1 7, P30–P3 7, P40, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “L” input voltage P2 0–P2 7, P42–P4 4, P46, P50,P 52, P54, P55, P57, P60 VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL Symbol Parameter Limits Min. V V V V V V V V V V Unit 4.0 2.5 3.0 5.0 5.0 5.0 Typ. Max. Ta = –20 to 85 °C Ta = –40 to –20 °C Ta = –20 to 85 °C Ta = –40 to –20 °C 2.5 3.0

0.7 VCC

5.0 5.5 VCC VCC VCC VCC “L” input voltage RESET “L” input voltage X IN 5.0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS RECOMMENDED OPERATING CONDITIONS (Extended Operating Temperature Version) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av erage value measured over 100 ms. The total peak current is the peak value of all the currents. 2: The peak output current is the peak current flowing in each port. 3: The average output current is an average value measured over 100 ms. 4: When the oscillation frequency has a duty cycle of 50 %. 5: When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than f(XIN)/3. –40 –40 –20 –20 –1.0 –2.5 2.5 5.0 8.0 (4XVCC )–8 8.0 “H” total peak output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “H” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L” total peak output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “L” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” total average output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “H” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L” total average output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “L” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 2) “L” peak output current P00–P07, P10–P17 (Note 2) “L” peak output current P2 0–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 2) “H” average output current P00–P0 7, P10–P1 7 (Note 3) “H” average output current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 3) “L” average output current P00–P0 7, P10–P1 7 (Note 3) “L” average output current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 3) Clock input frequency for timers X and Y (duty cycle 50 %) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) Σ IOH(peak) Σ IOH(peak) Σ IOL(peak) Σ IOL(peak) Σ IOH(avg) Σ IOH(avg) Σ IOL(avg) Σ IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR 0) f(CNTR 1) f(XIN) f(XCIN) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz Unit Typ. Max. 4.0 V ≤ VCC ≤ 5.5 V VCC ≤ 4.0 V 32.768 High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode 4.0 (2XVCC )–4 MHz MHz

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Note :When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. “H” output voltage P00–P0 7, P10–P1 7, P30–P3 7 “H” output voltage P20–P2 7, P41–P4 7,P50–P57, P60, P61, P70, P71 (Note) “L” output voltage P00–P0 7, P10–P1 7, P30–P3 7 “L” output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note) Hysteresis CNTR 0, CNTR1, INT0–INT3, P20–P2 7 Hysteresis R X D, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P30–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P5 7, P60, P61, P70, P71 “H” input current RESET “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P30–P3 7, P40, P70 “L” input current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P71 “L” input current RESET “L” input current XIN RAM hold voltage Symbol Parameter Limits Min. V V V V V V V V V V V V V V µ A µ A µ A µ A µ A µ A µ A µ A µ A µ A µ A µ A V Unit ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version) 0.5 0.5 0.5 4.0 –70 –25 –4.0 Typ. Max. IOH = –2.5 mA IOH = –0.6 mA VCC = 3.0 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 3.0 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 3.0 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 3.0 V RESET: VCC =3.0 V to 5.5 V VI = VCC Pull-downs “off” V CC = 5.0 V, VI = VCC Pull-downs “on” V CC = 3.0 V, VI = VCC Pull-downs “on” VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” V CC = 3.0 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS When clock is stopped Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIH IIL IIL IIL IIL VRAM VOH VOH VOL VOL VCC –2.0 VCC –0.9 VCC –2.0 VCC –0.5 VCC –0.9 6.0 –30 2.0 2.0 0.5 1.1 2.0 0.5 1.1 5.0 170 5.0 5.0 –5.0 –5.0 –140 –45 –5.0 5.5

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS All oscillation stopped (in STP state) Output transistors “off” Symbol Parameter Limits Min. Unit ELECTRICAL CHARACTERISTICS (Extended Operating Temperature Version) Typ. Max. Ta = 25 °C Ta = 85 °C Test conditions ICC mA mA µA µA µA µA µA Power source current

• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off”
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V, T a = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V , T a ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3V, T a = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” 6.4 1.6 7.0 4.5 0.1 3.2 14.0 9.0 1.0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RXD–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted.) 125 250 105 105 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RXD–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 125 500/ CC –2) 250/ (VCC –2)–20 250/ (VCC –2)–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART). TIMING REQUIREMENTS 1 (Extended Operating Temperature Version) TIMING REQUIREMENTS 2 (Extended Operating Temperature Version)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 0.25 t C (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted.) tc(SCLK1 )/2–30 tc(SCLK1 )/2–30 –30 tc(SCLK2 )/2–160 tc(SCLK2 )/2–160 Typ. Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TX D) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –SOUT2 ) tv(SCLK2 –S OUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 0.25 t C (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(SCLK1 )/2–50 tc(SCLK1 )/2–50 –30 tc(SCLK2 )/2–240 tc(SCLK2 )/2–240 Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TXD) tv(SCLK1 –TX D) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –SOUT2 ) tv(SCLK2 –S OUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. Typ. SWITCHING CHARACTERISTICS 1 (Extended Operating Temperature Version) SWITCHING CHARACTERISTICS 2 (Extended Operating Temperature Version) Measurement output pin 100pF CMOS output Note: When bit 4 of the UART control register (address 001B16) is “1”. (N-channel open-drain output mode) Measurement output pin 100pF N-channel open-drain output (Note) 1kΩ Fig.40 Circuit for measuring output switching characteristics

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Power source voltage Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60, P61, P70, P71 Input voltage VL1 Input voltage VL2 Input voltage VL3 Input voltage RESET, XIN Output voltage P00–P0 7, P10–P1 7 Output voltage P30–P3 7 Output voltage P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 Output voltage SEG0–SEG 15 Output voltage XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VI VI VO VO VO VO VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VL2 VL1 to VL3 VL2 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 –0.3 to VL3 +0.3 –0.3 to VCC +0.3 300 –20 to 85 –40 to 150 V V V V V V V V V V V V mW Unit All voltages are based on VSS . Output transistors are cut off. At output port At segment output At segment output T a = 25 °C (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.) 5.5 5.5 5.5 V CC VCC VCC VCC High-speed mode f(XIN)=8 MHz Power source voltage Middle-speed mode f(X IN)=8 MHz Low-speed mode Power source voltage “H” input voltage P0 0–P0 7, P10–P1 7, P30–P3 7, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “H” input voltage P2 0–P2 7, P42–P4 4, P46, P50, P52, P54, P55, P57, P60 “H” input voltage RESET “H” input voltage X IN “L” input voltage P0 0–P0 7, P10–P1 7, P30–P3 7, P40, P41, P45, P47, P51, P53, P56, P61, P70, P71 (CM4=0) “L” input voltage P2 0–P2 7, P42–P4 4, P46, P50, P52, P54, P55, P57, P60 “L” input voltage RESET “L” input voltage X IN VCC VSS VIH VIH VIH VIH VIL VIL VIL VIL Symbol Parameter Limits Min. V V V V V V V V V V Unit 4.0 2.2 2.2 0.7 V CC 5.0 5.0 5.0 Typ. Max. ABSOLUTE MAXIMUM RATINGS (Low Power Source Voltage Version) RECOMMENDED OPERATING CONDITIONS (Low Power Source Voltage Version)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS RECOMMENDED OPERATING CONDITIONS (Low Power Source Voltage Version) (VCC = 2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.) Notes 1: The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an av erage value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current is an average value measured over 100 ms. 4:When the oscillation frequency has a duty cycle of 50 %. 5:When using the microcomputer in low-speed mode, make sure that the sub-clock input oscillation frequency f(XCIN) is less than f(XIN)/3. –40 –40 –20 –20 –1.0 –2.5 2.5 5.0 8.0 8.0 “H” total peak output current P00–P07, P10–P17, P20–P2 7 (Note 1) “H” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L” total peak output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “L” total peak output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” total average output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “H” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “L” total average output currentP00–P07, P10–P17, P20–P2 7 (Note 1) “L” total average output current P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 2) “L” peak output current P00–P07, P10–P17 (Note 2) “L” peak output current P2 0–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 2) “H” average output current P00–P0 7, P10–P1 7 (Note 3) “H” average output current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 3) “L” average output current P00–P0 7, P10–P1 7 (Note 3) “L” average output current P20–P2 7, P41–P4 7, P50–P5 7, P60, P61, P70, P71 (Note 3) Clock input frequency for timers X and Y (duty cycle 50 %) Main clock input oscillation frequency (Note 4) Sub-clock input oscillation frequency (Note 4, 5) Σ IOH(peak) Σ IOH(peak) Σ IOL(peak) Σ IOL(peak) Σ IOH(avg) Σ IOH(avg) Σ IOL(avg) Σ IOL(avg) IOH(peak) IOL(peak) IOL(peak) IOH(avg) IOH(avg) IOL(avg) IOL(avg) f(CNTR 0) f(CNTR 1) f(XIN) f(XCIN) Symbol Parameter Limits Min. mA mA mA mA mA mA mA mA mA mA mA mA mA mA mA MHz MHz MHz kHz Unit Typ. Max. 4.0 V ≤ VCC ≤ 5.5 V VCC ≤ 4.0 V 32.768 High-speed mode (4.0 V ≤ VCC ≤ 5.5 V) High-speed mode (VCC ≤ 4.0 V) Middle-speed mode 4.0 (10XVCC –4) MHz MHz (20XVCC –8)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Note : When “1” is set to port XC switch bit (bit 4 of address 003B16) of CPU mode register, the drive ability of port P70 is different from the value above mentioned. “H” output voltage P00–P0 7, P10–P1 7, P30–P3 7 “H” output voltage P20–P2 7, P41–P4 7,P50–P5 7, P60, P61, P70, P71 (Note) “L” output voltage P00–P0 7, P10–P1 7, P30–P3 7 “L” output voltage P20–P2 7, P41–P4 7, P50–P57, P60, P61, P70, P71 (Note) Hysteresis CNTR 0, CNTR1, INT0–INT3, P20–P2 7 Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P30–P3 7 “H” input current P20–P2 7, P40–P4 7, P50–P57, P60, P61, P70, P71 “H” input current RESET “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P30–P37, P40, P70 “L” input current P20–P2 7, P41–P4 7, P50–P57, P60, P61, P71 “L” input current RESET “L” input current XIN Symbol Parameter Limits Min. V V V V V V V V V V V V V V µA µA µA µA µA µA µA µA µA µA µA µA Unit (VCC =4.0 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.) 0.5 0.5 0.5 8.0 4.0 –70 –25 –8.0 Typ. Max. IOH = –0.1 mA IOH = –25 µ A VCC = 2.2 V IOH = –5 mA IOH = –1.25 mA IOH = –1.25 mA VCC = 2.2 V IOL = 5 mA IOL = 1.25 mA IOL = 1.25 mA VCC = 2.2 V IOL = 10 mA IOL = 2.5 mA IOL = 2.5 mA VCC = 2.2 V RESET : VCC =2.2 V to 5.5 V VI = VCC Pull-downs “off” V CC = 5.0 V, VI = VCC Pull-downs “on” V CC = 3.0 V, VI = VCC Pull-downs “on” VI = VCC VI = VCC VI = VCC VI = VSS Pull-ups “off” VCC = 5.0 V, VI = VSS Pull-ups “on” V CC = 3.0 V, VI = VSS Pull-ups “on” V I = VSS VI = VSS Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIH IIL IIL IIL IIL VOH VOH VOL VOL VCC –2.0 VCC –1.0 VCC –2.0 VCC –0.5 VCC –1.0 6.0 –30 2.0 0.5 1.1 2.0 0.5 1.0 5.0 170 5.0 5.0 –5.0 –5.0 –140 –45 –5.0 ELECTRICAL CHARACTERISTICS (Low Power Source Voltage Version)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS All oscillation stopped (in STP state) Output transistors “off” Symbol VRAM Parameter RAM hold voltage Limits Min. 2.0 Unit V ELECTRICAL CHARACTERISTICS (Low Power Source Voltage Version) (VCC =2.2 to 5.5 V, Ta = –20 to 85 °C, unless otherwise noted.) Typ. Max. 5.5 Ta = 25 °C Ta = 85 °C Test conditions ICC mA mA µ A µ A µ A µ A µ A Power source current

• High-speed mode, VCC = 5 V f(XIN) = 8 MHz f(XCIN) = 32.768 kHz Output transistors “off”
• High-speed mode, VCC = 5 V f(XIN) = 8 MHz (in WIT state) f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5V, Ta ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 5 V , T a = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off”
• Low-speed mode, VCC = 3 V , T a ≤ 55°C f(XIN) = stopped f(XCIN) = 32.768 kHz Output transistors “off”
• Low-speed mode, VCC = 3V, Ta = 25°C f(XIN) = stopped f(XCIN) = 32.768 kHz (in WIT state) Output transistors “off” 6.4 1.6 7.0 4.5 0.2 3.2 14.0 9.0 2.0 When clock is stopped

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RX D–S CLK1 ) th(SCLK1 –R X D) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–SCLK2 ) th(SCLK2 –SIN2) Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0” (UART). Reset input “L” pulse width Main clock input cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) TIMING REQUIREMENTS 1 (Low Power Source Voltage Version) 125 250 105 105 800 370 370 220 100 1000 400 400 200 200 Typ. Max. Reset input “L” pulse width Main clock iuput cycle time (XIN input) Main clock input “H” pulse width Main clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT3 input “H” pulse width INT0 to INT3 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O1 clock input “H” pulse width (Note) Serial I/O1 clock input “L” pulse width (Note) Serial I/O1 input set up time Serial I/O1 input hold time Serial I/O2 clock input cycle time Serial I/O2 clock input “H” pulse width Serial I/O2 clock input “L” pulse width Serial I/O2 input set up time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twL(CNTR) twH(INT) twL(INT) tc(SCLK1 ) twH(S CLK1 ) twL(SCLK1 ) tsu(RXD–S CLK1 ) th(SCLK1 –R XD) tc(SCLK2 ) twH(S CLK2 ) twL(SCLK2 ) tsu(SIN2–S CLK2 ) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 2.5 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) 125 900/ (VCC –0.4) 450/ (VCC –0.4)–20 450/ (VCC –0.4)–20 230 230 2000 950 950 400 200 2000 950 950 400 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1” (clock synchronous). Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0” (UART). TIMING REQUIREMENTS 2 (Low Power Source Voltage Version)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS Measurement output pin 100pF CMOS output Note: When bit 4 of the UART control register (address 001B16) is “1”. (N-channel open-drain output mode) Measurement output pin 100pF N-channel open-drain output (Note) 1kW Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 140 0.25t C (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) tc(SCLK1 )/2–30 tc(SCLK1 )/2–30 –30 tc(SCLK2 )/2–160 tc(SCLK2 )/2–160 Typ. Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes 1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. SWITCHING CHARACTERISTICS 1 (Low Power Source Voltage Version) Serial I/O1 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O1 output valid time (Note 1) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output “H” pulse width Serial I/O2 clock output “L” pulse width Serial I/O2 output delay time Serial I/O2 output valid time Serial I/O2 clock output falling time CMOS output rising time (Note 2) CMOS output falling time (Note 2) 350 0.25 t C (SCLK2 ) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns Unit (VCC = 2.2 to 4.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted.) tc(SCLK1 )/2–50 tc(SCLK1 )/2–50 –30 tc(SCLK2 )/2–240 tc(SCLK2 )/2–240 Max. twH(S CLK1 ) twL(SCLK1 ) td(SCLK1 –TX D) tv(SCLK1 –TXD) tr(SCLK1 ) tf(SCLK1 ) twH(S CLK2 ) twL(SCLK2 ) td(SCLK2 –S OUT2 ) tv(SCLK2 –SOUT2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Notes 1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: XOUT and XCOUT pins are excluded. SWITCHING CHARACTERISTICS 2 (Low Power Source Voltage Version) Typ. Fig.41 Circuit for measuring output switching characteristics

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER MITSUBISHI MICROCOMPUTERS 0.2VCC tf 0.2VCC 0.8VCC 0.8VCC tr 0.2VCC tWL(X IN) 0.8VCC tWH(X IN) tC(XIN) XIN 0.2VCC 0.8VCC tW(RESET) RESET 0.2VCC tWL(CNTR) 0.8VCC tWH(CNTR) tC(CNTR) 0.2VCC tWL(INT) 0.8VCC tWH(INT) CNTR 0,CNTR 1 INT0–INT3 TXD SOUT2 R XD SIN2 SCLK1 SCLK2 td(SCLK1 -TXD),td(SCLK2 -SOUT2 ) tsu(RXD-SCLK1 ) tsu(SIN2-SCLK2 ) th(SCLK1 -RXD) th(SCLK2 -SIN2) tv(SCLK1 -TXD), tv(SCLK2 -SOUT2 ) tC(SCLK1 ),tC(SCLK2 ) tWL(S CLK1 ),tWL(S CLK2 ) tWH(S CLK1 ),tWH(S CLK2 ) TIMING DIAGRAM

© 1996 MITSUBISHI ELECTRIC CORP. H-DF047-C KI-9609 New publication, effective Sep. 1996. Specifications subject to change without notice. Notes regarding these materials

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• Mitsubishi Electric Corporation puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of non-flammable material or (iii) prevention against any malfunction or mishap. MITSUBISHI MICROCOMPUTERS 3820Group SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date

1.0 First Edition 971128

REVISION DESCRIPTION LIST 3820GROUP DATA SHEET (1/1) Revision Description