3802

Mitsubishi Electric Sem...

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

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M38027E8SP MITSUBISHI | Alldatasheet

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Technical content

PIN CONFIGURATION (TOP VIEW) Package type : 64P6N-A 64-pin plastic-molded QFP

DESCRIPTION

The 3802 group is the 8-bit microcomputer based on the 740 fam- ily core technology. The 3802 group is designed for controlling systems that require analog signal processing and include two serial I/O functions, A-D converters, and D-A converters. The various microcomputers in the 3802 group include variations of internal memory size and packaging. For details, refer to the section on part numbering. For details on availability of microcomputers in the 3802 group, re- fer to the section on group expansion.

FEATURES

(at 8 MHz oscillation frequency)

Memory size (connect to external ceramic resonator or quartz-crystal oscillator) (Extended operating temperature version : 4.0 to 5.5 V)
Memory expansion possible (Extended operating temperature version : –40 to 85°C)

APPLICATIONS

Office automation, VCRs, tuners, musical instruments, cameras, air conditioners, etc. MITSUBISHI MICROCOMPUTERS

3802 Group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN CONFIGURATION (TOP VIEW) Package type : 64P4B 64-pin shrink plastic-molded DIP P64/AN4 P66/AN6 P67/AN7 AV SS VREF VCC P63/AN3 P65/AN5 P62/AN2 P61/AN1 P60/AN0 P57/INT3 P56/PWM P55/CNTR 1 P54/CNTR 0 P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P47/SRDY1 P46/SCLK1 P43/INT2 P44/RXD P45/TXD CNV SS P41/INT0 P40/INT4 XIN XOUT VSS P42/INT1 RESET P24/DB4 P23/DB3 P22/DB2 P20/DB0 P21/DB1 P25/DB5 P27/DB7 P26/DB6 P33/RESET OUT P34/f P35/SYNC P37/RD P36/WR P32/ONW P30/DA1 P31/DA2 P00/AD0 P01/AD1 P02/AD2 P03/AD3 P04/AD4 P05/AD5 P06/AD6 P07/AD7 P10/AD8 P11/AD9 P12/AD10 P13/AD11 P14/AD12 P17/AD15 P16/AD14 P15/AD13 M38022M4-XXXSP

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL BLOCK DIAGRAM (Package : 64P4B) CNTR 1CNTR 0 VREF AV SS RAM ROM CPU A X Y S PC H PC L PS VSS RESET VCC 1 26 CNV SS P0(8) 49 50 5152 5354 55 56 P1(8) 41 43 45 4742 44 46 48 P2(8) 33 35 37 3936 38 40 P3(8) 57 59 61 6358 60 62 64 P4(8) 20 22 24 2821 23 25 29 P5(8) 12 14 16 1813 15 17 19 P6(8) 46 1059 113 342 XIN XOUT D-A (8) D-A (8) A-D (8) Reset input Clock generating circuit Clock input Clock output Prescaler 12 (8) Timer 1 (8) Timer 2 (8) I/O port P4 I/O port P0I/O port P1I/O port P2I/O port P3I/O port P5I/O port P6 7 8 SI/O1 (8) INT0 INT2 INT4 Prescaler X (8) Timer X (8) Prescaler Y (8) Timer Y (8) converter 2 converter 1 SI/O2 (8)PWM (8) INT3 converter

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PIN DESCRIPTION Pin VCC , VSS CNV SS VREF AVSS RESET XIN XOUT P00–P0 7 P10–P1 7 P20–P2 7 P30/DA1, P31/DA2 P32–P3 7 P40/INT4, P41/INT0, P42/INT1, P43/INT2 P44/RX D, P45/TXD, P46/SCLK1 , P47/SRDY1 P50/SIN2, P51/SOUT2 , P52/SCLK2 , P53/SRDY2 P54/CNTR 0, P55/CNTR 1 P56/PWM P57/INT3 P60/AN0– P67/AN7 Function

Apply voltage of 3.0 V–5.5 V to VCC , and 0 V to VSS . (Extended operating temperature version : 4.0 V to 5.5 V)
This pin controls the operation mode of the chip.
Normally connected to VSS .
If this pin is connected to VCC , the internal ROM is inhibited and external memory is accessed.
Reference voltage input pin for A-D and D-A converters
GND input pin for A-D and D-A converters
Connect to VSS .
Reset input pin for active “L”
Input and output signals for the clock generating circuit.
Connect a ceramic resonator or quartz-crystal oscillator between the X IN and XOUT pins to set the oscillation frequency.
If an external clock is used, connect the clock source to the XIN pin and leave the XOUT pin open.
The clock is used as the oscillating source of system clock.
8 bit CMOS I/O port
I/O direction register allows each pin to be individually programmed as either input or output.
At reset this port is set to input mode.
In modes other than single-chip, these pins are used as address, data, and control bus I/O pins.
CMOS compatible input level
CMOS 3-state output structure
8-bit CMOS I/O port with the same function as port P0
CMOS compatible input level
CMOS 3-state output structure
8-bit CMOS I/O port with the same function as port P0
CMOS compatible input level
CMOS 3-state output structure
8-bit CMOS I/O port with the same function as port P0
CMOS compatible input level
CMOS 3-state output structure Function except a port function
D–A conversion output pins
External interrupt input pin
Serial I/O1 I/O pins
Serial I/O2 I/O pins
Timer X and Timer Y I/O pins
PWM output pin
External interrupt input pin
A-D conversion input pins Name Power source CNV SS Analog reference voltage Analog power source Reset input Clock input Clock output I/O port P0 I/O port P1 I/O port P2 I/O port P3 I/O port P4 I/O port P5 I/O port P6

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER RAM size (bytes) 384 384 640 1024 Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) EPROM version EPROM version Package 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 64P6N-A 64S1B-E 64D0 Product M38022M2-XXXSP M38022M2-XXXFP M38022M4-XXXSP M38022M4-XXXFP M38024M6-XXXSP M38024M6-XXXFP M38027M8-XXXSP M38027E8-XXXSP M38027E8SP M38027M8-XXXFP M38027E8-XXXFP M38027E8FP M38027E8SS M38027E8FS (P) ROM size (bytes) ROM size for User in ( ) 8192 (8062) GROUP EXPANSION Mitsubishi plans to expand the 3802 group as follows: (1) Support for mask ROM, One Time PROM, and EPROM versions (2) Packages Memory Expansion Plan Currently supported products are listed below As of May 1996 16384 (16254) 24576 (24446) 32768 (32638) M38022M2 M38022M4 M38024M6 M38027M8/E8 Mass product Mass product Mass product Mass product ROM size (bytes) 32K 28K 24K 20K 16K 12K 192 256 384 512 640 768 896 1024 RAM size (bytes)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER GROUP EXPANSION (Extended operating temperature version) Mitsubishi plans to expand the 3802 group (extended operating temperature version) as follows: (1) Support for mask ROM One Time PROM, and EPROM ver- sions (2) Packages Memory Expansion Plan (Extended operating temperature version) Currently supported products are listed below. As of May 1996 RAM size (bytes) 384 384 1024 8192 (8062) 16384 (16254) 32768 (32638) Remarks Mask ROM version Mask ROM version Mask ROM version Mask ROM version Mask ROM version One Time PROM version One Time PROM version (blank) Mask ROM version One Time PROM version One Time PROM version (blank) Package 64P4B 64P6N-A 64P4B 64P6N-A 64P4B 64P6N-A Product M38022M2DXXXSP M38022M2DXXXFP M38022M4DXXXSP M38022M4DXXXFP M38027M8DXXXSP M38027E8DXXXSP M38027E8DSP M38027M8DXXXFP M38027E8DXXXFP M38027E8DFP (P) ROM size (bytes) M38022M2D M38022M4D M38027M8D/E8D Mass product Mass product Mass product ROM size (bytes) 32K 28K 24K 20K 16K 12K 192 256 384 512 640 768 896 1024 RAM size (bytes)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER PART NUMBERING M3802 2 M 4 - XXX SPProduct Package type ROM number ROM/PROM size : 4096 bytes : 8192 bytes : 12288 bytes : 16384 bytes : 20480 bytes : 24576 bytes : 28672 bytes : 32768 bytes The first 128 bytes and the last 2 bytes of ROM are reserved areas ; they cannot be used. Memory type : Mask ROM version : EPROM or One Time PROM version RAM size : 192 bytes : 256 bytes : 384 bytes : 512 bytes : 640 bytes : 768 bytes : 896 bytes : 1024 bytes Normally, using hyphen. When electrical characteristic, or division of quality identification code using alphanumeric character – : standard D : Extended operating temperature version SP : 64P4B package FP : 64P6N-A package SS : 64S1B-E package FS : 64D0 package Omitted in some types. M E

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER FUNCTIONAL DESCRIPTION Central Processing Unit (CPU) The 3802 group uses the standard 740 family instruction set. Re- fer to the table of 740 family addressing modes and machine in- structions or the SERIES 740 <Software> User’s Manual for de- tails on the instruction set. Machine-resident 740 family instructions are as follows: The FST and SLW instruction cannot be used. The STP, WIT, MUL, and DIV instruction can be used. CPU mode register The CPU mode register is allocated at address 003B16. The CPU mode register contains the stack page selection bit. Fig. 1 Structure of CPU mode register CPU mode register (CPUM : address 003B16) b7 b0 Stack page selection bit 0 : 0 page 1 : 1 page Not used (return “0” when read) Processor mode bits b1 b0 0 0 : Single-chip mode 0 1 : Memory expansion mode 1 0 : Microprocessor mode 1 1 : Not available

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Memory Special function register (SFR) area The Special Function Register area in the zero page contains con- trol registers such as I/O ports and timers. RAM RAM is used for data storage and for stack area of subroutine calls and interrupts. ROM The first 128 bytes and the last 2 bytes of ROM are reserved for device testing and the rest is user area for storing programs. Interrupt vector area The interrupt vector area contains reset and interrupt vectors. Zero page The 256 bytes from addresses 000016 to 00FF16 are called the zero page area. The internal RAM and the special function regis- ters (SFR) are allocated to this area. The zero page addressing mode can be used to specify memory and register addresses in the zero page area. Access to this area with only 2 bytes is possible in the zero page addressing mode. Special page The 256 bytes from addresses FF0016 to FFFF16 are called the special page area. The special page addressing mode can be used to specify memory addresses in the special page area. Ac- cess to this area with only 2 bytes is possible in the special page addressing mode. Fig. 2 Memory map diagram 010016 000016 004016 044016 FF0016 FFDC 16 FFFE 16 FFFF 16 192 256 384 512 640 768 896 1024 XXXX 00FF16 013F16 01BF 16 023F16 02BF 16 033F16 03BF 16 043F16 4096 8192 12288 16384 20480 24576 28672 32768 F000 E00016 D000 16 C000 16 B00016 A00016 900016 800016 F08016 E08016 D080 16 C080 16 B08016 A08016 908016 808016 YYYY 16 ZZZZ 16 RAM ROM Reserved area SFR area Not used Interrupt vector area ROM area Reserved ROM area (128 bytes) Zero page Special page RAM area RAM capacity (bytes) Address XXXX 16 ROM capacity (bytes) Address YYYY 16 Reserved ROM area Address ZZZZ 16

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 3 Memory map of special function register (SFR) 002016 002116 002216 002316 002416 002516 002616 002716 002816 002916 002A16 002B16 002C 16 002D 16 002E16 002F16 003016 003116 003216 003316 003416 003516 003616 003716 003816 003916 003A16 003B16 003C 16 003D 16 003E16 003F16 000016 000116 000216 000316 000416 000516 000616 000716 000816 000916 000A16 000B16 000C 16 000D 16 000E16 000F16 001016 001116 001216 001316 001416 001516 001616 001716 001816 001916 001A16 001B16 001C 16 001D 16 001E16 001F16 Serial I/O2 register (SIO2) Port P0 (P0) Port P0 direction register (P0D) Port P1 (P1) Port P1 direction register (P1D) Port P2 (P2) Port P2 direction register (P2D) Port P3 (P3) Port P3 direction register (P3D) Port P4 (P4) Port P4 direction register (P4D) Port P5 (P5) Port P5 direction register (P5D) Port P6 (P6) Port P6 direction register (P6D) Transmit/Receive buffer register (TB/RB) Serial I/O1 status register (SIO1STS) Serial I/O1 control register (SIO1CON) UART control register (UARTCON) Baud rate generator (BRG) Serial I/O2 control register (SIO2CON) Interrupt control register 2(ICON2) A-D conversion register (AD) Prescaler Y (PREY) Timer Y (TY) AD/DA control register (ADCON) D-A1 conversion register (DA1) D-A2 conversion register (DA2) Interrupt edge selection register (INTEDGE) CPU mode register (CPUM) Interrupt request register 1(IREQ1) Interrupt request register 2(IREQ2) Interrupt control register 1(ICON1) Prescaler 12 (PRE12) Timer 2 (T2) Prescaler X (PREX) Timer X (TX) Timer 1 (T1) Timer XY mode register (TM) PWM control register (PWMCON) PMW prescaler (PREPWM) PWM register (PWM)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Related SFRs CPU mode register CPU mode register CPU mode register AD/DA control register CPU mode register CPU mode register Interrupt edge selection register Serial I/O1 control register UART control register Serial I/O2 control register Timer XY mode register PWM control register Interrupt edge selection register Pin P00–P0 7 P10–P1 7 P20–P2 7 P30/DA1 P31/DA2 P32–P3 7 P40/INT4, P41/INT0, P43/INT2 P44/RX D, P45/TX D, P46/SCLK1 , P47/SRDY1 P50/SIN2, P51/SOUT2 , P52/SCLK2 , P53/SRDY2 P54/CNTR 0, P55/CNTR 1 P56/PWM P57/INT3 P60/AN0– P67/AN7 Name Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Input/Output Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits Input/output, individual bits I/O Format CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level CMOS 3-state output CMOS compatible input level Non-Port Function Address low-order byte output Address high-order byte output Data bus I/O D-A conversion output Control signal I/O External interrupt input Serial I/O1 function I/O Serial I/O2 function I/O Timer X and Timer Y function I/O PWM output External interrupt input A-D conversion input Ref.No. (1) (2) (1) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (3) (14) Note 1: For details of the functions of ports P0 to P3 in modes other than single-chip mode, and how to use double-function ports as func- tion I/O ports, refer to the applicable sections. 2: Make sure that the input level at each pin is either 0 V or VCC during execution of the STP instruction. When an input level is at an intermediate potential, a current will flow from VCC to VSS through the input-stage gate. I/O Ports Direction registers The 3802 group has 56 programmable I/O pins arranged in seven I/O ports (ports P0 to P6). The I/O ports have direction registers which determine the input/output direction of each individual pin. Each bit in a direction register corresponds to one pin, each pin can be set to be input port or output port. When “0” is written to the bit corresponding to a pin, that pin be- comes an input pin. When “1” is written to that bit, that pin be- comes an output pin. If data is read from a pin which is set to output, the value of the port output latch is read, not the value of the pin itself. Pins set to input are floating. If a pin set to input is written to, only the port output latch is written to and the pin remains floating.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 4 Port block diagram (single-chip mode) (1) (1) Ports P0, P1, P2, P32–P37 Direction register Data bus Port latch (2) Ports P30, P31 (3) Ports P40–P43, P57 Direction register Data bus Port latch Serial I/O1 input Serial I/O1 enable bit Receive enable bit (4) Port P44 (5) Port P45 (6) Port P46 Direction register Data bus Port latch Serial I/O1 ready output Serial I/O1 enable bit SRDY1 output enable bit Serial I/O1 mode selection bit (7) Port P47 (8) Port P50 Serial I/O2 input Direction register Data bus Port latch D–A conversion output DA 1 output enable bit (P30) DA 2 output enable bit (P31) Direction register Data bus Port latch Interrupt input Direction register Data bus Port latch Serial I/O1 output Serial I/O1 enable bit Transmit enable bit P45/TXD P-channel output disable bit Direction register Data bus Port latch Serial I/O1 clock output Serial I/O1 mode selection bit Serial I/O1 enable bit Serial I/O1 enable bit Serial I/O1 synchronous clock selection bit Serial I/O1 external clock input Direction register Data bus Port latch

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 5 Port block diagram (single-chip mode) (2) (14) Port P6(13) Port P56 (12) Ports P54, 55 (9) Port P51 (10) Port P52 (11) Port P53 Serial I/O2 transmit end signal Serial I/O2 port selection bit P51/SOUT2 P-channel output disable bit Direction register Data bus Port latch Serial I/O2 output Serial I/O2 external clock input Serial I/O2 synchronous clock selection bit Serial I/O2 port selection bit Direction register Data bus Port latch Serial I/O2 clock output Direction register Data bus Port latch Serial I/O2 ready output SRDY2 output enable bit Direction register Data bus Port latch Pulse output mode Timer output CNTR 0, CNTR1 Interrupt input Direction register Data bus Port latch PWM output PWM output enable bit A-D conversion input Direction register Data bus Port latch Analog input pin selection bit

Interrupt enable bits can be set or cleared by software. received according to priority. table into the program counter. (1) Disable the external interrupt which is selected. (2) Change the active edge selection. (3) Clear the interrupt request bit which is selected to “0”. (4) Enable the external interrupt which is selected. Table 1. Interrupt vector addresses and priority Note 1: Vector addresses contain interrupt jump destination addresses. 2: Reset function in the same way as an interrupt with the highest priority.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 6 Interrupt control Fig. 7 Structure of interrupt-related registers Interrupt disable flag (I) Interrupt request Interrupt request bit Interrupt enable bit BRK instruction Reset b7 b0 b7 b0 b7 b0 b7 b0 b7 b0 Interrupt edge selection register INT0 active edge selection bit INT1 active edge selection bit Not used (returns “0” when read) INT 2 active edge selection bit INT3 active edge selection bit INT4 active edge selection bit Not used (returns “0” when read) (INTEDGE : address 003A16) Interrupt request register 1 INT0 interrupt request bit INT1 interrupt request bit Serial I/O1 receive interrupt request bit Serial I/O1 transmit interrupt request bit Timer X interrupt request bit Timer Y interrupt request bit Timer 1 interrupt request bit Timer 2 interrupt request bit Interrupt control register 1 INT0 interrupt enable bit INT1 interrupt enable bit Serial I/O1 receive interrupt enable bit Serial I/O1 transmit interrupt enable bit Timer X interrupt enable bit Timer Y interrupt enable bit Timer 1 interrupt enable bit Timer 2 interrupt enable bit 0 : No interrupt request issued 1 : Interrupt request issued (IREQ1 : address 003C 16) (ICON1 : address 003E16) Interrupt request register 2 CNTR 0 interrupt request bit CNTR 1 interrupt request bit Serial I/O2 interrupt request bit INT2 interrupt request bit INT3 interrupt request bit INT4 interrupt request bit AD converter interrupt request bit Not used (returns “0” when read) (IREQ2 : address 003D 16) Interrupt control register 2 CNTR 0 interrupt enable bit CNTR 1 interrupt enable bit Serial I/O2 interrupt enable bit INT 2 interrupt enable bit INT3 interrupt enable bit INT4 interrupt enable bit AD converter interrupt enable bit Not used (returns “0” when read) (Do not write “1” to this bit) 0 : Interrupts disabled 1 : Interrupts enabled (ICON2 : address 003F 16) 0 : Falling edge active 1 : Rising edge active

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Timer X count stop bit 0: Count start 1: Count stop Timer XY mode register (TM : address 0023 16) Timer Y operating mode bit 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode CNTR 1 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode CNTR 0 active edge switch bit 0: Interrupt at falling edge Count at rising edge in event counter mode 1: Interrupt at rising edge Count at falling edge in event counter mode Timer X operating mode bit 0 0: Timer mode 0 1: Pulse output mode 1 0: Event counter mode 1 1: Pulse width measurement mode b1b0 b4b5 Timer Y count stop bit 0: Count start 1: Count stop Timers The 3802 group has four timers: timer X, timer Y, timer 1, and timer All timers are count down. When the timer reaches “00 16”, an un- derflow occurs at the next count pulse and the corresponding timer latch is reloaded into the timer and the count is continued. When a timer underflows, the interrupt request bit corresponding to that timer is set to “1”. The division ratio of each timer or prescaler is given by 1/(n + 1), where n is the value in the corresponding timer or prescaler latch. Timer 1 and Timer 2 The count source of prescaler 12 is the oscillation frequency di- vided by 16. The output of prescaler 12 is counted by timer 1 and timer 2, and a timer underflow sets the interrupt request bit. Timer X and Timer Y Timer X and Timer Y can each be selected in one of four operating modes by setting the timer XY mode register. Timer Mode The timer counts f(X IN)/16 in timer mode. Pulse Output Mode Timer X (or timer Y) counts f(XIN)/16. Whenever the contents of the timer reach “0016”, the signal output from the CNTR0 (or CNTR 1) pin is inverted. If the CNTR0 (or CNTR1) active edge switch bit is “0”, output begins at “ H”. If it is “1”, output starts at “L”. When using a timer in this mode, set the corresponding port P5 4 ( or port P55) direction register to out- put mode. Event Counter Mode Operation in event counter mode is the same as in timer mode, except the timer counts signals input through the CNTR 0 or CNTR 1 pin. Pulse Width Measurement Mode If the CNTR0 (or CNTR1) active edge selection bit is “0”, the timer counts at the oscillation frequency divided by 16 while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or CNTR1) active edge switch bit is “1”, the count continues during the time that the CNTR 0 (or CNTR1) pin is at “L”. In all of these modes, the count can be stopped by setting the timer X (timer Y) count stop bit to “1”. Every time a timer underflows, the corresponding interrupt request bit is set. Fig. 8 Structure of timer XY register

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 9 Block diagram of timer X, timer Y, timer 1, and timer 2 Timer X latch (8) Timer X (8) Prescaler X latch (8) Prescaler X (8) Oscillator Divider f(XIN) 1/16 CNTR 0 active edge switch bit P54/CNTR 0 pin Port P54 direction register “0” “1” Eventcounter mode Timer X count stop bit CNTR 0 active edge switch bit Port P54 latch Pulse output mode Pulse width measurement mode Timer mode Pulse output mode “1” “0” Timer X latch write pulse Pulse output mode To timer X interrupt request bit To CNTR 0 interrupt request bit Data bus Timer Y latch (8) Timer Y (8) Prescaler Y latch (8) Prescaler Y (8) CNTR 1 active edge switch bit P55/CNTR 1 pin Port P55 direction register “0” “1” Eventcounter mode Timer Y count stop bit CNTR 1 active edge switch bit Port P5 latch Pulse output mode Pulse width measurement mode Timer mode Pulse output mode “1” “0” Timer Y latch write pulse Pulse output mode To timer Y interrupt request bit To CNTR 1 interrupt request bit Data bus Q Q R Toggle flip- flop T Q Q R Toggle flip- flop T Timer 2 latch (8) Timer 1 latch (8)Prescaler 12 latch (8) Prescaler 12 (8) Timer 2 (8)Timer 1 (8) Data bus To timer 2 interrupt request bit To timer 1 interrupt request bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O1 Serial I/O1 can be used as either clock synchronous or asynchro- nous (UART) serial I/O. A dedicated timer is also provided for baud rate generation. Clock synchronous serial I/O mode Clock synchronous serial I/O1 mode can be selected by setting the mode selection bit of the serial I/O1 control register to “1”. For clock synchronous serial I/O1, the transmitter and the receiver must use the same clock. If an internal clock is used, transfer is started by a write signal to the TB/RB (address 0018 16). Fig. 10 Block diagram of clock synchronous serial I/O1 Fig. 11 Operation of clock synchronous serial I/O1 function 1/4XIN F/F P46/SCLK1 Serial I/O1 status register Serial I/O1 control register P47/SRDY1 P44/RXD P45/TXD f(XIN) Receive buffer Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Clock control circuitShift clock Serial I/O1 synchronous clock selection bit Frequency division ratio 1/(n+1) Baud rate generator Address 001C16 BRG count source selection bit Clock control circuitFalling-edge detector Transmit buffer Data bus Address 001816 Shift clock Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Transmit interrupt source selection bit Address 001916 Data bus Address 001A16 Transmit shift register D 7 D 7 D 0 D 1 D 2 D 3 D 4 D 5 D 6 D 0 D 1 D 2 D 3 D 4 D 5 D 6 RBF = 1 TSC = 1TBE = 0 TBE = 1 TSC = 0 Transfer shift clock (1/2 to 1/2048 of the internal clock, or an external clock) Serial output TxD Serial input RxD Write pulse to receive/transmit buffer (address 0018 16) Overrun error (OE) detection Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the transmit shift operation has ended (TSC=1), by setting the transmit interrupt source selection bit (TIC) of the serial I/O1 control register. 2 : If data is written to the transmit buffer when TSC=0, the transmit clock is generated continuously and serial data is output continuously from the TxD pin. 3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” . Receive enable signal SRDY1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Asynchronous serial I/O (UART) mode Clock asynchronous serial I/O mode (UART) can be selected by clearing the serial I/O mode selection bit of the serial I/O control register to “0”. Eight serial data transfer formats can be selected, and the transfer formats used by a transmitter and receiver must be identical. The transmit and receive shift registers each have a buffer, but the two buffers have the same address in memory. Since the shift reg- ister cannot be written to or read from directly, transmit data is written to the transmit buffer, and receive data is read from the re- ceive buffer. The transmit buffer can also hold the next data to be transmitted, and the receive buffer can hold a character while the next charac- ter is being received. Fig. 12 Block diagram of UART serial I/O f(XIN) OE PE FE Data bus Receive buffer Address 001816 Receive shift register Receive buffer full flag (RBF) Receive interrupt request (RI) Baud rate generator Frequency division ratio 1/(n+1) Address 001C16 ST/SP/PA generator Transmit buffer Data bus Transmit shift register Address 001816 Transmit shift completion flag (TSC) Transmit buffer empty flag (TBE) Transmit interrupt request (TI) Address 001916 STdetector SP detector UART control register Address 001B16 Character length selection bit Address 001A16 BRG count source selection bit Transmit interrupt source selection bit Serial I/O1 synchronous clock selection bit Clock control circuit Character length selection bit 7 bits 8 bits Serial I/O1 control register P46/SCLK1 Serial I/O1 status register P44/RXD P45/TXD

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 13 Operation of UART serial I/O function Serial I/O1 control register (SIO1CON) 001A16 The serial I/O control register consists of eight control bits for the serial I/O function. UART control register (UARTCON) 001B16 The UART control register consists of four control bits (bits 0 to 3) which are valid when asynchronous serial I/O is selected and set the data format of an data transfer. One bit in this register (bit 4) is always valid and sets the output structure of the P4 5/TX D pin. Serial I/O1 status register (SIO1STS) 001916 The read-only serial I/O1 status register consists of seven flags (bits 0 to 6) which indicate the operating status of the serial I/O function and various errors. Three of the flags (bits 4 to 6) are valid only in UART mode. The receive buffer full flag (bit 1) is cleared to “0” when the receive buffer is read. If there is an error, it is detected at the same time that data is transferred from the receive shift register to the receive buffer, and the receive buffer full flag is set. A write to the serial I/O status reg- ister clears all the error flags OE, PE, FE, and SE (bit 3 to bit 6, re- spectively). Writing “0” to the serial I/O enable bit SIOE (bit 7 of the Serial I/O Control Register) also clears all the status flags, in- cluding the error flags. All bits of the serial I/O1 status register are initialized to “0” at re- set, but if the transmit enable bit (bit 4) of the serial I/O control reg- ister has been set to “1”, the transmit shift completion flag (bit 2) and the transmit buffer empty flag (bit 0) become “1”. Transmit buffer/Receive buffer register (TB/ RB) 001816 The transmit buffer and the receive buffer are located at the same address. The transmit buffer is write-only and the receive buffer is read-only. If a character bit length is 7 bits, the MSB of data stored in the receive buffer is “0”. Baud rate generator (BRG) 001C16 The baud rate generator determines the baud rate for serial trans- fer. The baud rate generator divides the frequency of the count source by 1/(n + 1), where n is the value written to the baud rate genera- tor. TSC=0 TBE=1 RBF=0 TBE=0 TBE=0 RBF=1 RBF=1 STD 0 D 1 SP D 0 D 1ST SP TBE=1 TSC=1 STD 0 D 1 SP D 0 D 1ST SP Transmit or receive clock Transmit buffer write signal Generated at 2nd bit in 2-stop-bit mode 1 start bit 7 or 8 data bit 1 or 0 parity bit 1 or 2 stop bit (s) 1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception). 2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt source selection bit (TIC) of the serial I/O control register. 3: The receive interrupt (RI) is set when the RBF flag becomes "1". 4: After data is written to the transmit buffer when TSC=1, 0.5 to 1.5 cycles of the data shift cycle is necessary until changing to TSC=0. Notes Serial output TXD Serial input RXD Receive buffer read signal

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER b7b7 Transmit buffer empty flag (TBE) 0: Buffer full 1: Buffer empty Receive buffer full flag (RBF) 0: Buffer empty 1: Buffer full Transmit shift completion flag (TSC) 0: Transmit shift in progress 1: Transmit shift completed Overrun error flag (OE) 0: No error 1: Overrun error Parity error flag (PE) 0: No error 1: Parity error Framing error flag (FE) 0: No error 1: Framing error Summing error flag (SE) 0: (OE) U (PE) U (FE)=0 1: (OE) U (PE) U (FE)=1 Not used (returns "1" when read) Serial I/O1 status register (SIO1STS : address 0019 16) Serial I/O1 control register (SIO1CON : address 001A16) b0 b0 BRG count source selection bit (CSS) 0: f(XIN) 1: f(XIN)/4 Serial I/O1 synchronous clock selection bit (SCS) 0: BRG output divided by 4 when clock synchronous serial I/O is selected, BRG output divided by 16 when UART is selected. 1: External clock input when clock synchronous serial I/O is selected, external clock input divided by 16 when UART is selected. S RDY1 output enable bit (SRDY) 0: P47 pin operates as ordinaly I/O pin 1: P47 pin operates as SRDY1 output pin Transmit interrupt source selection bit (TIC) 0: Interrupt when transmit buffer has emptied 1: Interrupt when transmit shift operation is completed Transmit enable bit (TE) 0: Transmit disabled 1: Transmit enabled Receive enable bit (RE) 0: Receive disabled 1: Receive enabled Serial I/O1 mode selection bit (SIOM) 0: Asynchronous serial I/O (UART) 1: Clock synchronous serial I/O Serial I/O enable bit (SIOE) 0: Serial I/O disabled (pins P4 4 to P47 operate as ordinary I/O pins) 1: Serial I/O enabled (pins P4 4 to P47 operate as serial I/O pins) b7 UART control register (UARTCON : address 001B16) Character length selection bit (CHAS) 0: 8 bits 1: 7 bits Parity enable bit (PARE) 0: Parity checking disabled 1: Parity checking enabled Parity selection bit (PARS) 0: Even parity 1: Odd parity Stop bit length selection bit (STPS) 0: 1 stop bit 1: 2 stop bits 5/TXD P-channel output disable bit (POFF) 0: CMOS output (in output mode) 1: N-channel open drain output (in output mode) Not used (return "1" when read) Fig. 14 Structure of serial I/O control registers

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O2 The serial I/O2 function can be used only for clock synchronous serial I/O. For clock synchronous serial I/O the transmitter and the receiver must use the same clock. If the internal clock is used, transfer is started by a write signal to the serial I/O2 register. Serial I/O2 control register (SIO2CON) 001D16 The serial I/O2 control register contains seven bits which control various serial I/O functions. Fig. 15 Structure of serial I/O2 control register Fig. 16 Block diagram of serial I/O2 function XIN "1" "0" "0" "1" "0" "1" SRDY2 SCLK2 "0" "1" Data bus Serial I/O2 interrupt request Serial I/O2 port selection bit Serial I/O counter 2 (3) Serial I/O shift register 2 (8) Synchronization circuit Serial I/O2 port selection bit Serial I/O2 synchronous clock selection bit SRDY2 output enable bit External clock Internal synchronous clock selection bits Divider P53 latch P53/SRDY2 P52/SCLK2 P51/SOUT2 P50/SIN2 P52 latch P51 latch Serial I/O2 control register (SIO2CON : address 001D16) Internal synchronous clock selection bits 0 0 0: f(XIN)/8 0 0 1: f(XIN)/16 0 1 0: f(XIN)/32 0 1 1: f(XIN)/64 1 1 0: f(XIN)/128 1 1 1: f(XIN)/256 Serial I/O2 port selection bit (SM23) 0: I/O port 1: S OUT2 ,SCLK2 output pin SRDY2 output enable bit (SM24) 0: I/O port 1: SRDY2 output pin Transfer direction selection bit (SM25) 0: LSB first 1: MSB first Serial I/O2 synchronous clock selection bit (SM2 0: External clock 1: Internal clock 1/SOUT2 P-channel output disable bit 0: CMOS output (in output mode) 1: N-channel open-drain output (in output mode) b2 b1 b0

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 17 Timing of serial I/O2 function D 7D 0 D 1 D 2 D 3 D 4 D 5 D 6 Transfer clock (Note 1) Serial I/O2 output SOUT2 Serial I/O2 input SIN2 Receive enable signal SRDY2 Serial I/O2 register write signal (Note 2) Serial I/O2 interrupt request bit set 1: When the internal clock is selected as the transfer clock, the divide ratio can be selected by setting bits 0 to 2 of the serial I/O2 control register. 2: When the internal clock is selected as the transfer clock, the SOUT2 pin goes to high impedance after transfer completion. Notes

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Data bus Count source selection bit “0” “1” PWM prescaler pre-latch PWM register pre-latch PWM prescaler latch PWM register latch Transfer control circuit PWM register X IN Port P56 latch PWM enable bit Port P56 PWM prescaler PULSE WIDTH MODULATION (PWM) The 3802 group has a PWM function with an 8-bit resolution, based on a signal that is the clock input XIN or that clock input di- vided by 2. Data Setting The PWM output pin also functions as port P56. Set the PWM pe- riod by the PWM prescaler, and set the period during which the output pulse is an “H” by the PWM register. If the value in the PWM prescaler is n and the value in the PWM register is m (where n = 0 to 255 and m = 0 to 255) : PWM period = 255 5 (n+1)/f(X IN) = 51 5 (n+1) µs (when XIN = 5 MHz) Output pulse “H” period = PWM period 5 m/255 = 0.2 5 (n+1) 5 m µs (when XIN = 5 MHz) PWM Operation When bit 0 (PWM enable bit) of the PWM control register is set to “1”, operation starts by initializing the PWM output circuit, and pulses are output starting at an “H”. If the PWM register or PWM prescaler is updated during PWM output, the pulses will change in the cycle after the one in which the change was made. Fig. 18 Timing of PWM cycle Fig. 19 Block diagram of PWM function 51 5 m 5 (n+1) 255 ms PWM output m: Contents of PWM register n : Contents of PWM prescaler T : PWM cycle (when XIN = 5 MHz)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER AB C B T C T2= PWM output PWM register write signal PWM prescaler write signal (Changes from “A” to “B” during “H” period) (Changes from “T” to “T2” during PWM period) When the contents of the PWM register or PWM prescaler have changed, the PWM output will change from the next period after the change. T T T2 Fig. 20 Structure of PWM control register Fig. 21 PWM output timing when PWM register or PWM prescaler is changed PWM control register (PWMCON : address 002B16) PWM function enable bit Count source selection bit Not used (return “0” when read) b7 b0 0: PWM disabled 1: PWM enabled 0: f(XIN) 1: f(XIN)/2

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER A-D Converter The functional blocks of the A-D converter are described below. [A-D conversion register] The A-D conversion register is a read-only register that stores the result of an A-D conversion. When reading this register during an A-D conversion, the previous conversion result is read. [AD/DA control register] The AD/DA control register controls the A-D conversion process. Bits 0 to 2 select a specific analog input pin. Bit 3 signals the completion of an A-D conversion. The value of this bit remains at “0” during an A-D conversion, and changes to “1” when an A-D conversion ends. Writing “0” to this bit starts the A-D conversion. Bits 6 and 7 are used to control the output of the D-A converter. [Comparison voltage generator] The comparison voltage generator divides the voltage between AV SS and VREF into 256, and outputs the divided voltages. [Channel selector] The channel selector selects one of the ports P60/AN0 to P67/AN7, and inputs the voltage to the comparator. Fig.22 Structure of AD/DA control register Fig. 23 Block diagram of A-D converter [Comparator and Control circuit] The comparator and control circuit compares an analog input volt- age with the comparison voltage, then stores the result in the A-D conversion register. When an A-D conversion is complete, the control circuit sets the AD conversion completion bit and the AD interrupt request bit to “1”. Note that the comparator is constructed linked to a capacitor, so set f(X IN) to 500 kHz or more during an A-D conversion. AD/DA control register (ADCON : address 003416) Analog input pin selection bits 0 0 0: P60/AN0 0 0 1: P61/AN1 0 1 0: P62/AN2 0 1 1: P63/AN3 1 0 0: P64/AN4 1 0 1: P65/AN5 1 1 0: P66/AN6 1 1 1: P67/AN7 AD conversion completion bit 0: Conversion in progress 1: Conversion completed Not used (return "0" When read) DA 1 output enable bit 0: DA1 output disabled 1: DA1 output enabled DA 2 output enable bit 0: DA2 output disabled 1: DA2 output enabled b7 b0 b2 b1 b0 Channel selector A-D control circuit A-D conversion register Resistor ladder VREF AV SS Comparator A-D interrupt request b7 b0 P60/AN0 P61/AN1 P62/AN2 P63/AN3 P64/AN4 P65/AN5 P66/AN6 P67/AN7 Data bus (Address 003516) AD/DA control register (Address 003416)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER D-A Converter The 3802 group has two internal D-A converters (DA1 and DA2) with 8-bit resolutions. The D-A converter is performed by setting the value in the D-A conversion register. The result of D-A converter is output from the DA 1 or DA2 pin by setting the DA output enable bit to “1”. When using the D-A converter, the corresponding port direction register bit (P3 0/DA1 or P31/DA2) should be set to “0” (input sta- tus). The output analog voltage V is determined by the value n (base 10) in the D-A conversion register as follows: V = V REF 5 n/256 (n = 0 to 255) Where VREF is the reference voltage. At reset, the D-A conversion registers are cleared to “0016”, the DA output enable bits are cleared to “0”, and the P30/DA1 and P31/ DA 2 pins are set to input (high impedance). The D-A output is not buffered, so connect an external buffer when driving a low-impedance load. Set V CC to 3.0 V or more when using the D-A converter. Fig. 24 Block diagram of D-A converter Fig. 25 Equivalent connection circuit of D-A converter P30/DA1 D-A1 conversion register (8) R-2R resistor ladder DA 1 output enable bit P31/DA2 D-A2 conversion register (8) R-2R resistor ladder DA 2 output enable bit Data bus AV SS VREF "0" "1" MSB "0" "1" R R R R R R R 2R 2R LSB P30/DA1 D-A1 conversion register DA 1 output enable bit

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note. 5 : Undefined ] : The initial values of CM1 are determined by the level at the CNV SS pin. The contents of all other registers and RAM are undefined after a reset, so they must be initialized by software. Register contents (000116) · · · Prescaler X Port P0 direction register Port P1 direction register Port P2 direction register Port P3 direction register Port P4 direction register Port P5 direction register Port P6 direction register Serial I/O1 status register Serial I/O1 control register Timer X UART control register Serial I/O2 control register Prescaler 12 Timer 1 Timer XY mode register (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) (17) (18) (19) (20) (21) (22) (23) (24) (25) (26) (27) (28) (29) (30) (31) (0003 16) · · · (000516) · · · (000716) · · · (000916) · · · (000B16) · · · (000D16) · · · (001916) · · · (001A16) · · · (001B16) · · · (001D16) · · · (002016) · · · (002116) · · · (002216) · · · (002316) · · · (002416) · · · (002516) · · · (002616) · · · (002716) · · · (002B16) · · · (003416) · · · (003616) · · · (003716) · · · (003A16) · · · (003B16) · · · (003C16) · · · (003D16) · · · (003E16) · · · Address Timer 2 Prescaler Y Timer Y PWM control register AD/DA control register D-A1 conversion register D-A2 conversion register Interrupt edge selection register CPU mode register Interrupt request register 1 Interrupt request register 2 Interrupt control register 1 Interrupt control register 2 Processor status register Program counter 0016 0016 0016 0016 0016 0016 0016 FF16 FF16 FF16 FF16 0016 FF16 0116 0016 0016 0016 111000 0 0 0016 0016 0016 Contents of address FFFC16 55555 1 55(PS) (PCH ) (PCL) Contents of address FFFD16 0016 0016 0016 (003F16) · · · 100000 0 0 FF16 000010 0 0 0016 000000 0 ] Reset Circuit To reset the microcomputer, the RESET pin should be held at an “L” level for 2 µs or more. Then the RESET pin is returned to an “H” level (the power source voltage should be between 4.0 V and 5.5 V), reset is released. Internal operation begin until after 8 to 13 X IN clock cycles are completed. After the reset is completed, the pro- gram starts from the address contained in address FFFD 16 (high- order byte) and address FFFC16 (low-order byte). Make sure that the reset input voltage is less than 0.6 V for VCC of

3.0 V (Extended operating temperature version : the reset input

voltage is less than 0.8 V for V CC of 4.0 V). Fig. 27 Internal status of microcomputer after reset Fig. 26 Example of reset circuit 4.0V 0.8V VCC RESET Power source voltage Reset input voltage VSS M51953AL 3 0.1 m F 3802 group

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Fig. 28 Timing of reset RESET Data f Address SYNC XIN: 8 to 13 clock cycles XIN ? ? ?? ? FFFC FFFD AD H , ADL 1: f(XIN) and f(f) are in the relationship: f(XIN)=2 • f(f). 2: A question mark (?) indicates an undefined status that depends on the previous status. Reset address from the vector table Notes RESET OUT (internal reset)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Clock Generating Circuit An oscillation circuit can be formed by connecting a resonator be- tween XIN and XOUT . To supply a clock signal externally, input it to the XIN pin and make the XOUT pin open. Oscillation control Stop Mode If the STP instruction is executed, the internal clock φ stops at an “H”. Timer 1 is set to “01 16” and prescaler 12 is set to “FF16”. Oscillator restarts when an external interrupt is received, but the internal clock φ remains at an “H” until timer 1 underflow. This allows time for the clock circuit oscillation to stabilize. If oscillator is restarted by a reset, no wait time is generated, so keep the RESET pin at an “L” level until oscillation has stabilized. Wait Mode If the WIT instruction is executed, the internal clock φ stops at an “H” level, but the oscillator itself does not stop. The internal clock restarts if a reset occurs or when an interrupt is received. Since the oscillator does not stop, normal operation can be started immediately after the clock is restarted. To ensure that interrupts will be received to release the STP or WIT state, interrupt enable bits must be set to “1” before the STP or WIT instruction is executed. When the STP status is released, prescaler 12 and timer 1 will start counting and reset will not be released until timer 1 underflows, so set the timer 1 interrupt enable bit to “0” before the STP instruction is executed. Fig. 31 Block diagram of clock generating circuit Fig. 30 External clock input circuit Fig. 29 Ceramic resonator circuit C OUT XIN X OUT C IN X IN XOUT Open External oscillation circuit Vss Vcc X OUTXIN R SQ STP instruction WIT instruction R S Q R SQ Reset STP instruction Timer 1 ONW control Prescaler 121/2 f output Internal clock f Rd Rf ONW pin Single-chip mode Reset Interrupt request Interrupt disable flag (I) FF16 0116 Reset or STP instruction

ports P0 to P3 lose their I/O port functions and become bus pins. Outputs low-order byte of address. Outputs high-order byte of address. (including instruction codes). (except that the port latch cannot be read). Table 2. Functions of ports in memory expansion mode and The shaded areas are external memory areas. : YYYY 16 is the start address of internal ROM.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Bus control with memory expansion The 3802 group has a built-in ONW function to facilitate access to external memory and I/O devices in memory expansion mode or microprocessor mode. If an “L” level signal is input to the ONW pin when the CPU is in a read or write state, the corresponding read or write cycle is ex- tended by one cycle of φ. During this extended period, the RD or WR signal remains at “L”. This extension period is valid only for writing to and reading from addresses 0000 16 to 000716 and 044016 to FFFF16 in microprocessor mode, 044016 to YYYY16 in memory expansion mode, and only read and write cycles are ex- tended. Fig. 34 ONW function timing f Read cycle Write cycleDummy cycle Write cycle Read cycle Dummy cycle AD 15 to AD0 Period during which ONW input signal is received During this period, the ONW signal must be fixed at either “H” or “L”. At all other times, the input level of the ONW signal has no affect on operations. The bus cycles is not extended for an address in the area 0008 16 to 043F16, regardless of whether the ONW signal is received. ] : ]]] ONW WR RD

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER NOTES ON PROGRAMMING Processor Status Register The contents of the processor status register (PS) after a reset are undefined, except for the interrupt disable flag (I) which is “1”. Af- ter a reset, initialize flags which affect program execution. In particular, it is essential to initialize the index X mode (T) and the decimal mode (D) flags because of their effect on calculations. Interrupts The contents of the interrupt request bits do not change immedi- ately after they have been written. After writing to an interrupt re- quest register, execute at least one instruction before executing a BBC or BBS instruction. Decimal Calculations To calculate in decimal notation, set the decimal mode flag (D) to “1”, then execute an ADC or SBC instruction. Only the ADC and SBC instructions yield proper decimal results. After executing an ADC or SBC instruction, execute at least one instruction before executing a SEC, CLC, or CLD instruction. In decimal mode, the values of the negative (N), overflow (V), and zero (Z) flags are invalid. The carry flag can be used to indicate whether a carry or borrow has occurred. Initialize the carry flag before each calculation. Clear the carry flag before an ADC and set the flag before an SBC. Timers If a value n (between 0 and 255) is written to a timer latch, the fre- quency division ratio is 1/(n + 1). Multiplication and Division Instructions The index X mode (T) and the decimal mode (D) flags do not af- fect the MUL and DIV instruction. The execution of these instructions does not change the contents of the processor status register. Ports The contents of the port direction registers cannot be read. The following cannot be used:

The data transfer instruction (LDA, etc.)
The operation instruction when the index X mode flag (T) is “1”
The addressing mode which uses the value of a direction regis- ter as an index
The bit-test instruction (BBC or BBS, etc.) to a direction register
The read-modify-write instruction (ROR, CLB, or SEB, etc.) to a direction register Use instructions such as LDM and STA, etc., to set the port direc- tion registers. Serial I/O In clock synchronous serial I/O, if the receive side is using an ex- ternal clock and it is to output the S RDY1 signal, set the transmit enable bit, the receive enable bit, and the SRDY1 output enable bit to “1”. Serial I/O1 continues to output the final bit from the T X D pin after transmission is completed. The SOUT2 pin from serial I/O2 goes to high impedance after transmission is completed. A-D Converter The comparator uses internal capacitors whose charge will be lost if the clock frequency is too low. Make sure that f(X IN) is at least 500 kHz during an A-D conver- sion. (If the ONW pin has been set to “L”, the A-D conversion will take twice as long to match the longer bus cycle, and so f(X IN) must be at least 1 MHz.) Do not execute the STP or WIT instruction during an A-D conver- sion. D-A Converter The accuracy of the D-A converter becomes poor rapidly under the V CC = 3.0 V or less condition. Instruction Execution Time The instruction execution time is obtained by multiplying the fre- quency of the internal clock φ by the number of cycles needed to execute an instruction. The number of cycles required to execute an instruction is shown in the list of machine instructions. The frequency of the internal clock φ is half of the X IN frequency. When the ONW function is used in modes other than single-chip mode, the frequency of the internal clock φ may be one fourth the X IN frequency. Memory Expansion Mode The memory expansion mode is not available in the following mi- crocomputers.
M38024M6-XXXSP
M38024M6-XXXFP Memory Expansion Mode and Microproces- sor Mode Execute the LDM or STA instruction for writing to port P3 (address 000616) in memory expansion mode and microprocessor mode. Set areas which can be read out and write to port P3 (address 0006 16) in a memory, using the read-modify-write instruction (SEB, CLB).

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER DATA REQUIRED FOR MASK ORDERS The following are necessary when ordering a mask ROM produc- tion: 1. Mask ROM Order Confirmation Form 2. Mark Specification Form 3. Data to be written to ROM, in EPROM form (three identical copies) ROM PROGRAMMING METHOD The built-in PROM of the blank One Time PROM version and built- in EPROM version can be read or programmed with a general- purpose PROM programmer using a special programming adapter. Set the address of PROM programmer in the user ROM area. The PROM of the blank One Time PROM version is not tested or screened in the assembly process and following processes. To en- sure proper operation after programming, the procedure shown in Figure 35 is recommended to verify programming. Fig. 35 Programming and testing of One Time PROM version Package 64P4B, 64S1B 64P6N 64D0 Name of Programming Adapter PCA4738S-64A PCA4738F-64A PCA4738L-64A Programming with PROM programmer Screening (Caution) (150°C for 40 hours) Verification with PROM programmer Functional check in target device The screening temperature is far higher than the storage temperature. Never expose to 150 °C exceeding 100 hours. Caution :

0.2 VCC

0.16 VCC

–80 –80 –40 –40 –10

6 VCC –16

Power source voltage (f(XIN) < 2 MHz) (Note 1) Power source voltage (f(XIN) = 8 MHz) (Note 1) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN 0–AN 7 “H” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input voltage RESET, X IN, CNVSS “L” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “L” input voltage RESET, CNV SS “L” input voltage X IN “H” total peak output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 2) “H” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “L” total peak output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 2) “L” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “H” total average output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 2) “H” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “L” total average output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 2) “L” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 2) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 3) “L” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 3) “H” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 4) “L” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 4) Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) Internal clock oscillation frequency (VCC = 3.0 to 4.0 V) VCC VSS VREF AV SS VIA VIH VIH VIL VIL VIL Σ IOH(peak) Σ IOH(peak) Σ IOL(peak) Σ IOL(peak) Σ IOH(avg) Σ IOH(avg) Σ IOL(avg) Σ IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Symbol Parameter Limits Min. V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz Unit 3.0 4.0 2.0 3.0 AV SS

0.8 VCC

5.0 5.0 Typ. Max. X+1 6 Note: 300 mW in case of the flat package.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER stopped, output transistors isolated. Note 1:P4 5 is measured when the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 2:With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin. 2.0 1.0 5.0 5.0 –5.0 –5.0 5.5 2.0 “H” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7,P50–P57, P60–P6 7 Hysteresis CNTR 0, CNTR1, INT0–INT4 Hysteresis R X D, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input current RESET, CNVSS “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, RESET, CNVSS “L” input current RESET, CNVSS “L” input current XIN RAM hold voltage Symbol Parameter Limits Min. V Unit VCC –2.0 VCC –1.0 0.4 0.5 0.5 6.4 0.8 1.5 0.2 0.1 Typ. Max. IOH = –10 mA VCC = 4.0 to 5.5 V IOH = –1.0 mA VCC = 3.0 to 5.5 V IOL = 10 mA VCC = 4.0 to 5.5 V IOL = 1.0 mA VCC = 3.0 to 5.5 V VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz, VCC = 5 V f(XIN) = 5 MHz, VCC = 5 V f(XIN) = 2 MHz, VCC = 3 V Ta = 25 °C (Note 2) Ta = 85 °C (Note 2) 2.0 Test conditions VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIL IIL IIL VRAM VOH VOL ICC V V V V µ A µ A µ A µ A µ A µ A V mA µ A Power source current When WIT instruction is executed with f(Xin) = 8MHz,VCC =5V When WIT instruction is executed with f(Xin) = 5MHz,VCC =5V When WIT instruction is executed with f(Xin) = 2MHz,V CC =3V ±2.5 200 5.0 Limits Min. Bits LSB tC (φ) kΩ µ A µ A Typ. Max. 150 0.5 Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”. Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current t CONV R LADDER IVREF II(AD) Symbol Parameter Unit VREF = 5.0 V 50 ELECTRICAL CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Test conditions A–D CONVERTER CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC , Ta = –20 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur- rents flowing through the A-D resistance ladder. 1.0 2.5 3.2 Resolution Absolute accuracy VCC = 4.0 to 5.5 V VCC = 3.0 to 4.0 V Setting time Output resistor Reference power source input current (Note) tsu R O IVREF Symbol Parameter Limits Min. Bits µs kΩ mA Unit Typ. Max.Test conditions 2.5 D-A CONVERTER CHARACTERISTICS (VCC = 3.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 3.0 V to VCC , Ta = –20 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RXD–S CLK1 ) tsu(SIN2–S CLK2 ) th(SCLK1 –R X D) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit TIMING REQUIREMENTS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) 125 200 800 1000 370 400 370 400 220 200 100 200 Typ. Max. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RX D–S CLK1 ) tsu(SIN2–SCLK2 ) th(SCLK1 –R X D) th(SCLK2 –S IN2) Symbol Parameter Limits Min. µ s ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit TIMING REQUIREMENTS 2 (VCC = 3.0 to 5.5 V, VSS = 0 V , Ta = –20 to 85 °C, unless otherwise noted) 500/ (3 VCC –8) 200/ (3 VCC –8) 200/ (3 VCC –8) 500 230 230 230 230 2000 2000 950 950 950 950 400 400 200 300 Typ. Max. Note: When f(XIN) = 2 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 2 MHz and bit 6 of address 001A16 is “0”.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) 140 200 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit SWITCHING CHARACTERISTICS 1 (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 –30 Typ. Max. twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TXD) td(SCLK2 –SOUT2 ) tv(SCLK1 –TX D) tv(SCLK2 –S OUT2 ) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Test conditions Fig. 36 Note1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 3: XOUT pin is excluded. SWITCHING CHARACTERISTICS 2 (VCC = 3.0 to 5.5 V , VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) 350 400 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(SCLK1 )/2–50 tc(SCLK2 )/2–240 tc(SCLK1 )/2–50 tc(SCLK2 )/2–240 –30 Typ. Max. twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TXD) td(SCLK2 –SOUT2 ) tv(SCLK1 –TX D) tv(SCLK2 –S OUT2 ) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Test conditions Fig. 36 Note1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 3: XOUT pin is excluded.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note 1:The RESET OUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time tsu(ONW– φ) th(φ–ONW) tsu(DB–φ) th(φ–DB) tsu(ONW–RD) tsu(ONW–WR) th(RD–ONW) th(WR–ONW) tsu(DB–RD) th(RD–DB) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns Unit –20 –20 –20 –20 Typ. Max. φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD15–AD 8 delay time After φ AD15–AD 8 valid time After φ AD 7–AD 0 delay time After φ AD7–AD 0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (When one-wait is valid) After AD 15–AD 8 RD delay time After AD15–AD 8 WR delay time After AD7–AD 0 RD delay time After AD7–AD 0 WR delay time After RD AD15–AD 8 valid time After WR AD15–AD 8 valid time After RD AD7–AD 0 valid time After WR AD7–AD 0 valid time After WR data bus delay time After WR data bus valid time RESET OUT output delay time (Note 1) RESET OUT output valid time (Note 1) 200 200 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(XIN)–10 tc(XIN)–10 t c(XIN)–10 3tc(XIN)–10 tc(XIN)–35 tc(XIN)–40 c(XIN) tc(XIN)–15 tc(XIN)–20 Typ. Max. t c(φ) twH(φ) twL(φ) td(φ–AH) tv(φ–AH) td(φ–AL) tv(φ–AL) td(φ–SYNC) tv(φ–SYNC) td(φ–WR) tv(φ–WR) td(φ–DB) tv(φ–DB) twL(RD) twL(WR) td(AH–RD) td(AH–WR) td(AL–RD) td(AL–WR) tv(RD–AH) tv(WR–AH) tv(RD–AL) tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESET OUT ) tv(φ–RESET) Test conditions Fig. 36 TIMING REQUIREMENTS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) SWITCHING CHARATERISTICS 1 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time tsu(ONW– φ) th(φ–ONW) tsu(DB–φ) th(φ–DB) tsu(ONW–RD) tsu(ONW–WR) th(RD–ONW) th(WR–ONW) tsu(DB–RD) th(RD–DB) Symbol Parameter Limits Min. ns ns ns ns Unit –20 –20 180 –20 –20 185 Typ. Max. φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD15–AD 8 delay time After φ AD15–AD 8 valid time After φ AD 7–AD 0 delay time After φ AD7–AD 0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (when one-wait is valid) After AD 15–AD 8 RD delay time After AD15–AD 8 WR delay time After AD7–AD 0 RD delay time After AD7–AD 0 WR delay time After RD AD15–AD 8 valid time After WR AD15–AD 8 valid time After RD AD7–AD 0 valid time After WR AD7–AD 0 valid time After WR data bus delay time After WR data bus valid time RESET OUT output delay time (Note 1) RESET OUT output valid time (Note 1) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(XIN)–20 tc(XIN)–20 t c(XIN)–20 3tc(XIN)–20 tc(XIN)–145 tc(XIN)–145 c(XIN) Typ. Max. t c(φ) twH(φ) twL(φ) td(φ–AH) tv(φ–AH) td(φ–AL) tv(φ–AL) td(φ–SYNC) tv(φ–SYNC) td(φ–WR) tv(φ–WR) td(φ–DB) tv(φ–DB) twL(RD) twL(WR) td(AH–RD) td(AH–WR) td(AL–RD) td(AL–WR) tv(RD–AH) tv(WR–AH) tv(RD–AL) tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESET OUT ) tv(φ–RESET) Test conditions Fig. 36 Note1: The RESET OUT output goes “H” in sync with the fall of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. TIMING REQUIREMENTS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) SWITCHING CHARACTERISTICS 2 IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (VCC = 3.0 V, VSS = 0 V, Ta = –20 to 85 °C, unless otherwise noted) ns ns ns ns ns 150 150 200 195 300 300

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Input voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, VREF Input voltage RESET, XIN Input voltage CNVSS Output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, XOUT Power dissipation Operating temperature Storage temperature VCC VI VI VI VO Pd Topr Tstg Symbol Parameter Conditions Ratings –0.3 to 7.0 –0.3 to VCC +0.3 –0.3 to VCC +0.3 –0.3 to 13 –0.3 to VCC +0.3 1000 (Note) –40 to 85 –65 to 150 V V V V V mW Unit Ta = 25 °C All voltage are based on VSS . Output transistors are cut off. Note 1:The total output current is the sum of all the currents flowing through all the applicable ports. The total average current is an aver- age value measured over 100 ms. The total peak current is the peak value of all the currents. 2:The peak output current is the peak current flowing in each port. 3:The average output current IOL(avg), IOH(avg) in an average value measured over 100 ms. 5.5 VCC VCC VCC VCC VCC –80 –80 –40 –40 –10 Power source voltage (f(X IN) ≤ 2 MHz) Power source voltage Analog reference voltage (when A-D converter is used) Analog reference voltage (when D-A converter is used) Analog power source voltage Analog input voltage AN 0–AN 7 “H” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input voltage RESET, X IN, CNVSS “L” input voltage P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “L” input voltage RESET, CNV SS “L” input voltage X IN “H” total peak output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 1) “H” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “L” total peak output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 1) “L” total peak output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “H” total average output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 1) “H” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “L” total average output currentP00–P07, P10–P17, P20–P2 7, P30–P37 (Note 1) “L” total average output current P40–P4 7,P50–P5 7, P60–P6 7 (Note 1) “H” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 2) “L” peak output current P0 0–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 2) “H” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 3) “L” average output current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 3) Internal clock oscillation frequency (VCC = 4.0 to 5.5 V) VCC VSS VREF AV SS VIA VIH VIH VIL VIL VIL Σ IOH(peak) Σ IOH(peak) Σ IOL(peak) Σ IOL(peak) Σ IOH(avg) Σ IOH(avg) Σ IOL(avg) Σ IOL(avg) IOH(peak) IOL(peak) IOH(avg) IOL(avg) f(XIN) Symbol Parameter Limits Min. V V V V V V V V V V mA mA mA mA mA mA mA mA mA mA mA mA MHz Unit 4.0 2.0 4.0 AV SS 5.0 Typ. Max. ABSOLUTE MAXIMUM RATINGS (Extended operating temperature version) RECOMMENDED OPERATING CONDITIONS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, Ta = –40 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER stopped, output transistors isolated. Note 1:P4 5 is measured when the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. P51 is measured when the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 2:With output transistors isolated and A-D converter having completed conversion, and not including current flowing through VREF pin. 2.0 5.0 5.0 –5.0 5.5 “H” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 (Note 1) “L” output voltage P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7,P50–P5 7, P60–P6 7 Hysteresis CNTR 0, CNTR1, INT0–INT4 Hysteresis R XD, SCLK1 , SIN2, SCLK2 Hysteresis RESET “H” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7 “H” input currentRESET , CNVSS “H” input current XIN “L” input current P00–P0 7, P10–P1 7, P20–P2 7, P30–P3 7, P40–P4 7, P50–P5 7, P60–P6 7, RESET , CNVSS “L” input current XIN RAM hold voltage Symbol Parameter Limits Min. Unit VCC –2.0 0.4 0.5 0.5 6.4 1.5 0.1 Typ. Max. IOH = –10 mA IOL = 10 mA VI = VCC VI = VCC VI = VCC VI = VSS VI = VSS When clock stopped f(XIN) = 8 MHz f(XIN) = 5 MHz When WIT instruction is executed with f(XIN) = 8 MHz When WIT instruction is executed with f(XIN) = 5 MHz Ta = 25 °C (Note 2) Ta = 85 °C (Note 2) 2.0 Test conditions Note: When D-A conversion registers (addresses 003616 and 003716) contain “0016”. ±2.5 200 5.0 Resolution Absolute accuracy (excluding quantization error) Conversion time Ladder resistor Reference power source input current (Note) A-D port input current t CONV R LADDER IVREF II(AD) Symbol Parameter Limits Min. Bits LSB tC (φ) kΩ µ A µ A Unit Typ. Max. VREF = 5.0 V Test conditions ± 1 150 0.5 A-D CONVERTER CHARACTERISTICS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 2.0 V to VCC , Ta = –40 to 85 °C, unless otherwise noted) VT+ – VT– VT+ – VT– VT+ – VT– IIH IIH IIH IIL IIL VRAM VOH VOL V V V V V µA µA µA µA µA V Power source current mA ELECTRICAL CHARACTERISTICS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) ICC µA

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: Using one D-A converter, with the value in the D-A conversion register of the other D-A converter being “0016”, and excluding cur- rents flowing through the A-D resistance ladder. 1.0 3.2 Resolution Absolute accuracy Setting time Output resistor Reference power source input current (Note) t su R O IVREF Symbol Parameter Limits Min. Bits µs kΩ mA Unit Typ. Max.Test conditions 2.5 D-A CONVERTER CHARACTERISTICS (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = AVSS = 0 V, VREF = 4.0 V to VCC , Ta = –40 to 85 °C, unless otherwise noted)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note: When f(XIN) = 8 MHz and bit 6 of address 001A16 is “1”. Divide this value by four when f(XIN) = 8 MHz and bit 6 of address 001A16 is “0”. Reset input “L” pulse width External clock input cycle time External clock input “H” pulse width External clock input “L” pulse width CNTR 0, CNTR1 input cycle time CNTR 0, CNTR1 input “H” pulse width INT0 to INT4 input “H” pulse width CNTR 0, CNTR1 input “L” pulse width INT0 to INT4 input “L” pulse width Serial I/O1 clock input cycle time (Note) Serial I/O2 clock input cycle time Serial I/O1 clock input “H” pulse width (Note) Serial I/O2 clock input “H” pulse width Serial I/O1 clock input “L” pulse width (Note) Serial I/O2 clock input “L” pulse width Serial I/O1 input set up time Serial I/O2 input set up time Serial I/O1 input hold time Serial I/O2 input hold time tw(RESET) tc(XIN) twH(X IN) twL(XIN) tc(CNTR) twH(CNTR) twH(INT) twL(CNTR) twL(INT) tc(SCLK1 ) tc(SCLK2 ) twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) tsu(RXD–S CLK1 ) tsu(SIN2–S CLK2 ) th(SCLK1 –R XD) th(SCLK2 –SIN2) Symbol Parameter Limits Min. µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit 125 200 800 1000 370 400 370 400 220 200 100 200 Typ. Max. SWITCHING CHARACTERISTICS 1 (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) TIMING REQUIREMENTS 1 (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) Serial I/O1 clock output “H” pulse width Serial I/O2 clock output “H” pulse width Serial I/O1 clock output “L” pulse width Serial I/O2 clock output “L” pulse width Serial I/O1 output delay time (Note 1) Serial I/O2 output delay time (Note 2) Serial I/O1 output valid time (Note 1) Serial I/O2 output valid time (Note 2) Serial I/O1 clock output rising time Serial I/O1 clock output falling time Serial I/O2 clock output rising time Serial I/O2 clock output falling time CMOS output rising time (Note 3) CMOS output falling time (Note 3) 140 200 Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 tc(SCLK1 )/2–30 tc(SCLK2 )/2–160 –30 Typ. Max. twH(S CLK1 ) twH(S CLK2 ) twL(SCLK1 ) twL(SCLK2 ) td(SCLK1 –TX D) td(SCLK2 –S OUT2 ) tv(SCLK1 –TXD) tv(SCLK2 –S OUT2 ) tr(SCLK1 ) tf(SCLK1 ) tr(SCLK2 ) tf(SCLK2 ) tr(CMOS) tf(CMOS) Test conditions Fig. 36 Note1: When the P45/TX D P-channel output disable bit of the UART control register (bit 4 of address 001B16) is “0”. 2: When the P51/SOUT2 P-channel output disable bit of the serial I/O2 control register (bit 7 of address 001D16) is “0”. 3: XOUT pin excluded.

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER Note 1:The RESET OUT output goes “H” in sync with the rise of the φ clock that is anywhere between about 8 cycle and 13 cycles after the RESET input goes “H”. TIMING REQUIREMENTS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (Extended operating temperature version) (VCC = 4.0 to 5.5 V, VSS = 0 V , Ta = –40 to 85 °C, unless otherwise noted) Before φ ONW input set up time After φ ONW input hold time Before φ data bus set up time After φ data bus hold time Before RD ONW input set up time Before WR ONW input set up time After RD ONW input hold time After WR ONW input hold time Before RD data bus set up time After RD data bus hold time tsu(ONW– φ) th(φ–ONW) tsu(DB–φ) th(φ–DB) tsu(ONW–RD) tsu(ONW–WR) th(RD–ONW) th(WR–ONW) tsu(DB–RD) th(RD–DB) Symbol Parameter Limits Min. ns ns ns ns ns ns ns ns Unit –20 –20 –20 –20 Typ. Max. φ clock cycle time φ clock “H” pulse width φ clock “L” pulse width After φ AD15–AD 8 delay time After φ AD15–AD 8 valid time After φ AD7–AD 0 delay time After φ AD7–AD 0 valid time SYNC delay time SYNC valid time RD and WR delay time RD and WR valid time After φ data bus delay time After φ data bus valid time RD pulse width, WR pulse width RD pulse width, WR pulse width (when one wait is valid) Symbol Parameter Min. ns ns ns ns ns ns ns ns ns ns ns ns ns ns Unit tc(XIN)–10 tc(XIN)–10 25 tc(XIN) Typ. Max. t c(φ) twH(φ) twL(φ) td(φ–AH) tv(φ–AH) td(φ–AL) tv(φ–AL) td(φ–SYNC) tv(φ–SYNC) td(φ–WR) tv(φ–WR) td(φ–DB) tv(φ–DB) twL(RD) twL(WR) td(AH–RD) td(AH–WR) td(AL–RD) td(AL–WR) tv(RD–AH) tv(WR–AH) tv(RD–AL) tv(WR–AL) td(WR–DB) tv(WR–DB) td(RESET–RESET OUT ) tv(φ–RESET) Test conditions Fig. 36 SWITCHING CHARACTERISTICS IN MEMORY EXPANSION MODE AND MICROPROCESSOR MODE (Extended operating temperature version) Fig. 36 Circuit for measuring output switching characteristics (VCC = 4.0 to 5.5 V, VSS = 0 V, Ta = –40 to 85 °C, unless otherwise noted) After AD15–AD 8 RD delay time After AD15–AD 8 WR delay time After AD7–AD 0 RD delay time After AD7–AD 0 WR delay time After RD AD15–AD 8 valid time After WR AD15–AD 8 valid time After RD AD7–AD 0 valid time After WR AD7–AD 0 valid time After WR data bus delay time After WR data bus valid time RESET OUT output delay time RESET OUT output valid time (Note 1) tc(XIN)–10 3tc(XIN)–10 tc(XIN)–35 tc(XIN)–40 tc(XIN)–15 tc(XIN)–20 15 65 200 200 ns ns ns ns ns ns ns ns ns Measurement output pin 100pF CMOS output Limits

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (1) Timing Diagram tWL(INT) tWH(INT) tWL(X IN) tWH(X IN) tC(XIN) XIN tW(RESET) RESET tf tr tWL(CNTR) tWH(CNTR) tC(CNTR) td(SCLK1 -TXD),td(SCLK2-SOUT2 ) tv(SCLK1 -TXD), tv(SCLK2-SOUT2 ) tC(SCLK1 ), tC(SCLK2 ) tWL(S CLK1 ), tWL(S CLK2 ) tWH(S CLK1 ), tWH(S CLK2 ) th(SCLK1-R XD), th(SCLK2-SIN2) tsu(RXD -SCLK1 ), tsu(SIN2-SCLK2 ) TXD SOUT2 R XD SIN2 SCLK1 SCLK2 INT0–INT4 CNTR 0, CNTR1

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (2)Timing Diagram in Memory Expansion Mode and Microprocessor Mode (a) (3)Timing Diagram in Microprocessor Mode tWL( f)tWH( f) tC(f) f td(f-AH) td(f-AL) td(f-SYNC) tv(f-AH) tv(f-AL) tv(f-SYNC) td(f-WR) tv(f-WR) tSU(ONW- f) th(f-ONW) tSU(DB- f) th(f-DB) td(f-DB) tv(f-DB) td(RESET- RESET OUT ) AD 15–AD 8 AD 7–AD 0 SYNC RD,WR ONW DB 0–DB 7 DB 0–DB 7 RESET f RESET OUT tv(f- RESETOUT )

0.5 VCC

(At CPU reading) (At CPU writing)

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER (4) Timing Diagram in Memory Expansion Mode and Microprocessor Mode (b)

0.5 VCCRD,WR

0.5 VCCAD 15–AD 8

td(AH-WR) tv(WR-AH)

0.5 VCCAD 7–AD 0

td(AL-WR) tv(WR-AL)

0.2 VCCDB 0–DB 7

0.5 VCCRD

tSU(DB-RD) th(RD-DB)

0.5 VCCDB 0–DB 7

0.5 VCCWR

td(WR-DB) tv(WR-DB) th(WR-ONW) ONW tsu(ONW-WR) tv(RD-AH)td(AH-RD) td(AL-RD) tv(RD-AL) th(RD-ONW)tsu(ONW-RD) tWL(RD) tWL(WR) (At CPU reading) (At CPU writing) tWL(RD) tWL(WR)

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SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Rev. Rev. No. date

1.0 First Edition 971226

REVISION DESCRIPTION LIST 3802 GROUP DATA SHEET (1/1) Revision Description

Product Information

3802 specifications and overview.

Summary

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Description

SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

Source title 3802 Datasheet(PDF) - Mitsubishi Electric Semiconductor

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