33C408 MAXWELL | Alldatasheet
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All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com
4 Megabit (512K x 8-Bit)
©2002 Maxwell Technologies All rights reserved. CMOS SRAM
04.16.02 REV 8
FEATURES:
- R AD -PAK ® Technology radiation-hardened against natural space radiation 524,288 x 8 bit organization
- Total dose hardness: - > 100 krad (Si), depending upon space mis- sion Excellent Single Event Effect
- - SELTH : > 68 MeV/mg/cm2
- - SEUTH : = 3 MeV/mg/cm2 - SEU saturated cross section: 6E-9 cm2/bit Package: - 32-Pin RAD -PAK ® flat pack - 32-Pin Non-RAD -PAK ® flat pack Fast access time: - 20, 25, 30 ns maximum times available Single 5V + 10% power supply Fully static operation - No clock or refresh required Three state outputs TTL compatible inputs and outputs Low power: - Standby: 60 mA (TTL); 10 mA (CMOS) - Operation: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30 ns) D ESCRIPTION : Maxwell Technologies’ 33C408 high-density 4 Megabit SRAM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. Using Maxwell’s radiation-hard- ened R AD -PAK ® packaging technology, the 33C408 realizes a high density, high performance, and low power consumption. Its fully static design elimi- nates the need for external clocks, while the CMOS circuitry reduces power consumption and provides higher reliability. The 33C408 is equipped with eight common input/output lines, chip select and output enable, allowing for greater system flex- ibility and eliminating bus contention. The 33C408 features the same advanced 512K x 8-bit SRAM, high-speed, and low-power demand as the com- mercial counterpart. Maxwell Technologies' patented R AD -PAK packag- ing technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while providing the required radiation shielding for a lifetime in orbit or space mission. In a GEO orbit, R AD -PAK provides greater than 100 krad (Si) radiation dose tolerance. This product is available with screening up to Class S. Logic Diagram
4 Megabit (512K x 8-Bit) CMOS SRAM 33C408
TABLE 1. PINOUT DESCRIPTION
29 WE Write Enable
22 CS Chip Select
24 OE Output Enable
16 V SS Ground
TABLE 2. 33C408 ABSOLUTE MAXIMUM RATINGS TABLE 3. DELTA LIMITS
TABLE 4. 33C408 RECOMMENDED OPERATING CONDITIONS
- V IH (max) = VCC +2.0V ac (pulse width < 10 ns) for I < 20 mA
- VIL (min) = -2.0V ac(pulse width < 10 ns) for I < 20 mA
TABLE 5. 33C408 DC ELECTRICAL CHARACTERISTICS TABLE 6. 33C408 AC TEST CONDITIONS AND CHARACTERISTICS
TABLE 7. 33C408 AC CHARACTERISTICS FOR READ CYCLE TABLE 6. 33C408 AC TEST CONDITIONS AND CHARACTERISTICS
TABLE 8. 33C408 FUNCTIONAL DESCRIPTION TABLE 9. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE TABLE 7. 33C408 AC CHARACTERISTICS FOR READ CYCLE
TABLE 9. 33C408 AC CHARACTERISTICS FOR WRITE CYCLE
FIGURE 1. AC TEST LOAD TIMING WAVEFORM OF READ CYCLE (1) FIGURE 2. TIMING WAVEFORM OF READ CYCLE (2) 1.W E is high for read cycle.
- All read cycle timing is referenced form the last valid address to the first transition address.
referenced to VOH or VOL levels.
- At any given temperature and voltage condition, tHZ(max) is less than tLZ(min) both for a given device and
- Transition is measured + 200mV from steady state voltage. This parameter is sampled and not 100%
- Device is continuously selected with CS = VIL.
- Address valid prior to coincident with CS transition low.
- For common I/O applications, minimization or elimination of bus contention condition is necessary dur-
FIGURE 3. TIMING WAVEFORM OF WRITE CYCLE (1) FIGURE 4. TIMING WAVEFORM OF WRITE CYCLE (2) FIGURE 5. TIMING WAVEFORM OF WRITE CYCLE (3)
9All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. W RITE CYCLE NOTE : 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and WE going low: A write ends at the earliest transition among CS going high and WE going high. tWP is measured from beginning of write to the end of write. 3.t CW is measured from the later of CS going low to end of write. 4.t AS is measured from the address valid to the beginning of write. 5.t WR is measured form the end of write to the address change. TWR applied in case a write ends as CS, or WR going high. 6. If OE , CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8.I C CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state. 9.D OUT is the read data of the new address. 10. When CS is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied.
10All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Note: All dimensions in inchesImportant Notice:
32 PIN RAD-PAK® FLAT PACKAGE
A 0.120 0.135 0.155 b 0.013 0.015 0.020 c 0.008 0.010 0.012 D -- 0.930 0.940 E 0.635 0.645 0.655 E1 -- -- 0.690 E2 0.550 0.565 -- E3 0.030 0.040 -- e 0.050 BSC L 0.390 0.400 0.410 Q 0.026 0.098 -- S1 0.005 0.082 -- N3 2
11All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample test- ing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Technologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.
12All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Feature Option Details33C408 XX F X -XX Access Time Screening Flow Package Radiation Feature Base Product Nomenclature 20 = 20 ns 25 = 25 ns 30 = 30 ns Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25° I = Industrial (testing @ -55°C, +25°C, +125°C) F = Flat Pack RP = R AD-PAK® package RT = Non-RAD-PAK® package