32C408B MAXWELL | Alldatasheet

Document overview

  • Manufacturer or author: Provided By ALLDATASHEET.COM(FREE DATASHEET DOWNLOAD SITE)
  • PDF pages: 11

Technical content

All data sheets are subject to change without notice (858) 503-3300 - Fax: (858) 503-3301 - www.maxwell.com

4 Megabit (512K x 8-Bit) SRAM

©2002 Maxwell Technologies All rights reserved.

05.02.02 Rev 7

FEATURES:

  • 512k x 8-bit CMOS architecture R AD-PAK® technology hardened against natural space radi- ation  Total dose hardness: - > 100 krad (Si), depending upon space mission  Single event effect: - SELTH: > 68 MeV/mg/cm2 - SEUTH: < 3MeV/mg/cm2 - SEU saturated cross section: 6E-9 cm2/bit  Package: -36 pin RAD-PAK® flat pack  Fast propagation time: -20, 25, 30 ns maximum access time  Single 5V + 10% power supply  Low power dissipation: - Standby: 60mA (TTL); 10mA (CMOS) - Operating: 180 mA (20 ns); 170 mA (25 ns); 160 mA (30 ns)  TTL compatible inputs and outputs  Fully static operation - No clock or refresh required  Three state outputs DESCRIPTION: Maxwell Technologies’ 32C408B high-speed 4 Megabit SRAM microcircuit features a greater than 100 krad (Si) total dose tolerance, depending upon space mission. Using R AD-PAK® packaging technology, the 32C408B realizes higher density, higher performance and lower power consumption, and is well suited for high-speed system application. Its fully static design eliminates the need for external clocks, while the CMOS cir- cuitry reduces power consum ption and provides higher reli- ability. The 32C408B is equipped with eight common input/ output lines, chip select and output enable, allowing for greater system flexibility and eliminating bus contention. Maxwell Technologies' patented R AD-PAK packaging technol- ogy incorporates radiation shielding in the microcircuit pack- age. In a GEO orbit, R AD-PAK can provides true greater than 100 krad (Si) total radiation dose tolerance; dependent upon space mission. The patented radiation-hardened R AD-PAK technology incorporates radiation shielding in the microcircuit package. It eliminates the need for box shielding while provid- ing the required radiation shielding for a lifetime in orbit or a space mission. This product is available with packaging and screening up to Class S. NC A18 CS I/O1 I/O2 Vcc Vss I/O3 I/O4 WE A17 A16 A15 OE I/O8 I/O7 Vss Vcc A14 A13 A12 A11 NC A10 I/O5 I/O6 1 36 18 19 ROW DECODER INPUT DATA CONTROL MEMORY MATRIX

1024 ROWS x 4096 COLUMNS

4 Megabit (512K x 8-Bit) SRAM 32C408B

TABLE 1. 32C408B ABSOLUTE MAXIMUM RATINGS TABLE 2. 32C408B RECOMMENDED OPERATING CONDITIONS

  1. V IH(max) = VCC + 2.0V ac(pulse width < 10ns) for I < 20mA.
  2. V IL (min) = -2.0V ac(pulse width < 10ns) for I < 20mA.

TABLE 3. 32C408B DC ELECTRICAL CHARACTERISTICS

TABLE 4. 32C408B AC CHARACTERISTICS FOR READ CYCLE

TABLE 5. 32408B FUNCTIONAL DESCRIPTION 1 TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE

FIGURE 1. TIMING WAVEFORM OF WRITE CYCLE(1) (OE CLOCK) TABLE 6. 32C408B AC CHARACTERISTICS FOR WRITE CYCLE

FIGURE 2. TIMING WAVEFORM OF WRITE CYCLE (OE LOW FIXED)

  1. All write cycle timing is referenced from the la st valid address to the first transition address.
  2. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going low and
  3. t CW is measured from the later of CS going low to end of write.
  4. t AS is measured from the address valid to the beginning of write.
  5. t WR is measured from the end of write to the address change. TWR applied in case a write ends as CS or WE going high.
  6. If OE , CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase

of the output must not be applied because bus contention can occur.

  1. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write
  2. IC CS goes low simultaneously with WE going low or after WE going low, the outputs remain high impedance state.
  3. D OUT is the read data of the new address.

FIGURE 3. TIMING WAVEFORM OF READ CYCLE(1) (ADDRESS CONTROLLED, CS = OE = VIL, WE = VIH)

FIGURE 4. TIMING WAVEFORM OF READ CYCLE(2) (WE = VIH)

  1. WE is high for read cycle.
  2. All read cycle timing is referenced from the la st valid address to the first transition address.
  3. t HZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
  4. At any given temperature and voltage condition, t HZ(max) is less than tLZ(min) both for a given device and from device to device.
  5. Transition is measured +200mV from steady state voltage wi th Load(B). This parameter is sampled and not 100% tested.
  6. Device is continuously selected with CS = VIL.
  7. Address valid prior to coincident with CS transition low.
  8. For common I/O applications, minimization or elimination of bus contention is necessary during read and

FIGURE 5. SRAM HEAVY ION CROSS SECTION

FIGURE 6. SRAM PROTON SEU CROSS SECTION STATIC

9All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Note: All dimensions in inches

36 PIN FLAT RAD-PAK® PACKAGE

A 0.122 0.135 0.148 b 0.015 0.017 0.019 c 0.008 0.010 0.012 D -- 0.930 0.940 E 0.638 0.645 0.652 E1 -- -- 0.690 E2 0.560 0.565 -- E3 0.005 0.040 -- e 0.050 BSC L 0.390 0.400 0.410 Q 0.088 0.098 0.108 S1 0.005 0.032 -- N3 6

10All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Important Notice: These data sheets are created using the chip manufacturers published specifications. Maxwell Technologies verifies functionality by testing key parameters either by 100% testing, sample testing or characterization. The specifications presented within these data sheets represent the latest and most accurate information available to date. However, these specifications are subject to change without notice and Maxwell Technologies assumes no responsibility for the use of this information. Maxwell Technologies’ products are not authorized for use as critical components in life support devices or systems without express written approval from Maxwell Technologies. Any claim against Maxwell Technologies must be made within 90 days from the date of shipment from Maxwell Tech- nologies. Maxwell Technologies’ liability shall be limited to replacement of defective parts.

11All data sheets are subject to change without notice ©2002 Maxwell Technologies All rights reserved. Feature Option Details32C408B XX F X -XX Access Time Screening Flow Package Radiation Feature Base Product Nomenclature 20 = 20 ns 25 = 25 ns 30 = 30 ns Monolithic S = Maxwell Class S B = Maxwell Class B E = Engineering (testing @ +25° I = Industrial (testing @ -55°C, +25°C, +125°C) F = Flat Pack RP = R AD-PAK® package CMOS 512kword x 8-bit Static RAM