27C040

AT27C040 ATMEL | Alldatasheet

Document overview

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Technical content

Features

 Fast Read Access Time – 70 ns  Low Power CMOS Operation –1 0 0 µA Max Standby – 30 mA Max Active at 5 MHz  JEDEC Standard Packages – 32-lead, 600-mil PDIP – 32-lead PLCC – 32-lead TSOP  5V ± 10% Supply  High Reliability CMOS Technology – 2000V ESD Protection – 200 mA Latchup Immunity  Rapid™ Programming Algorithm – 100 µs/Byte (Typical)  CMOS and TTL Compatible Inputs and Outputs  Integrated Product Identification Code  Commercial and Industrial Temperature Ranges

Description

The AT27C040 chip is a low-power, high-performance, 4,194,304-bit one-time pro- grammable read-only memory (OTP EPROM) organized as 512K by 8 bits. The AT27C040 requires only one 5V power supply in normal read mode operation. Any byte can be accessed in less than 70 ns, eliminating the need for speed reducing WAIT states on high-performance microprocessor systems. 4-Megabit (512K x 8) OTP EPROM AT27C040 PDIP Top View Pin Configurations Pin Name Function A0 - A18 Addresses O0 - O7 Outputs CE Chip Enable OE Output Enable VPP A16 A15 A12 GND VCC A18 A17 A14 A13 A11 OE A10 CE TSOP Top View PLCC Top View A11 A13 A14 A17 A18 VCC VPP A16 A15 A12 OE A10 CE GND A14 A13 A11 OE A10 CE GND A12 A15 A16 VPP VCC A18 A17

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0189F–EPROM–4/03 Atmel’s scaled CMOS technology provides low active power consumption, and fast program- ming. Power consumption is typically 8 mA in active mode and less than 10µA in standby mode. The AT27C040 is available in a choice of industry standard JEDEC-approved one-time pro- grammable (OTP) plastic PDIP, PLCC and TSOP packages. The device features two-line control (CE , OE) to eliminate bus contention in high-speed systems. Atmel’s AT27C040 has additional features to ensure high quality and efficient production use. The Rapid Programming Algorithm reduces the time required to program the part and guaran- tees reliable programming. Programming time is typically only 100 µs/byte. The Integrated Product Identification Code electronically identifies the device and manufacturer. This feature is used by industry standard programming equipment to select the proper programming algo- rithms and voltages. Switching Considerations Switching between active and standby conditions via the Chip Enable pin may produce tran- sient voltage excursions. Unless accommodated by the system design, these transients may exceed datasheet limits, resulting in device non-conformance. At a minimum, a 0.1 µF high frequency, low inherent inductance, ceramic capacitor should be utilized for each device. This capacitor should be connected between the V CC and Ground terminals of the device, as close to the device as possible. Additionally, to stabilize the supply voltage level on printed circuit boards with large EPROM arrays, a 4.7 µF bulk electrolytic capacitor should be utilized, again connected between the VCC and Ground terminals. This capacitor should be positioned as close as possible to the point where the power supply is connected to the array. Block Diagram

0189F–EPROM–4/03 Notes: 1. X can be VIL or VIH. 2. Refer to Programming Characteristics 4. Two identifier bytes may be selected. All Ai inputs are held low (VIL), except A9 which is set to VH and A0 which is toggled low (VIL) to select the Manufacturer’s Identification byte and high (VIH) to select the Device Code byte. Operating Modes Mode/Pin CE OE Ai V PP Outputs Read V IL VIL Ai X (1) D OUT Output Disable X V IH XX H i g h Z Standby V IH XXX H i g h Z Rapid Program(2) VIL VIH Ai V PP D IN PGM Verify X V IL Ai V PP D OUT PGM Inhibit V IH VIH XV PP High Z Product Identification(4) VIL VIL A9 = VH (3) A0 = VIH or VIL A1 - A18 = VIL X Identification Code Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin with Voltage on A9 with V PP Supply Voltage with

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0189F–EPROM–4/03 Notes: 1. VCC must be applied simultaneously or before VPP, and removed simultaneously or after VPP. 2. VPP may be connected directly to VCC , except during programming. The supply current would then be the sum of ICC and IPP. Note: 1. 2, 3, 4, 5 – see AC Waveforms for Read Operation DC and AC Operating Conditions for Read Operation AT27C040-70 AT27C040-90 AT27C040-12 AT27C040-15 Operating Temperature (Case) VCC Power Supply 5V ± 10% 5V ± 10% 5V ± 10% 5V ± 10% DC and Operating Characteristics for Read Operation Symbol Parameter Condition Min Max Units ILI Input Load Current V IN = 0V to VCC ±1 µA ILO Output Leakage Current V OUT = 0V to VCC ±5 µA IPP1 (2) VPP (1) Read/Standby Current VPP = VCC 10 µA ISB VCC1 (1) Standby Current I SB1 (CMOS), CE = VCC ± 0.3V 100 µA ISB2 (TTL), CE = 2.0 to VCC + 0.5V 1 mA ICC VCC Active Current f = 5 MHz, I OUT = 0 mA, CE = VIL 30 mA VIL Input Low Voltage -0.6 0.8 V VIH Input High Voltage 2.0 V CC + 0.5 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -400 µA2 . 4 V AC Characteristics for Read Operation Symbol Parameter Condition AT27C040 Units -70 -90 -12 -15 Min Max Min Max Min Max Min Max tACC (3) Address to Output Delay CE = OE = VIL 70 90 120 150 ns tCE (2) CE to Output Delay OE = VIL 70 90 120 150 ns tOE (2)(3) OE to Output Delay CE = VIL 30 35 35 40 ns tDF (4)(5) OE or CE High to Output Float, whichever occurred first 20 20 30 30 ns tOH Output Hold from Address, CE or OE, whichever occurred first 0000 n s

0189F–EPROM–4/03 AC Waveforms for Read Operation(1) 2. OE may be delayed up to tCE - tOE after the falling edge of CE without impact on tCE . 3. OE may be delayed up to tACC - tOE after the address is valid without impact on tACC . 4. This parameter is only sampled and is not 100% tested. 5. Output float is defined as the point when data is no longer driven. Input Test Waveforms and Measurement Levels Output Test Load Note: 1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested. OUTPUT PIN 1.3V (1N914) 3.3K CL Pin Capacitance f = 1 MHz, T = 25°C (1) Symbol Typ Max Units Conditions C IN 48 p F V IN = 0V C OUT 81 2 p F V OUT = 0V

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0189F–EPROM–4/03 Programming Waveforms (1) Notes: 1. The Input Timing Reference is 0.8V for VIL and 2.0V for VIH. 2. tOE and tDFP are characteristics of the device but must be accommodated by the programmer. 3. When programming the AT27C040 a 0.1 µF capacitor is required across VPP and ground to suppress spurious voltage transients. DC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Symbol Parameter Test Conditions Limits UnitsMin Max ILI Input Load Current V IN = VIL, VIH ±10 µA VIL Input Low Level -0.6 0.8 V VIH Input High Level 2.0 V CC + 0.7 V VOL Output Low Voltage I OL = 2.1 mA 0.4 V VOH Output High Voltage I OH = -400 µA 2.4 V ICC2 VCC Supply Current (Program and Verify) 40 mA IPP2 VPP Supply Current CE = VIL 20 mA VID A9 Product Identification Voltage 11.5 12.5 V

0189F–EPROM–4/03 Notes: 1. VCC must be applied simultaneously or before VPP and removed simultaneously or after VPP. 2. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no longer driven – see timing diagram. 3. Program Pulse width tolerance is 100 µsec ± 5%. AC Programming Characteristics TA = 25 ± 5°C, VCC = 6.5 ± 0.25V, VPP = 13.0 ± 0.25V Symbol Parameter Test Conditions (1) Limits UnitsMin Max tAS Address Setup Time Input Rise and Fall Times: (10% to 90%) 20 ns Input Pulse Levels: 0.45V to 2.4V Input Timing Reference Level: 0.8V to 2.0V Output Timing Reference Level: 0.8V to 2.0V 2 µs tOES OE Setup Time 2 µs tDS Data Setup Time 2 µs tAH Address Hold Time 0 µs tDH Data Hold Time 2 µs tDFP OE High to Output Float Delay(2) 0 130 ns tVPS VPP Setup Time 2 µs tVCS VCC Setup Time 2 µs tPW CE Program Pulse Width(3) 95 105 µs tOE Data Valid from OE(2) 150 ns tPRT VPP Pulse Rise Time During Programming 50 ns Atmel’s AT27C040 Integrated Product Identification Code Codes Pins Hex DataA0 O7 O6 O5 O4 O3 O2 O1 O0 Manufacturer 0 00011110 1 E Device Type 1 00001011 0 B

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0189F–EPROM–4/03 Rapid Programming Algorithm A 100 µs CE pulse width is used to program. The address is set to the first location. VCC is raised to 6.5V and VPP is raised to 13.0V. Each address is first programmed with one 100 µs CE pulse without verification. Then a verification/reprogramming loop is executed for each address. In the event a byte fails to pass verification, up to 10 successive 100 µs pulses are applied with a verification after each pulse. If the byte fails to verify after 10 pulses have been applied, the part is considered failed. After the byte verifies properly, the next address is selected until all have been checked. V PP is then lowered to 5.0V and VCC to 5.0V. All bytes are read again and compared with the original data to determine if the device passes or fails.

0189F–EPROM–4/03

Ordering Information

tACC (ns) ICC (mA) Ordering Code Package Operation RangeActive Standby 70 30 0.1 AT27C040-70JC AT27C040-70PC AT27C040-70TC 32J 32P6 32T Commercial (0°C to 70°C) 30 0.1 AT27C040-70JI AT27C040-70PI AT27C040-70TI 32J 32P6 32T Industrial (-40°C to 85°C) 90 30 0.1 AT27C040-90JC AT27C040-90PC AT27C040-90TC 32J 32P6 32T Commercial (0°C to 70°C) 30 0.1 AT27C040-90JI AT27C040-90PI AT27C040-90TI 32J 32P6 32T Industrial (-40°C to 85°C) 120 30 0.1 AT27C040-12JC AT27C040-12PC AT27C040-12TC 32J 32P6 32T Commercial (0°C to 70°C) 30 0.1 AT27C040-12JI AT27C040-12PI AT27C040-12TI 32J 32P6 32T Industrial (-40°C to 85°C) 150 30 0.1 AT27C040-15JC AT27C040-15PC AT27C040-15TC 32J 32P6 32T Commercial (0°C to 70°C) 30 0.1 AT27C040-15JI AT27C040-15PI AT27C040-15TI 32J 32P6 32T Industrial (-40°C to 85°C) Package Type 32J 32-lead, Plastic J-leaded Chip Carrier (PLCC) 32P6 32-lead, 0.600" Wide, Plastic Dual Inline Package (PDIP) 32T 32-lead, Plastic Thin Small Outline Package (TSOP)

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0189F–EPROM–4/03

Package Information

32J – PLCC DRAWING NO. REV.

2325 Orchard Parkway

San Jose, CA 95131R TITLE 32J, 32-lead, Plastic J-leaded Chip Carrier (PLCC) B32J 10/04/01 1.14(0.045) X 45˚ PIN NO. 1 IDENTIFIER 1.14(0.045) X 45˚ 0.51(0.020)MAX 0.318(0.0125) 0.191(0.0075) 45˚ MAX (3X) A B1 E2 B e E1 E D COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MS-016, Variation AE. 2. Dimensions D1 and E1 do not include mold protrusion. Allowable protrusion is .010"(0.254 mm) per side. Dimension D1 and E1 include mold mismatch and are measured at the extreme material condition at the upper or lower parting line. 3. Lead coplanarity is 0.004" (0.102 mm) maximum. A 3.175 – 3.556 A1 1.524 – 2.413 A2 0.381 – – D 12.319 – 12.573 D1 11.354 – 11.506 Note 2 D2 9.906 – 10.922 E 14.859 – 15.113 E1 13.894 – 14.046 Note 2 E2 12.471 – 13.487 B 0.660 – 0.813 B1 0.330 – 0.533 e 1.270 TYP

0189F–EPROM–4/03 32P6 – PDIP San Jose, CA 95131 TITLE DRAWING NO. R REV. 32P6, 32-lead (0.600"/15.24 mm Wide) Plastic Dual Inline Package (PDIP) B32P6 09/28/01 PIN B REF E C L SEATING PLANE A 0º ~ 15º D e eB COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A – – 4.826 A1 0.381 – – D 41.783 – 42.291 Note 1 E 15.240 – 15.875 E1 13.462 – 13.970 Note 1 B 0.356 – 0.559 B1 1.041 – 1.651 L 3.048 – 3.556 C 0.203 – 0.381 eB 15.494 – 17.526 e 2.540 TYP Note: 1. Dimensions D and E1 do not include mold Flash or Protrusion. Mold Flash or Protrusion shall not exceed 0.25 mm (0.010").

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0189F–EPROM–4/03 32T – TSOP San Jose, CA 95131 TITLE DRAWING NO. R REV. 32T, 32-lead (8 x 20 mm Package) Plastic Thin Small Outline Package, Type I (TSOP) B32T 10/18/01 PIN 1 D1 D Pin 1 Identifier be E A 0º ~ 8º c L GAGE PLANESEATING PLANE COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE Notes: 1. This package conforms to JEDEC reference MO-142, Variation BD. 2. Dimensions D1 and E do not include mold protrusion. Allowable protrusion on E is 0.15 mm per side and on D1 is 0.25 mm per side. 3. Lead coplanarity is 0.10 mm maximum. A – – 1.20 A1 0.05 – 0.15 A2 0.95 1.00 1.05 D 19.80 20.00 20.20 D1 18.30 18.40 18.50 Note 2 E 7.90 8.00 8.10 Note 2 L 0.50 0.60 0.70 L1 0.25 BASIC b 0.17 0.22 0.27 c 0.10 – 0.21 e 0.50 BASIC

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