25HCU04A

IN74HCU04 INTEGRAL | Alldatasheet

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Technical content

High-Performance Silicon-Gate CMOS The IN74HC U04A is identical in pinout to the LS/A LS04. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs. This device consists of six single -stage inverters. These inverters are well suited for use as oscillators, pulse shapers , and in many other applications requiring a high -input impedance amplifier. For digital applications, the HC04 is recommended.

• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2.0 to 6.0 V; 2.5 to 6 V in Oscillator Configurations .
• Low Input Current: 1.0 µA
• High Noise Immunity Characteristic of CMOS Devices IN74HCU04

ORDERING INFORMATION

TA = -55° to 125° C for all packages LOGIC DIAGRAM PIN 14 =VCC PIN 7 = GND PIN ASSIGNMENT V CC14 GND FUNCTION TABLE Inputs Output A Y L H H L

MAXIMUM RATINGS* Symbol Parameter Value Unit VCC DC Supply Voltage (Referenced to GND) -0.5 to +7.0 V VIN DC Input Voltage (Referenced to GND) -1.5 to VCC +1.5 V VOUT DC Output Voltage (Referenced to GND) -0.5 to VCC +0.5 V IIN DC Input Current, per Pin ±20 mA IOUT DC Output Current, per Pin ±25 mA ICC DC Supply Current, VCC and GND Pins ±50 mA PD Power Dissipation in Still Air, Plastic DIP ** 750 500 mW Tstg Storage Temperature -65 to +150 °C TL Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) 260 °C *Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. ** Derating - Plastic DIP: - 10 mW/°C from 65° to 125°C RECOMMENDED OPERATING CONDITIONS Symbol Parameter Min Max Unit VCC DC Supply Voltage (Referenced to GND) 2.0 6.0 V VIN, VOUT DC Input Voltage, Output Voltage (Referenced to GND) 0 VCC V TA Operating Temperature, All Package Types -55 +125 °C tr, tf Input Rise and Fall Time (Figure 1) VCC =2.0 Â VCC =4.5 Â VCC =6.0 Â - 1000 500 400 ns This device contains protection circuitry to guard against damage due to high static voltages or electric fields. Howeve r, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high -impedance circuit. For proper operation, V IN and VOUT should be constrained to the range GND≤ (VIN or VOUT)≤ VCC. Unused inputs must always be t ied to an appropriate logic voltage level (e.g., either GND or V CC). Unused outputs must be left open.

DC ELECTRICAL CHARACTERISTICS(Voltages Referenced to GND) VCC Guaranteed Limit Symbol Parameter Test Conditions V 25 °C to -55°C ≤ 85 ≤ 125 Unit VIH Minimum High- Level Input Voltage VOUT=0.1 V * IOUT≤ 20 µA 2.0 4.5 6.0 1.7 3.6 4.8 1.7 3.6 4.8 1.7 3.6 4.8 V VIL Maximum Low - Level Input Voltage VOUT= VCC-0.1 V * IOUT ≤ 20 µA 2.0 4.5 6.0 0.3 0.8 1.1 0.3 0.8 1.1 0.3 0.8 1.1 V VOH Minimum High- Level Output Voltage VIN=VIL IOUT ≤ 20 µA 2.0 4.5 6.0 1.8 4.0 5.5 1.8 4.0 5.5 1.8 4.0 5.5 V VIN=VIL IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 3.98 5.48 3.84 5.34 3.7 5.2 VOL Maximum Low- Level Output Voltage VIN=VIH IOUT ≤ 20 µA 2.0 4.5 6.0 0.2 0.5 0.5 0.2 0.5 0.5 0.2 0.5 0.5 V VIN=VIH IOUT ≤ 4.0 mA IOUT ≤ 5.2 mA 4.5 6.0 0.26 0.26 0.33 0.33 0.4 0.4 IIN Maximum Input Leakage Current VIN=VCC or GND 6.0 ±0.1 ±1.0 ±1.0 µA ICC Maximum Quiescent Supply Current (per Package) VIN=VCC or GND IOUT=0µA 6.0 2.0 20 40 µA * For VCC = 2.0 V, VOUT = 0.2 V or VCC – 0.2 V.

For load considerations, see Chepter 4. Figure 1. Switching Waveforms. Figure 2. Test Circuit

R2 > > R1 C1 < C2 Vout R2 R1 C 1/6 HCU041/6 HCU041/6 HCU04 Vout Schmitt Trigger High Input Single-Stage Amplifier with a 2 to 6 V Supply Range Vin Vout 1/6 HCU04 1/6 HCU04 R2 > 6R1 VCC INPUT OUTPUT 1 M 1 M 1/6 HCU04 Multi-Stage Amplifier LED Driver VCC INPUT OUTPUT 1/6 HCU04 1/6 HCU04 1/6 HCU04 1/6 HCU04 For reduced power suplly current, use high-efficiency LEDs such as the Hewlett-Packard HLMP series or equivalent

CHIP PAD DIAGRAM IZ74HCU04 Chip marking 25HCU04A (x=0.992, y=0.092) 1.17 + 0.003 1.19 + 0.003 (0,0) Thickness of chip 0.46 ± 0,02 mm PAD LOCATION Pad No Symbol X Y Pad size* , mm 01 A1 0.110 0.280 0.105x0.105 02 Y1 0.170 0.110 0.105x0.105 03 A2 0.350 0.110 0.105x0.105 04 Y2 0.610 0.110 0.105x0.105 05 A3 0.850 0.110 0.105x0.105 06 Y3 0.950 0.320 0.105x0.105 07 GND 0.950 0.510 0.105x0.105 08 Y4 0.950 0.760 0.105x0.105 09 A4 0.850 0.970 0.105x0.105 10 Y5 0.610 0.970 0.105x0.105 11 A5 0.350 0.970 0.105x0.105 12 Y6 0.170 0.970 0.105x0.105 13 A6 0.110 0.800 0.105x0.105 14 VCC 0.110 0.550 0.105x0.105 * Pad size is given as per metallization layer