24C64

24C64_1 ESTEK | Alldatasheet

Document overview

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Technical content

Features

The 24C32/ 24C64 provides 32,768/65,536 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 4096/8192 words of 8 bits each. The device is optimized for use in many industrial and commercial applications where low-power and low-voltage operation are essential. The 24C32/ 24C64 is available in space-saving 8-lead PDIP, 8-lead SOP, and 8-lead TSSOP packages and is accessed via a two-wire serial interface. Pin Configuration Pin Descriptions Pin Designation A0 - A2 SDA SCL GND WP V CC Name and Functions Write Protect Address Inputs Serial Data Serial Clock Input Ground Power Supply I I I P P Type Table 1: Pin Configuration I/O & Open-drain SDA SCL WP V CC GND 8-lead PDIP SDA SCL WP V CC GND 8-lead SOP SDA SCL WP V CC GND 8-lead TSSOP 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD

V CC GND START STOP LOGIC SERIAL CONTROL LOGIC DEVICE ADDRESS COMPARATOR DATA WORD ADDRESS COUNTER LOAD COMP LOAD INC Y DECODER HIGH VOLTAGE PUMP/TIMING EN DATA RECOVERY EEPROM SERIAL MUX X DECODER DOUT/ACKNOWLEDGE DIN DOUT 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD

DEVICE/PAGE ADDRESSES (A2, A1 and A0): The A2, A1 and A0 pins are device address inputs that are hard wired for the 24C32/ 24C64. Eight 32K/64K devices may be addressed on a single bus system (device addressing is discussed in detail under the Device Addressing section). SERIAL DATA (SDA): The SDA pin is bi-directional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open-drain or open- collector devices. SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. WRITE PROTECT (WP): The 24C32/ 24C64 has a Write Protect pin that provides hardware data protection. The Write Protect pin allows normal read/write operations when connected to ground (GND). When the Write Protect pin is connected to V CC , the write protection feature is enabled and operates as shown in the following Table 2. Memory Organization 24C32, 32K SERIAL EEPROM: Internally organized with 128 pages of 32 bytes each, the 32K requires an 12-bit data word address for random word addressing. 24C64, 64K SERIAL EEPROM: Internally organized with 256 pages of 32 bytes each, the 64K requires a 13-bit data word address for random word address Table 2: Write Protect WP Pin Status Part of the Array Protected 24C64 Full (64K) Array 24C32 Full (32K) Array Normal Read / Write Operations At V CC At GND 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD

Figure 3: Output Acknowledge Device Addressing The 32K and 64K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 4 on page 7). The device address word consists of a mandatory "1", "0" sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 32K/64K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The eighth bit of the device address is the read/write operation select bit. A read operation is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a "0". If a compare is not made, the chip will return to a standby state. SCL DATA IN DATA OUT 8 9 ACKNOWLEDGE START 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD

BYTE WRITE: A write operation requires two 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a "0" and then clock in the first 8- bit data word. Following receipt of the 8-bit data word, the EEPROM will output a "0" and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, tWR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 5 on page 7). PAGE WRITE: The 32K/64K EEPROM is capable of an 32-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to 31 (32K, 64K) more data words. The EEPROM will respond with a "0" after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 6 on page 7). The data word address lower five (32K, 64K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than 32 (32K, 64K) data words are transmitted to the EEPROM, the data word address will "roll over" and previous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a "0", allowing the read or write sequence to continue. Read Operations Read operations are initiated the same way as write operations with the exception that the read/write select bit in the device address word is set to "1". There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed during the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address "roll over" during read is from the last byte of the last memory page to the first byte of the first page. The address "roll over" during write is from the last byte of the current page to the first byte of the same page. Once the device address with the read/write select bit set to "1" is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input "0" but does generate a following stop condition (see Figure 7 on page 8). 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD

Absolute Maximum Stress Ratings CC +0.3V

Electrical Characteristics

Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to this device. These are stress ratings only. Functional operation of this device at these or any other conditions above those indicated in the operational sections of this specification is not implied or intended. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability. Applicable over recommended operating range from: T A CC = +1.8V to +5.5V (unless otherwise noted) Parameter Supply Voltage Supply Current V CC = 5.0V Supply Current V CC = 5.0V Standby Current 5.5 1.0 3.0 1.0 Max. READ at 100 kHz WRITE at 100 kHz V IN = V CC or GND Condition 1.8 Min. V CC I CC1 I CC2 I SB Symbol 0.4 2.0 Typ. V mA mA Unit A Input Leakage Current Output Leakage Current Input Low Level Output Low Level V CC =1.8V Output Low Level V CC =5.0V Input High Level Output Low Level V CC =3.0V 3.0 3.0 V CC X 0.3 0.2 0.4 V CC + 0.5 0.4 V IN = V CC or GND V OUT = V CC or GND I OL = 0.15 mA I OL = 3.0 mA I OL = 2.1 mA -0.6 V CC X 0.7 I LI I LO V IL V OL1 V OL3 V IH V OL2 0.05 V V V V V A A Pin Capacitance Applicable over recommended operating range from T A = 25 。C, f = 1.0 MHz, V CC = +1.8V Parameter Input/Output Capacitance (SDA) Input Capacitance (A0, A1, A2, Max. V IN = 0V Condition Min. C I/O C IN Symbol Typ. pF pF Unit SCL) V I/O = 0V 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD

Applicable over recommended operating range from T A = -40。C to +85。C, V CC = +1.8V to +5.5V, CL = 1 TTL Gate and 100 pF (unless otherwise noted) Note Parameter Clock Frequency, SCL Clock Pulse Width Low Clock Pulse Width High Start Hold Time Clock Low to Data Out Valid Noise Suppression Time Time the bus must be free before a new transmission can start Start Setup Time Data In Hold Time Data In Setup Time Data Out Hold Time Write Cycle Time Inputs Fall Time(1) Inputs Rise Time(1) Stop Setup Time f SCL t LOW t HIGH t HD.STA t AA t I t BUF t SU.STA t HD.DAT t SU.DAT t DH t WR 5.0V, 25 C, Byte Mode 1.2 0.6 0.6 0.05 1.2 0.6 100 0.6 400 0.9 300 0.3 0.6 0.4 0.25 0.05 0.5 0.25 100 0.25 1000 0.55 100 0.3 kHz ns ns ms ns Write CyclesEndurance t F t R t SU.STO Max. Units Min. Symbol Typ. 1.8-volt Max.Min. Typ. 5.0-volt s s s s s s s s s s 1. This parameter is characterized and is not 100% tested. 2. AC measurement conditions: R L (connects to V CC Input pulse voltages: 0.3 V CC to 0.7 V CC Input rise and fall time: 50 ns Input and output timing reference voltages: 0.5 V CC The value of R L should be concerned according to the actual loading on the user's system. 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD

Ordering Information

1.Prefix 2.Series Name 24: Two-wire (I2C) Interface 3.EEPROM Density C32=32K bits C64=64K bits 4.Design Option o= (Blank) 5.Package Type D = DIP S = SOP R = TSSOP W = Wafer/die 6. Temperature Range C = Com Temp(0 C-70 I = Ind Temp(-40 C-85 E = Exp Temp(-40 C-125 7.Pack Type T = Tube R = Tape & Reel 8.Plating Technology Blank = Standard SnPb plating G = ECOPACK(RoHS compliant) 9.Operating Voltage S=2.7~5.5 A=1.8~5.5 K 24 XXX X - X X X X - X 1 2 3 4 5 6 7 8 9 Code Number Part Number Product Datasheet Change Notice 1.0 Datasheet Mar., 2007 Version Content Date Datasheet Revision History 24C32 / 24C64 BEIJING ESTEK ELECTRONICS CO.,LTD