24C21

AT24C21 ATMEL | Alldatasheet

Document overview

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Technical content

Features

• 2-Wire Serial Interface
• Schmitt Trigger, Filtered Inputs For Noise Suppression
• DDC1™/ DDC2™ Interface Compliant for Monitor Identification
• Low Voltage Operation – 2.5 (VCC = 2.5V to 5.5V)
• Internally Organized 128 x 8
• 100 kHz (2.5V) Compatibility
• 8-Byte Page Write Mode
• Write Protection Available
• Self-timed Write Cycle (10 ms max)
• High Reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years – ESD Protection: >3000V
• 8-Pin PDIP and JEDEC SOIC Packages

Description

The AT24C21 provides 1024 bits of serial electrically erasable and programmable read only memory (EEPROM) organized as 128 words of 8 bits each. The device is optimized for use in applications requiring data storage and serial transmission of con- figuration and control information. The AT24C21 features two modes of operation: Transmit-Only Mode and Bidirectional Mode. Upon power-up, the AT24C21 will be in the Transmit-Only Mode, sending a serial-bit stream of the entire memory contents, clocked via the VCLK pin. The Bidirectional Mode is selected by a valid high-to-low transition on the SCL pin and offers byte selectable read/write capability of the entire memory array. The AT24C21 is available in space saving 8-pin PDIP and 8-pin SOIC packages. 2-Wire Serial EEPROM 1K (128 x 8) AT24C21 Rev. 0405E–07/98 2-Wire, 1K Serial EEPROM Pin Configurations Pin Name Function NC No Connect SDA Serial Data SCL Serial Clock Input (Bidirectional Mode) VCLK Serial Clock Input (T ransmit-Only Mode) 8-Pin PDIP 8-Pin SOIC

SERIAL CLOCK (SCL): The SCL input is used to positive edge clock data into each EEPROM device and negative edge clock data out of each device. SERIAL DATA (SDA): The SDA pin is bidirectional for serial data transfer. This pin is open-drain driven and may be wire-ORed with any number of other open drain or open collector devices. SERIAL CLOCK (VCLK): Upon power-up, the device is in the Transmit-Only mode and will transmit the entire mem- ory contents via the SDA pin with positive signals on the VCLK pin. Memory Organization AT24C21, 1K SERIAL EEPROM: Internally organized with 128 pages of one byte each. The 1K requires a 7-bit data word address for random word addressing. Absolute Maximum Ratings* Maximum Ratings” may cause permanent dam- age to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Voltage on Any Pin

Note: 1. V IL min and VIH max are for reference only and not tested. Note: 1. This parameter is characterized and is not 100% tested. DC Characteristics Applicable over recommended operating range from: TAI = -40°C to +85°C, TAC = 0°C to +70°C, VCC = +2.5V to +5.5V (unless otherwise noted). Symbol Parameter Test Condition Min Typ Max Units VCC Supply Voltage 2.5 5.5 V ICC Supply Current VCC = 5.0V READ at 100 KHz 0.4 1.0 mA ICC Supply Current VCC = 5.0V WRITE at 100 KHz 2.0 3.0 mA VIN = VCC or VSS VIN = VCC or VSS 3.0 12.0 4.0 30.0 µA µA ILI Input Leakage Current V IN = VCC or VSS 0.10 1.0 µA ILO Output Leakage Current V OUT = VCC or VSS 0.05 1.0 µA VIL Input Low Level(1) SCL, SDA Pin Input Low Level VCLK Pin V CC ≥ 2.7V VCC < 2.7V -0.6 V CC × 0.3 0.8 0.2 × VCC V V V VIH Input High Level(1) SCL, SDA Pin Input High Level VCLK Pin VCC × 0.7 2.0 VCC + 0.5 V V VOL Output Low Level VCC = 3.0V I OL = 2.1 mA 0.40 V Pin Capacitance(1) Applicable over recommended operating range from TA = 25°C, f = 1.0 MHz, VCC = +1.8V. Symbol Test Condition Max Units Conditions C I/O Input/Output Capacitance (SDA) 8 pF V I/O = 0V C IN Input Capacitance (A0, A1, A2, SCL, VCLK) 6 pF V IN = 0V Transmit-Only Mode Symbol Parameter 2.5-volt Units Min Max TVAA Output valid from VCLK 500 ns TVHIGH VCLK high-time 4.0 µs TVLOW VCLK low-time 4.7 µs TVHZ Mode transition time 500 ns TVPU T ransmit-Only power-up time 0 ns

Note: 1. This parameter is characterized and is not 100% tested. AC Characteristics Applicable over recommended operating range from TA = -40°C to +85°C, VCC = +2.5V to +5.5V CL = 1 TTL Gate and 100 pF (unless otherwise noted). Symbol Parameter 2.5-volt UnitsMin Max fSCL Clock Frequency, SCL 0 100 KHz tLOW Clock Pulse Width Low 4.7 µs tHIGH Clock Pulse Width High 4.0 µs tI Noise Suppression Time(1) (SDA and SCL pins) NA ns tAA Clock Low to Data Out Valid 0.1 3.5 µs tBUF Time the bus must be free before a new transmission can start 4.7 µs tHD.ST A Start Hold Time 4.0 µs tSU.ST A Start Set-up Time 4.7 µs tHD.DAT Data In Hold Time 0 µs tSU.DA T Data In Set-up Time 250 ns tR Inputs Rise Time(1) 1.0 µs tF Inputs Fall Time(1) 300 ns tSU.STO Stop Set-up Time 4.0 µs tDH Data Out Hold Time 100 ns tWR Write Cycle Time 10 ms Endurance(1) 5.0V , 25°C, Page Mode 1M Write Cycles

reads are supported in this mode. ally transmitted to and from the EEPROM in 8-bit words. write operation (refer to Figure 4). shown. This is common to all the EEPROM devices. The next three bits are don’t care for the AT24C21. and a write operation is initiated if this bit is low. Figure 3. Mode Transition

SCL: Serial Clock, SDA: Serial Data I/O Write Cycle Timing SCL: Serial Clock, SDA: Serial Data I/O Note: 1. The write cycle time tWR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle. SCL SDA WORD n 8th BIT ACK STOP CONDITION START CONDITION tWR (1)

BYTE WRITE: A write operation requires an 8-bit data word addresses following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a zero and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a zero and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally-timed write cycle , t WR , to the nonvola- tile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is com- plete (refer to Figure 5). It is required that VCLK be held at a high logic level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. PAGE WRITE: The AT24C21 is capable of an 8-byte page write. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcon- troller can transmit up to seven more data words. The EEPROM will respond with a zero after each data word received. The microcontroller must terminate the page write sequence with a stop condition (refer to Figure 6). The data word address lower three bits are internally incre- mented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, inter- nally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight data words are transmitted to the EEPROM, the data word address will “roll over” and previous data will be overwritten. The address “roll over” during write is from the last byte of the current page to the first byte of the same page. It is required that VCLK be held at a high logic level in order to program the device. This applies to byte write and page write operation. Note that VCLK can go low while the device is in its self-timed program operation and not affect programming. ACKNOWLEDGE POLLING: Once the internally-timed write cycle has started and the EEPROM inputs are dis- abled, acknowledge polling can be initiated. This involves sending a start condition followed by the device address word. The read/write bit is representative of the operation desired. Only if the internal write cycle has completed will the EEPROM respond with a zero allowing the read or write sequence to continue. WRITE PROTECTION: When VCLK pin is connected to GND and in the Bidirectional Mode, the entire memory is protected and becomes ROM only. This protects the device memory from any inadvertent write operations. NOISE PROTECTION: Special internal circuitry placed on the SDA and SCL pins prevent small noise spikes from activating the device. Furthermore, the AT24C21 employs a low V CC detector circuit which disables the erase\\write logic whenever VCC falls below 1.5 volts. Read Operations Read operations are initiated the same way as write opera- tions with the exception that the read/write select bit in the device address word is set to one. There are three read operations: current address read, random address read and sequential read. CURRENT ADDRESS READ: The internal data word address counter maintains the last address accessed dur- ing the last read or write operation, incremented by one. This address stays valid between operations as long as the chip power is maintained. The address “roll over” during read is from the last byte of the last memory page to the first byte of the first page. Once the device address with the read/write select bit set to one is clocked in and acknowledged by the EEPROM, the current address data word is serially clocked out. The microcontroller does not respond with an input zero but does generate a following stop condition (refer to Figure 7). RANDOM READ: A random read requires a “dummy” byte write sequence to load in the data word address. Once the device address word and data word address are clocked in and acknowledged by the EEPROM, the microcontroller must generate another start condition. The microcontroller now initiates a current address read by sending a device address with the read/write select bit high. The EEPROM acknowledges the device address and serially clocks out the data word. The microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 8). SEQUENTIAL READ: Sequential reads are initiated by either a current address read or a random address read. After the microcontroller receives a data word, it responds with an acknowledge. As long as the EEPROM receives an acknowledge, it will continue to increment the data word address and serially clock out sequential data words. When the memory address limit is reached, the data word address will “roll over” and the sequential read will con- tinue. The sequential read operation is terminated when the microcontroller does not respond with a zero but does generate a following stop condition (refer to Figure 9).

Figure 9. Sequential Read

Ordering Information

tWR (max) (ms) ICC (max) (µA) ISB (max) (µA) fMAX (KHz) Ordering Code Package Operation Range 10 3000 4 100 A T24C21-10PC-2.5 A T24C21-10SC-2.5 8P3 8S1 Commercial (0°C to 70°C) 3000 4 100 A T24C21-10PI-2.5 A T24C21-10SI-2.5 8P3 8S1 Industrial (-40°C to 85°C) Package Type 8P3 8-Lead, 0.300" Wide, Plastic Dual Inline Package (PDIP) 8S1 8-Lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Options -2.5 Low-Voltage (2.5V to 5.5V)

.400 (10.16) .355 (9.02) PIN .280 (7.11) .240 (6.10) .037 (.940) .210 (5.33) MAX SEATING PLANE .100 (2.54) BSC .015 (.380) MIN .022 (.559) .014 (.356) .150 (3.81) .115 (2.92) .070 (1.78) .045 (1.14) .325 (8.26) .300 (7.62)

15 REF

.430 (10.9) MAX .012 (.305) .008 (.203) .020 (.508) .013 (.330) PIN 1 .157 (3.99) .150 (3.81) .244 (6.20) .228 (5.79) .050 (1.27) BSC .196 (4.98) .189 (4.80) .068 (1.73) .053 (1.35) .010 (.254) .004 (.102) 8 REF .010 (.254) .007 (.203) .050 (1.27) .016 (.406) 8P3, 8-Lead, 0.300” Wide, Plastic Dual Inline Package (PDIP) Dimensions in Inches and (Millimeters) JEDEC STANDARD MS-001 BA 8S1, 8-Lead, 0.150” Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) Dimension in Inches and (Millimeters)