AT24C08A_14 ATMEL | Alldatasheet
Document overview
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Technical content
Features
Standard-voltage Operation – 2.7 (V CC = 2.7V to 5.5V) Automotive Temperature Range –40Ct o1 2 5C Internally Organized 128 x 8 (1K), 256 x 8 (2K), 512 x 8 (4K), 1024 x 8 (8K) or 2048 x 8 (16K) Two-wire Serial Interface Schmitt Trigger, Filtered Inputs for Noise Suppression Bidirectional Data Transfer Protocol 400 kHz Compatibility Write Protect Pin for Hardware Data Protection 8-byte Page (1K, 2K), 16-byte Page (4K, 8K, 16K) Write Modes Partial Page Writes are Allowed Self-timed Write Cycle (5 ms max) High-reliability – Endurance: 1 Million Write Cycles – Data Retention: 100 Years 8-lead JEDEC SOIC and 8-lead TSSOP Packages
Description
The AT24C01A/02/04/08A/16A provides 1024/2048/4096/8192/16384 bits of serial electrically erasable and programmable read-only memory (EEPROM) organized as 128/256/512/1024/2048 words of 8 bits each. The device is optimized for use in many automotive applications where low-power and low-voltage operation are essential. The AT24C01A/02/04/08A/16A is available in space-saving 8-lead JEDEC SOIC and 8-lead TSSOP packages and is accessed via a two-wire serial interface. In addition, the entire family is available in 2.7V (2.7V to 5.5V) versions. Table 1. Pin Configurations
- AT24C02 not recommended for
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Figure 1. Block Diagram EEPROM device and negative edge clock data out of each device. discussed in detail under the Device Addressing section). devices may be addressed on a single bus system. The A0 pin is a no connect.
devices on a single bus to one. The A0, A1 and A2 pins are no connects. the 1K requires a 7-bit data word address for random word addressing. the 2K requires an 8-bit data word address for random word addressing. the 4K requires a 9-bit data word address for random word addressing. the 8K requires a 10-bit data word address for random word addressing. each, the 16K requires an 11-bit data word address for random word addressing. Table 2. Write Protect
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Note: 1. This parameter is characterized and is not 100% tested. Note: 1. V IL min and VIH max are reference only and are not tested. Table 3. Pin Capacitance(1) Table 4. DC Characteristics
Note: 1. This parameter is characterized and is not 100% tested (T A =2 5C).
- This parameter is characterized.
which must precede any other command (see to Figure 5 on page 7). STOP CONDITION: A low-to-high transition of SDA with SCL high is a stop condition. mode (see Figure 5 on page 7). each word. This happens during the ninth clock cycle. completion of any internal operations. Table 5. AC Characteristics
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- Look for SDA high in each cycle while SCL is high.
- Create a start condition.
Figure 2. SCL: Serial Clock, SDA: Serial Data I/O Figure 3. SCL: Serial Clock, SDA: Serial Data I/O Note: 1. The write cycle time t WR is the time from a valid stop condition of a write sequence to the end of the internal clear/write cycle.
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5092D–SEEPR–4/07 Device Addressing The 1K, 2K, 4K, 8K and 16K EEPROM devices all require an 8-bit device address word following a start condition to enable the chip for a read or write operation (see to Figure 7 on page 9). The device address word consists of a mandatory “1”, “0” sequence for the first four most significant bits as shown. This is common to all the Serial EEPROM devices. The next 3 bits are the A2, A1 and A0 device address bits for the 1K/2K EEPROM. These 3 bits must compare to their corresponding hardwired input pins. The 4K EEPROM only uses the A2 and A1 device address bits with the third bit being a memory page address bit. The two device address bits must compare to their corre- sponding hardwired input pins. The A0 pin is no connect. The 8K EEPROM only uses the A2 device address bit with the next two bits being for memory page addressing. The A2 bit must compare to its corresponding hardwired input pin. The A1 and A0 pins are no connect. The 16K does not use any device address bits but instead the three bits are used for memory page addressing. These page addressing bits on the 4K, 8K and 16K devices should be considered the most significant bits of the data word address which follows. The A0, A1 and A2 pins are no connect. The eighth bit of the device address is the read/write operation select bit. A read opera- tion is initiated if this bit is high and a write operation is initiated if this bit is low. Upon a compare of the device address, the EEPROM will output a “0”. If a compare is not made, the chip will return to a standby state. Write Operations BYTE WRITE: A write operation requires an 8-bit data word address following the device address word and acknowledgment. Upon receipt of this address, the EEPROM will again respond with a “0” and then clock in the first 8-bit data word. Following receipt of the 8-bit data word, the EEPROM will output a “0” and the addressing device, such as a microcontroller, must terminate the write sequence with a stop condition. At this time the EEPROM enters an internally timed write cycle, t WR, to the nonvolatile memory. All inputs are disabled during this write cycle and the EEPROM will not respond until the write is complete (see Figure 8 on page 10). PAGE WRITE: The 1K/2K EEPROM is capable of an 8-byte page write, and the 4K, 8K and 16K devices are capable of 16-byte page writes. A page write is initiated the same as a byte write, but the microcontroller does not send a stop condition after the first data word is clocked in. Instead, after the EEPROM acknowledges receipt of the first data word, the microcontroller can transmit up to seven (1K/2K) or fifteen (4K, 8K, 16K) more data words. The EEPROM will respond with a “0” after each data word received. The microcontroller must terminate the page write sequence with a stop condition (see Figure 9 on page 10). The data word address lower three (1K/2K) or four (4K, 8K, 16K) bits are internally incremented following the receipt of each data word. The higher data word address bits are not incremented, retaining the memory page row location. When the word address, internally generated, reaches the page boundary, the following byte is placed at the beginning of the same page. If more than eight (1K/2K) or sixteen (4K, 8K, 16K) data words are transmitted to the EEPROM, the data word address will “roll over” and previ- ous data will be overwritten. ACKNOWLEDGE POLLING: Once the internally timed write cycle has started and the EEPROM inputs are disabled, acknowledge polling can be initiated. This involves send-
will the EEPROM respond with a “0”, allowing the read or write sequence to continue. operations: current address read, random address read and sequential read. rent page to the first byte of the same page. acknowledged by the EEPROM, the current address data word is serially clocked out. stop condition (see Figure 10 on page 10). with a “0” but does generate a following stop condition (see Figure 11 on page 11). Figure 7. Device Address
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Figure 8. Byte Write Figure 9. Page Write Figure 10. Current Address Read
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5092D–SEEPR–4/07 Note: 1. This device is not recommended for new design. Please refer to AT24C01B Automotive datasheet. Ordering Code Package Operation Range AT24C01A-10SQ-2.7 AT24C01A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free/Automotive Temperature (40Ct o1 2 5C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options 2.7 Low-voltage (2.7V to 5.5V)
5092D–SEEPR–4/07 Note: 1. This device is not recommended for new design. Please refer to AT24C02B Automotive datasheet. Ordering Code Package Operation Range AT24C02N-10SQ-2.7 AT24C02-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free/Automotive Temperature (40Ct o1 2 5C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options 2.7 Low-voltage (2.7V to 5.5V)
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5092D–SEEPR–4/07 Ordering Code Package Operation Range AT24C04N-10SQ-2.7 AT24C04-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free/Automotive Temperature (40Ct o1 2 5C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options 2.7 Low-voltage (2.7V to 5.5V)
5092D–SEEPR–4/07 Note: For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 4 on page 4 and Table 5 on page 5). Ordering Code Package Operation Range AT24C08AN-10SQ-2.7 AT24C08A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free/ Automotive Temperature (40Ct o1 2 5C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options 2.7 Low Voltage (2.7V to 5.5V)
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5092D–SEEPR–4/07 Notes: 1. For 2.7V devices used in the 4.5V to 5.5V range, please refer to performance values in the AC and DC characteristics tables (Table 4 on page 4 and Table 5 on page 5). 2. AT24C16A not recommended for new design; replaced by AT24C16C Automotive. Ordering Code Package Operation Range AT24C16AN-10SQ-2.7 AT24C16A-10TQ-2.7 8S1 8A2 Lead-free/Halogen-free/ Automotive Temperature (40Ct o1 2 5C) Package Type 8S1 8-lead, 0.150" Wide, Plastic Gull Wing Small Outline (JEDEC SOIC) 8A2 8-lead, 0.170" Wide, Thin Shrink Small Outline Package (TSSOP) Options 2.7 Low Voltage (2.7V to 5.5V)
5092D–SEEPR–4/07 Packaging Information 8S1 – JEDEC SOIC 1150 E. Cheyenne Mtn. Blvd. Colorado Springs, CO 80906 TITLE DRAWING NO. R REV. Note: 10/7/03 8S1, 8-lead (0.150" Wide Body), Plastic Gull Wing Small Outline (JEDEC SOIC) 8S1 B COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE A1 0.10 – 0.25 These drawings are for general information only. Refer to JEDEC Drawing MS-012, Variation AA for proper dimensions, tolerances, datums, etc. A 1.35 – 1.75 b 0.31 – 0.51 C 0.17 – 0.25 D 4.80 – 5.00 E1 3.81 – 3.99 E 5.79 – 6.20 e 1.27 BSC L 0.40 – 1.27 ∅ 0˚ – 8˚ Top View End View Side View e B D A N E C L
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5092D–SEEPR–4/07
2325 Orchard Parkway
San Jose, CA 95131 TITLE DRAWING NO. R REV. 5/30/02 COMMON DIMENSIONS (Unit of Measure = mm) SYMBOL MIN NOM MAX NOTE D 2.90 3.00 3.10 2, 5 E 6.40 BSC E1 4.30 4.40 4.50 3, 5 A – – 1.20 A2 0.80 1.00 1.05 b 0.19 – 0.30 4 e 0.65 BSC L 0.45 0.60 0.75 L1 1.00 REF 8A2, 8-lead, 4.4 mm Body, Plastic Thin Shrink Small Outline Package (TSSOP) Notes: 1. This drawing is for general information only. Refer to JEDEC Drawing MO-153, Variation AA, for proper dimensions, tolerances, datums, etc. 2. Dimension D does not include mold Flash, protrusions or gate burrs. Mold Flash, protrusions and gate burrs shall not exceed 0.15 mm (0.006 in) per side. 3. Dimension E1 does not include inter-lead Flash or protrusions. Inter-lead Flash and protrusions shall not exceed 0.25 mm (0.010 in) per side. 4. Dimension b does not include Dambar protrusion. Allowable Dambar protrusion shall be 0.08 mm total in excess of the b dimension at maximum material condition. Dambar cannot be located on the lower radius of the foot. Minimum space between protrusion and adjacent lead is 0.07 mm. 5. Dimension D and E1 to be determined at Datum Plane H. 8A2 B Side View End ViewTop View A L D 123 N b Pin 1 indicator this corner E e 8A2 – TSSOP
5092D–SEEPR–4/07
Revision History
Doc. Rev. Date Comments 5092D 8/2012 AT24C16A not recommended for new design; replaced by AT24C16C Automotive. 5092D 4/2007 Added ‘Not recommended for new design’ notes to AT24C01A and AT24C02 on pages 1, 12 and 13. 5092C 2/2007 Implemented revision history. Removed PDIP offering and parts. Added ‘AT24C02 Not Recommended for New Design’ note to page
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