1345 AGERE | Alldatasheet
Document overview
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Technical content
Features
■ Backward compatible with 1330 family ■ Space-saving, self-contained, 20-pin plastic DIP ■ Silicon based ICs ■ Single 5 V power supply operation including photocurrent monitor capability ■ Exceeds all SONET (GR-253-CORE) and ITU-T G.958 jitter requirements ■ Clocked decision circuit ■ Regenerated differential clock signal ■ Wide dynamic range ■ Qualified to meet the intent of T elcordia T echnolo- gies ™ reliability practices ■ Operates at data rates of 155 Mbits/s or
622 Mbits/s
■ Positive ECL (PECL) data outputs ■ CMOS (TTL) link-status flag output ■ Operation at 1.3 µm or 1.55 µm wavelengths ■ Operating temperature range of –40 °C to +85 °C
Applications
■ T elecommunications: — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks ■ High-speed data communications
Description
The 1345-T ype fiber-optic receiver is designed for use in transmission systems or medium- to high- speed data communication applications. Used in intermediate- and long-reach applications, the receiver operates at the SONET OC-3 or OC-12 data rate as well as the ITU-T synchronous digital hierar- chy (SDH) rate of STM-1 or STM-4, depending on the receiver model chosen. The receiver meets all present Telcordia Technologies GR-253-CORE requirements, the current ANSI T1X1.5 intraoffice specifications, and the ITU-T G.957 and G.958 rec- ommendations. Compact packaging, a high level of integration, and a wide dynamic range make these receivers ideal for data communications. Manufactured in a 20-pin DIP , the receiver consists of a planar InGaAs PIN photodetector, a silicon pream- plifier, a silicon bipolar limiting amplifier that converts the small signal to ECL levels, a timing recovery unit to recover the clock, and a silicon bipolar decision cir- cuit.
1.1µm to 1.6 µm into retimed clock and data signals. there is a loss of optical signal. temperature range is –40 °C to +85 °C. clock outputs are squelched (stop outputting a signal). Figure 1. Block Diagram
5 V DATA DATA
3Agere Systems Inc. Data Sheet 1345-Type Receiver with January 2000 Clock Recovery and Data Retiming Absolute Maximum Ratings Stresses in excess of the absolute maximum ratings can cause permanent damage to the device. These are abso- lute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of the data sheet. Exposure to absolute maximum ratings for extended periods can adversely affect device reliability. Parameter Symbol Min Max Unit Supply Voltage V CC 05 . 5V Operating Case T emperature Range T C –40 85 °C Storage Case T emperature Range T stg –40 85 °C Lead Soldering T emperature/Time — — 250/10 °C/s Operating Wavelength Range λ 1.1 1.6 µm Minimum Fiber Bend Radius — 1.0 (25.4) — in. (mm) Pin Information * Pins designated as no user connection are not connected inter- nally. However, to allow for future functional upgrades, it is recom- mended that the user not make any connections to these pins. † The link status flag is a logic flag that indicates the presence or absence of a minimum acceptable level of optical input. A logic high on the FLAG output indicates the presence of a valid optical signal. Mounting and Connections The pigtail consists of a 39 in. ± 4 in. (1 m ± 10 cm), 62.5 µm core/125 µm cladding multimode fiber. The standard fiber has a 0.036 in. (914 µm) diameter tight- buffered outer-jacket. The minimum fiber bending radius during operation is 1.0 in. (25.4 mm). Electrostatic Discharge CAUTION: This device is susceptible to damage as a result of electrostatic discharge (ESD). Take proper precautions during both handling and testing. Follow guide- lines such as EIA ® Standard EIA-625. Although protection circuitry is designed into the device, take proper precautions to avoid exposure to ESD. Agere Systems Inc. employs a human-body model (HBM) for ESD susceptibility testing and protection- design evaluation. ESD voltage thresholds are depen- dent on the critical parameters used to define the model. A standard HBM (resistance = 1.5 kΩ capaci- tance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM ESD thresh- old established for the 1345 receiver is ±1000 V . Receiver Processing The 1345-T ype receiver devices can withstand normal wave-soldering processes. The complete receiver module is not hermetically sealed; therefore, it should not be immersed in or sprayed with any cleaning solu- tion or solvents. The process cap and fiber pigtail jacket can deform at temperatures greater than 85 °C. The receiver pins can be wave-soldered at maximum tem- perature of 250 °C for 10 seconds. Pin Name Pin Name
1 Ground 20 No User Connection*
2 Ground 19 No User Connection*
3 Ground 18 No User Connection*
4 CLOCK 17 No User Connection*
16 Ground
6 Ground 15 Ground
8 Ground 13 Ground
12 FLAG †
10 No Internal
11 V CC
44 Agere Systems Inc. 1345-Type Receiver with Data Sheet Clock Recovery and Data Retiming January 2000
Application Information
The 1345 receiver is a highly sensitive fiber-optic receiver. Although the data outputs are digital logic lev- els (PECL), the device should be thought of as an ana- log component. When laying out the printed-wiring board (PWB), the 1345 receiver should be given the same type of consideration one would give to a sensi- tive analog component. At a minimum, a double-sided printed-wiring board with a large component-side ground plane beneath the receiver must be used. In applications that include many other high-speed devices, a multilayer PWB is highly recommended. This permits the placement of power and ground connections on separate layers, which helps minimize the coupling of unwanted signal noise into the power supplies of the receiver. Layout Considerations A fiber-optic receiver employs a very high-gain, wide- bandwidth transimpedance amplifier. The amplifier detects and amplifies signals that are only tens of nA in amplitude. Any unwanted signal currents that couple into the receiver circuitry cause a decrease in the receiver's sensitivity and can also degrade the perfor- mance of the receiver's loss of signal (FLAG) circuit. T o minimize the coupling of unwanted noise into the receiver, route high-level, high-speed signals such as transmitter inputs and clock lines as far away as possi- ble from the receiver pins. If this is not possible, then the PWB layout engineer should consider interleaving the receiver signal and flag traces with ground traces in order to provide the required isolation. Noise that couples into the receiver through the power supply pins can also degrade device performance. The application schematics, Figures 2—3, show recom- mended power supply filtering that helps minimize noise coupling into the receiver. The bypass capacitors should be high-quality ceramic devices rated for RF applications. They should be surface-mount compo- nents placed as close as possible to the receiver power supply pins. The ferrite bead should have as high an impedance as possible in the frequency range that is most likely to cause problems. This will vary for each application and is dependent on the signaling frequen- cies present on the application circuit card. Surface- mount, high-impedance beads are available from sev- eral manufacturers. Data and Flag Outputs The data and clock outputs of the 1345 receiver are driven by open-emitter NPN transistors which have an output impedance of approximately 7 Ω . Each output can provide approximately 50 mA maximum output cur- rent. Due to the high switching speeds of ECL outputs, transmission line design must be used to interconnect components. To ensure optimum signal fidelity, both data outputs (DA TA and DA T A ) and clock outputs (CLOCK and CLOCK ) should be terminated identically. The signal lines connecting the data and clock outputs to the next device should be equal in length and should have matched impedances. Controlled impedance stripline or microstrip construc- tion must be used in order not to degrade the quality of the signal into the next component and to minimize reflections back into the receiver. Excessive ringing due to reflections caused by improperly terminated signal lines makes it difficult for the component receiving these signals to decipher the proper logic levels and may cause transitions to occur where none were intended. Also, by minimizing high frequency ringing due to reflections caused by improperly designed and terminated signal lines, possible EMI problems can be avoided. The applications sections in the Signetics™ ECL 10K/100K Data Manual or the National Semicon- ductor ® ECL Logic Databook and Design Guide pro- vide excellent design information on ECL interfacing. The FLAG and FLAG outputs of the OC-3/STM-1
155 Mbits/s receiver and the OC-12/STM-4 622 Mbits/s
receiver are 5 V TTL logic-level compatible. The FLAG output is provided directly by the comparator IC. How- ever, the FLAG output is derived from the FLAG output through an inverter. Excessive loading of the FLAG out- put can cause the FLAG output to malfunction. Recommended User Interface The 1345 receiver is designed to be operated from a
5 V power supply and provides raised or pseudo-ECL
(PECL) data outputs. Figures 2 and 3 show two possi- ble application circuits for the 1345 receiver. Figure 2 represents an application for a PECL compatible inter- face while Figure 3 shows a possible application for an ac-coupled, ECL-compatible interface. In both instances, the DA T A outputs are terminated with a Thévenin equivalent circuit, which provides the equiva- lent of a 50 Ω load terminated to (V CC – 2 V). A single 50 Ω resistor terminated to (VCC – 2 V) could also be used, but this requires a second power supply. Other methods of terminating ECL-type outputs are dis- cussed in the references previously mentioned.
Figure 2. PECL-Compatible (5 V) Interface Figure 3. ac-Coupled ECL-Compatible Interface
5 CLOCK*
- DATA, DATA, CLOCK, and CLOCK are 50 Ω transmission lines that can be ac- or dc-coupled.
Assemblies T echnical Note (TN95-010LWP). ues are measured at beginning-of-life (BOL) room temperature unless otherwise noted. Table 1. Electrical Characteristics
- Customers have the option for either a +5 V or –5 V supply.
- Includes approximately 50 mA of DA T A and CLOCK output termination current.
- Measured with 50 Ω load terminated to (VCC – 2.00) V .
- DA TA and CLOCK outputs are 10K ECL compatible.
- Measured as shown in Figure 4.
- Measured with an input data pseudorandom word 223 – 1.
Table 2. Optical Characteristics
- For a 1 x 10–10 BER. Measured with a 223 – 1 pseudorandom word optical input having a 50% average duty cycle.
page 2 for the DAT A and CLOCK output signal levels. mended power supply filtering. Figure 4. Clock/Data Alignment
8 Agere Systems Inc. 1345-Type Receiver with Data Sheet Clock Recovery and Data Retiming January 2000 PWB Layout Guidelines ■ Follow high-speed ECL design rules. ■ All high-speed output lines must be controlled-impedance lines, and the termination impedance must match the line impedance. Controlled-impedance interruptions should be avoided (i.e., 90° bends, etc.) and paired lines (i.e., DA T A and DATA) should be of equal length. ■ Each output line should be terminated at the end of the line and must have a bypass capacitor on the voltage side of the resistor for each termination. ■ Data and clock output lines should be as short and as straight as possible and isolated from noise sources (and each other) to prevent noise from feeding back into the receiver. ■ Noise that couples into the receiver through the power supply pins can degrade device performance. See Figure 2 for an example of power supply filtering for the receiver 5 V power supply pins. ■ Use a multilayer board so that the ground plane surrounds the areas occupied by the receiver and directly under- neath it. Directly attach all pins listed as ground pins to the ground plane with no additional lead length. All unused outputs must be terminated as shown. All resistors are 1/8 W, thin-film, ceramic chips. All capacitors are 25 Vdc, ceramic X7R or equivalent. Qualification and Reliability T o help ensure high product reliability and customer satisfaction, Agere Systems is committed to an intensive qual- ity program that starts in the design phase and proceeds through the manufacturing process. Optoelectronics mod- ules are qualified to Agere Systems internal standards using MIL-STD-883 test methods and procedures and using sampling techniques consistent with Telcordia T echnologies requirements. The 1345 series of receivers have undergone an extensive and rigorous set of qualification tests. This qualification program fully meets the intent of T elcordia T echnologies reliability practices TR-NWT -000468 and T A-NWT -000983. In addition, the design, develop- ment, and manufacturing facility of the Optoelectronics unit at Agere Systems is certified to be in full compliance with the latest ISO ® -9001 Quality System Standards.
9Agere Systems Inc. Data Sheet 1345-Type Receiver with January 2000 Clock Recovery and Data Retiming Outline Drawings 1-988(C) 1.339 (34.01) 0.968 (24.58) 0.635 (16.14) 0.147 (3.73) TOP VIEW PIN 1 INDICATOR 0.125 (3.17) 0.110 (2.80) 0.100 (2.54) 0.900 (22.86) 0.350 (8.89) 0.400 (10.16) PIN 20PIN 11 PIN 1PIN 10 0.018 (0.46)
10 Agere Systems Inc. 1345-Type Receiver with Data Sheet Clock Recovery and Data Retiming January 2000
Ordering Information
Table 3. OC-3/STM-1 Receiver Versions
- These versions have nonsquelching data and clock outputs. See Nonsquelched Data and Clock Outputs section on page 2.
Table 4. OC-12/STM-4 Receiver Versions
- These versions have nonsquelching data and clock outputs. See Nonsquelched Data and Clock Outputs section on page 2.
Table 5. Related Products
11Agere Systems Inc. Data Sheet 1345-Type Receiver with January 2000 Clock Recovery and Data Retiming Notes
1345-Type Receiver with D ata Sheet Clock Recovery and D ata Retiming January 2000 Agere System s Inc. reserves the right to m ake changes to the product(s) or information contained herein without notice. No liability is assum ed as a result of their use or application. ST is a registered trademark of Agere System s Inc. Co pyright © 2001 Agere System s Inc. All Rights Reserved January 2000 DS00-099O PTO (Replaces D S99-071LWP) For additional information, contact your Agere Systems Account Manager or the following: IN TERNE T: http://www .agere.com E-M AIL: docm aster@ agere.com N. AM ERICA : Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, PA 18109-3286 1-800-372-2447, FAX 610-712-4106 (In C AN ADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F, Tower 2, The Gatew ay, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 C H INA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN : (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIW AN : (886) 2-2725-5858 (Taipei) EU R OPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045 Telcordia T echnologies is a trademark of Telcordia Technologies Inc. EIA is a registered trademark of Electronic Industries Association. Signetics is a registered trademark of Signetics Corp. National Semiconductor is a registered trademark of National Semiconductor Corporation. ISO is a registered trademark of The International Organization for Standardization.