1340 AGERE | Alldatasheet
Document overview
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Technical content
Features
I Backward compatible with 1310 receiver family I Space-saving, self-contained, 20-pin plastic DIP I Silicon-based ICs I Single 5 V power supply operation including photo- current monitor capability I Exceeds all SONET (GR-253-CORE) and ITU-T G.958 jitter requirements I Wide dynamic range I Qualified to meet the intent of T elcordia T echnolo- gies * reliability practices I Operates at data rates of 155 Mbits/s, 622 Mbits/s, or 1.25 Gbits/s I Positive ECL (PECL) data outputs I CMOS (TTL) link-status flag output I Operation at 1.3 µm or 1.55 µm wavelengths I Operating case temperature range of –40 °C to +85 °C
Applications
I Telecommunications: — Inter- and intraoffice SONET/ITU-T SDH — Subscriber loop — Metropolitan area networks I High-speed data communications
Description
The 1340-T ype receiver is designed for use in trans- mission systems or medium- to high-speed data communications applications at data rates up to 1.25 Gbits/s. Compact packaging, along with wide dynamic range, makes these receivers ideal for both telecommunications and data communications appli- cations. The following three versions of the receiver are avail- able: I SONET/SDH compliant with OC-3/STM-1 I SONET/SDH compliant with OC-12/STM-4 I 1.25 Gbits for data applications. * Telcordia Technologies is a trademark of T elcordia T echnologies, Inc.
to +85 °C at the appropriate data rate for each version. nector. Other connectors are available on special order. level of optical input signal. Figure 1. Block Diagram
January 2000 1340-Type Lightwave Receiver Agere Systems Inc. 3 Description (continued) T o help ensure high product reliability and customer satisfaction, Agere is committed to an intensive quality program that starts in the design phase and proceeds through the manufacturing and shipping process. Opto- electronics subsystems are qualified to Agere internal standards using MIL-STD-883 test methods and pro- cedures and sampling techniques consistent with Te l - cordia T echnologies requirements. The 1340 receiver qualification program meets the intent of Telcordia T echnologies TR-NWT -000468 and TA-TS Y-000983.
Application Information
The 1340 receiver is a highly sensitive fiber-optic receiver. Although the data outputs are digital logic lev- els (PECL), the device should be thought of as an ana- log component. When laying out the printed-wiring board (PWB), the 1340 receiver should be given the same type of consideration one would give to a sensi- tive analog component. At a minimum, a double-sided printed-wiring board with a large component-side ground plane beneath the receiver must be used. In applications that include many other high-speed devices, a multilayer PWB is highly recommended. This permits the placement of power and ground connections on separate layers, which helps minimize the coupling of unwanted signal noise into the power supplies of the receiver. Layout Considerations A fiber-optic receiver employs a very high-gain, wide- bandwidth transimpedance amplifier. The amplifier detects and amplifies signals that are only tens of nA in amplitude. Any unwanted signal currents that couple into the receiver circuitry cause a decrease in the receiver’s sensitivity and can also degrade the perfor- mance of the receiver’s loss of signal (FLAG) circuit. T o minimize the coupling of unwanted noise into the receiver, route high-level, high-speed signals such as transmitter inputs and clock lines as far away as possi- ble from the receiver pins. If this is not possible, then the PWB layout engineer should consider interleaving the receiver signal and flag traces with ground traces in order to provide the required isolation. Noise that couples into the receiver through the power supply pins can also degrade device performance. The application schematics, Figures 3—5, show recom- mended power supply filtering that helps minimize noise coupling into the receiver. The bypass capacitors should be high-quality ceramic devices rated for RF applications. They should be surface-mount compo- nents placed as close as possible to the receiver power supply pins. The ferrite bead should have as high an impedance as possible in the frequency range that is most likely to cause problems. This will vary for each application and is dependent on the signaling frequen- cies present on the application circuit card. Surface- mount, high-impedance beads are available from sev- eral manufacturers. Data and Flag Outputs The data outputs of the 1340 receiver are driven by open-emitter NPN transistors which have an output impedance of approximately 7 Ω . Each output can pro- vide approximately 50 mA maximum output current. Due to the high switching speeds of ECL outputs, transmission line design must be used to interconnect components. To ensure optimum signal fidelity, both data outputs (DA T A and DA T A ) should be terminated identically. The signal lines connecting the data outputs to the next device should be equal in length and should have matched impedances. Controlled impedance stripline or microstrip construc- tion must be used to preserve the quality of the signal into the next component and to minimize reflections back into the receiver. Excessive ringing due to reflec- tions caused by improperly terminated signal lines makes it difficult for the component receiving these sig- nals to decipher the proper logic levels and may cause transitions to occur where none were intended. Also, by minimizing high frequency ringing due to reflections caused by improperly designed and terminated signal lines, possible EMI problems can be avoided. The applications sections in the Signetics *ECL 10K/100K Data Manual or the National Semiconductor† ECL Logic Databook and Design Guide provide excellent design information on ECL interfacing. * Signetics is a registered trademark of Signetics Corp. † National Semiconductor is a registered trademark of National Semiconductor Corporation.
155 Mbits/s version of the 1340 receiver are PECL
patible and provide both true and inverted logic levels. put can cause the FLAG output to malfunction.
- Part available from Linear T echnology Corporation of Milpitas, CA 95035.
Figure 2. Converting PECL FLAG Outputs to TTL
5 V power supply and provides raised or pseudo-ECL
also be used, but this requires a second power supply. discussed in the references previously mentioned.
- The capacitive coupling isolates and permits
data lines on the 100314 side of the coupling capacitor. † DA T A and DATA are 50 Ω impedance transmission lines; both lines can be ac- or dc-coupled into the next device. ‡ Fair-Rite Products Corporation part number 2743037447 or equivalent. 25 Vdc, ceramic X7R, or equivalent. Figure 3. Interfacing to the 155 Mbits/s 1340 Receiver
Table 1. Pin Descriptions recommended that the user not make any connections to these pin positions. FLAG indicates the presence of a valid optical signal.
1 Ground
2 Ground
3 Ground
4 Ground
5 No User Connection*
6 Ground
8 Ground
10 NIC or Optional V PIN
11 Vcc (5 V)
12 FLAG †
13 Ground
14 FLAG
15 Ground
16 Ground
17 No User Connection*
18 No User Connection*
19 No User Connection*
20 No User Connection*
January 20001340-Type Lightwave Receiver 8 Agere Systems Inc. Electrostatic Discharge Caution: This device is susceptible to damage as a result of electrostatic discharge (ESD). Take proper precautions during both handling and testing. Follow EIA* Standard EIA-625. Although protection circuitry is designed into the device, take proper precautions to avoid exposure to ESD. Agere employs a human-body model (HBM) for ESD susceptibility testing and protection-design evaluation. ESD voltage thresholds are dependent on the critical parameters used to define the model. A standard HBM (resistance = 1.5 kΩ , capacitance = 100 pF) is widely used and, therefore, can be used for comparison purposes. The HBM E SD t h r e s h o ld e st abl i s h e d f o r t h e 1 3 4 0 r e c e i v er is ± 1000 V. Receiver Processing The 1340-type receiver devices can withstand normal wave-soldering processes. The complete receiver module is not hermetically sealed; therefore, it should not be immersed in or sprayed with any cleaning solution or solvents. The process cap and fiber pigtail jacket deformation temperature is 85 °C. The receiver pins can be wave-soldered at maximum temperature of 250 °C for 10 seconds. Installation Considerations Although the receiver features a robust design, care should be used during handling. The optical connector should be kept free from dust, and the process cap should be kept in place as a dust cover when the device is not con- nected to a cable. If contamination is present on the optical connector, the use of canned air with an extension tube should remove any debris. Other cleaning procedures are identified in the technical note, Cleaning Fiber-Optic Assemblies (TN95-010LWP). * EIA is a registered trademark of Electronic Industries Association.
periods can adversely affect device reliability. Minimum and maximum values specified over operating case temperature range and end-of-life (EOL). Typical values are measured at beginning-of-life (BOL) room temperature unless otherwise noted. Table 2. Optical Characteristics
- For 1 x 10–10 BER with an optical input using a 223 – 1 pseudorandom word having a 50% average duty cycle.
Table 3. Electrical Characteristics
- Customers have the option for either a +5 V or –5 V supply.
† Measured from VCC with a 50 Ω load to (VCC – 2) V. ‡ Internally terminated CMOS output. 9001 Quality System Standards.
- ISO is a registered trademark of The International Organization for Standardization.
January 2000 1340-Type Lightwave Receiver Agere Systems Inc. 11 Outline Diagram 1-988(C) 1.339 (34.01) 0.968 (24.58) 0.635 (16.14) 0.147 (3.73) TOP VIEW PIN 1 INDICATOR 0.125 (3.17) 0.110 (2.80) 0.100 (2.54) 0.900 (22.86) 0.350 (8.89) 0.400 (10.16) PIN 20PIN 11 PIN 1PIN 10 0.018 (0.46)
1340-Type Lightwave Receiver Advance Data Sheet for OC-1,3/STM-1 January 2000 Agere Systems Inc. reserves the right to make changes to the product(s) or information contained herein without notice. No liabi lity is assumed as a result of their use or application. ST is a registered trademark of Agere Systems Inc. Copyright © 2000 Agere Systems Inc. All Rights Reserved Printed in U.S.A. January 2000 DS00-098OPTO (Replaces DS99-072LWP) For additional information, contact your Agere Systems Account Manager or the following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com N. AMERICA: Agere Systems Inc., 555 Union Boulevard, Room 30L-15P-BA, Allentown, P A 18109-3286 1-800-372-2447, FAX 610-712-4106 (In CANADA: 1-800-553-2448, FAX 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 & 3210-12, 32/F , T ower 2, The Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, FAX (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 10-6522-5566 (Beijing), (86) 755-695-7224 (Shenzhen) JAPAN: (81) 3-5421-1600 (T okyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, T AIWAN: (886) 2-2725-5858 (T aipei) EUROPE: Tel. (44) 7000 624624, FAX (44) 1344 488 045
Ordering Information
Table 4. OC-3/STM-1 Receiver Versions Table 5. OC-12/STM-4 Receiver Versions Table 6. 1.25 Gbits/s Receiver Versions Table 7. Related Products