IQE030N06NM5CG INFINEON | Alldatasheet
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OptiMOS™ 5 Power-Transistor, 60 V PG-TTFN-9-1 Features an * Optimized for synchronous rectification * 100% avalanche tested 9 + Superior thermal resistance + N-channel, normal level oo _ + Pb-free lead plating; ROHS compliant 4 at + Halogen-free according to IEC61249-2-21 Product validation Fully qualified according to JEDEC for Industrial Applications Pins Table 1 Key Performance Parameters OV. 10V) (8) @ RoHS IQEO30NO6NMSCG PG-TTFN-9-1 o3osc5 =| li Final Data Sheet 1 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V Cinfi neon IQEO30NO6NM5CG Table of Contents Final Data Sheet 2 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V nrineon IQEO30NO6NM5CG
1 Maximum ratings
at Ta=25 °C, unless otherwise specified Table 2__ Maximum ratings paramet ymeot [—taues Note /Test Condit arameter [Min. | ote / Test Condition Typ. Max. |
137 Ves=10 V, Tc=25 °C
Continuous drain current’? lo 97 A Ves=10 V, Tc=100 °C »)
21 Ves=10V, Ta=25°C, Rinsa=60°C/W'
Avalanche energy, single pulse les |e |- ([t53 mu Ip=20 A, Res=25 Q «cin at 107 Tc=25 °C Operating and storage temperature ite [ss | is fo | re cumatic category; DIN IEC 68-1:
2 Thermal characteristics
Table 3 Thermal characteristics paramet symbol Note /Test Condit arameter ymbol [Min. | jlote / Test Condition Tye. Max. | Thermal resistance, junction - case, ey bottom oc fF tw ow : Device on PCB, ° 6 cm? cooling area” row foo fom : *) Rating refers to the product only with datasheet specified absolute maximum values, maintaining case temperature as specified. For other case temperatures please refer to Diagram 2. De-rating will be required based on the actual environmental conditions. 2) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm? (one layer, 70 ym thick) copper area for drain connection. PCB is vertical in still air. 3) See Diagram 3 for more detailed information ” See Diagram 13 for more detailed information Final Data Sheet 3 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ In Ineon IQE030NO6NM5CG 3_ Electrical characteristics at Tj=25 °C, unless otherwise specified Table 4 __ Static characteristics Paramet symbol Note / Test Condit arameter ymbo! [min. | jlote / Test Condition Hyp. Drain-source breakdown voltage [Venoss 60 |- |- |v | Ves=0 V, lb=1 mA Gate threshold voltage Vos=Ves, lo=50 uA Zero gate voltage drain current lees | oe 1a yes85 vr ay Mi pat3s sc Gate-source leakage current licss [= ——«|10—s[t00. [na Voes=20 V, Vos=0 V Drain-source on-state resistance roam 33 30 Vere eee A Transconductance lo [es frz0.s (> Ss [Vos|22|/o|Ros(on)max, Ib=64 A Table 5 Dynamic characteristics Paramet yma [taut Note / Test Condit arameter [Min. | lote / Test Condition Typ. [Max Input capacitance” [Css (-__ [2900 [3800 Ves=0 V, Vos=30 V, f=1 MHz Output capacitance") [Con [= ———([600.— (780 [pF Ves=0 V, Vos=30 V, 1 MHz Reverse transfer capacitance” [Case 3765 [pe Ves=0 V, Vos=30 V, f1 MHz rcv fo ff ere ot et re a ot Table 6 _Gate charge characteristics” Paramet symbst a a Note / Test Condit arameter [Min. | lote / Test Condition Typ. [ax | Gate to source charge [as [- «42.2 |- [nC _| Voo=0 V, f0=20 A, Vos=0 to 10 V Gate charge at threshold lam (faa (- [no Voo=30 V, In=20 A, Ves=0 to 10 V Gate to drain charge” [Qe 6.8 [40.2 nC | Vo0=30 V, b=20A, Vos=0 to 10 V Switching charge [Qw [-——*[40.9_|- [nC] Vo=30 V, f0=20 A, Vos=0 to 10 V Gate charge total” la s- sa [49 |_| Voo=30 V, f=20 A, Vos=0 to 10 V Gate plateau voltage [Von (4.2 |V | Vo 80 V, f0=20 A, Vos=0 to 10 V Gate charge total, sync. FET [Quemy |- *(35 (= nc Vos=0.1 V, Ves=0 to 10 V ” Defined by design. Not subject to production test. 2) See "Gate charge waveforms” for parameter definition Final Data Sheet 4 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ In ineon IQE030NO6NM5CG Table 7 Reverse diode paramet symbol Note / Test Conditi arameter ymbo lote / Test Condition [min. [Typ [Max._| Diode continuous forward current re ee ee ee Tc=25 °C Diode forward voltage [Vos |- «0.82 |4.2 —|V__| Vas=0 V, =20 A, Ti=25 °C Reverse recovery time” lt |- ‘(31 fez_—s|ns_| Va=30 V, Ir=20 A, die/dt=100 A/us Reverse recovery charge") la «Fs [26 [52 [nc Vp=30 V, Ir=20 A, dic/dt=100 A/us ‘) Defined by design. Not subject to production test. Final Data Sheet 5 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ In fi neon IQEO30NO6NM5CG
4 Electrical characteristics diagrams
“ a “ a a eS | a
400 Xr 120 rr rr
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© opeeeremscaen Senate |* CAPT TI TIE Il 40° Nill ZAC co _—— TT SS TE TE TTT Tc AR yor ——L LIU TET 10? 10° 10° 10° 10? 10° 10+ 10° 10? 107 10° Vos [V] t Is] Final Data Sheet 6 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ In ineon IQEO30NO6NM5CG Diagram 5: Typ. output characteristics Diagram 6: Typ. drain-source on resistance SEER ESEEEEEEEEEEee | ECPEPEPEEEEEEEEEEEEEEEEE HEE ———t I SSS008/ 0 oe EEE EEE / 7 CPP Ae Po 2 soot {itt tf fev yrr errr errr errr COCO’ vi COCOA ZC / te SSeS 4s EEE AAA COZ ERE LEE LLL COZ eee y See
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200 AT ee EEC
i | YA AE CECE CACC CCE EEE EEE | Ss / GS |
100 Cee ee RES Se
RSS | fy 4000 2 | 0 1 2 3 4 5 0 40 80 120 160 200 240 280 Vos [V] Io IA] To=F(Vos), T}=25 °C; parameter: Ves Rosten)=(lo), T=25 °C; parameter: Ves Diagram 7: Typ. transfer characteristics Diagram 8: Typ. drain-source on resistance 600 7 HEREC tes i ee a ee Frerrrrreerererit ttt etrterteceeel soo +H eee 2 COC CEE Ss | ECE ECE Eee SCE) Bas *¢ 20S ee SEER R EERE SCE EEE EEE recA eee SS Cee) goo EECCA Y SU Oe ie LT TTT TTT rr trey tr ett At TT EECEPECC CPE LT YP TP yyy ry yr 175 ct SS ee im eo Ae 12 | poy se seu sese caus seasasessee/ 270s EMM nu Gage UuueGeua\\'eeeeeSSEEe 2 ee ee a 3 RR ee é 2 ee ESS ee ee ee Frerrrrreereeeeelei Meee 200 eee Se ee oe HEEL EEA eo ee 2S te ee HEE EEC EEE EEL ey a HEE EEE CEE EEE CEE Pe SSeS eee Oe ee, a LTP Pe Pere eee eee ECE a COCO a
9 SOOCCCCCC ee eee 9 SECC eee ee eee)
0 4 2 3 4 5 6 7 0 2 4 6 8 10 Ves [V] Ves [V] Io=f( Ves), |Vos|>2|/o|Ros(onymax; parameter: 7; Rosjon)=f(Ves), /o=20 A; parameter: Tj Final Data Sheet 7 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ In fi neon IQEO30NO6NM5CG 2.0 3.5 COO q COCCCeCeeeeeeeee HUTTE COCOA petanel i LLCS 3.0 ~ J ve LOTTE re LEENA CELE COPE BNO se COCO es}: PINWINY {2) Yy 5 KIN
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2 Pere eee N
§ Cree CE J € LETT 1.0 POPPE EET oe EECEEEEECCCCCCC ee Toe | OT COCCCeCEPEeeee ee STAAL | COCCCeCEPEeeee ee oo LELEEEEEPE eee] | yg FEL -80 -40 0 0. rer 120 160 200 -80 -40 0 oO. rer 120 160 200 Sees | ° CePrr rrr errr eer eee eee eee) irene CEPT [}--- 175°C rrr rye ye er ere t | ST []-++++ 175 °C, max HPT eer tT SSH HH RRNUHUUUOEORORERRDD COZ OHEOL ee ATTN) | LT ERE EEEE EEE ES EEE EEE EEE EE EEE EH FREER EEE EE EEE EEE AEE EEE FREER EERE RREE EERE EERE EE FERRER EEE EERE BARA E EEE WER eee eee. —H ee eee eee Cc AREER EEE EEE _ Ee Oe ee & CN TET (Tt) je LEP a tT 9° REET HEHE = CTT eT TUN}. LO eT COP rer rr ine re rere eee ee ee Bei ee bee COTTA Ee Be ee eee ee ee LPP eT COE ers PE CEE ET a) vo ALLE), LETTE ET Vos [V] Vso [V] Final Data Sheet 8 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ In fi neon IQEOZONOGNMSCG Diagram 13: Avalanche characteristics Diagram 14: Typ. gate charge 1 nn es 10 eo y — | [7 2, | — W224 a a | —-30V rere eee Li AY LLL a a | a a So / COTATI ITI) EEE EEE EH a ~~ SE Re ee NU pel NI COCeCCCeCCecy eee) . Me NL DNesec COC CCC eer 8 "Sr SOC ECCCC CC > a A OS S FLCELLL ELLE va CECE) eg a | 2 | UTA TTTIINS ETT] ECR NY atti reer ee aN LTT TTA TTT ee ee 10? — FE NY SSSSP AS a y a ott WOT eee a a COAT TTT | HALAS LVTT TTT Tr ery ey er 10° rp 48 ee 10° 10° 10? 10° 0 10 20 30 40 50 tay [us] Qgate [nC] Ins=f(tav); Res=25 Q; parameter: Tsar Ves=f(Qgate), 1o=20 A pulsed, T;=25 °C; parameter: Voo Diagram 15: Drain-source breakdown voltage Diagram Gate charge waveforms 85 eee COA ECC EEECC CCC
64 GOOCCECE EEE Vos
EERE CCC eCard Q,
63 EECCCCCE EEE
62 EEOC Eee eee
-_ ey a Ss A gg GOECCECCEE eee 3 Oe g Soe, & ey
60 HECECEEE
59 EEOCCE CECE
88 CECE Pom | | Qa Q gate
67 SECC eee eee ee Polo | Qye
TLC) Verse Ty, het mA Cy Final Data Sheet 9 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ Infi neon IQEOSONOGNMSCG
5 Package Outlines
[=| [0] ot [=| - ~ [8] 2 A pa Ss E Bloke) Fo boo tot = TH 5 + A T — a | Hla tT SEO) TT Uti be 4 21011) wioex marine Al - STAN OFF [el b 8x [6]o1@[a[e[c] [meson [| a a Yo a [ea SCALE 10:1 Keer ee 0 1 2mm a Usui a EUROPEAN PROJECTION a ; [et 0305 a XC Ke [a 073 08 08.11.2019 Figure 1 Outline PG-TTFN-9-1, dimensions in mm Final Data Sheet 10 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V | n fi neon IQEOQZONOGNMSCG Infineon 0.15 0.35 a 8x 1.059 0.595 be = | | o97s os sig lag ana, T lalb— Yi) oe AAI: AMPLE) Pint 0.65, 14 4x 0.365 oss looa Fa oars _|osis || ‘copper solder mask stencil apertures All dimensions are in units mm Figure 2 Outline Boardpad (PG-TTFN-9-1), dimensions in mm Final Data Sheet 11 Rev. 2.0, 2021-04-27
OptiMOS™ 5 Power-Transistor, 60 V ¢ | nrineon IQEO30NO6NMSCG
Revision History
Revision: 2021-04-27, Rev. 2.0 Previous Revision Revision [Date __| Subjects (major changes since last revision) 2.0 2021-04-27 | Release of final version Trademarks All referenced product or service names and trademarks are the property of their respective owners We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: erratum@infineon.com Published by Infineon Technologies AG
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