SLG46169

SLG46169 RENESAS

Document overview

• Manufacturer or author: Provided By www.digicamel.com(free datasheet download site)
• PDF pages: 103

Technical content

Features

• Logic & Mixed Signal Circuits
• Highly Versatile Macrocells
• Read Back Protection (Read Lock)
• 1.8 V (±5%) to 5 V (±10%) Supply
• Operating Temperature Range: -40°C to 85°C
• RoHS Compliant / Halogen-Free
• 14-pin STQFN: 2 x 2.2 x 0.55 mm, 0.4 mm pitch

Applications

• Personal Computers and Servers
• PC Peripherals
• Consumer Electronics
• Data Communications Equipment
• Handheld and Portable Electronics Pin Configuration GND GPIO GPIO GPIO GPIO 4 9 GPI VDD 1 14-pin STQFN (Top View) GPIO GPIO 6 7 14 13 GPIO GPIO GPIO GPIO GPIO 5 3-bit LUT3_8 or Pipe Delay Vref Programmable Delay RC Oscillator Pin 5 GPIO Pin 1 VDD Pin 2 GPI Pin 3 GPIO Pin 4 GPIO Pin 14 GPIO Pin 13 GPIO Pin 6 GPIO Pin 7 GPIO Pin 8 GPIO Pin 12 GPIO Pin 11 GPIO Pin 10 GPIO Pin 9 GND INV_0 ACMP0 ACMP1 FILTER_0 INV_1 Additional Logic Functions Look Up Tables (LUTs) Counters/Delay Generators CNT0 CNT4 CNT1 CNT5 CNT6 2-bit LUT2_4 3-bit LUT3_0 2-bit LUT2_5 3-bit LUT3_1 3-bit LUT3_5 3-bit LUT3_4 3-bit LUT3_6 3-bit LUT3_9 3-bit LUT3_7 Combination Function Macrocells 2-bit LUT2_0 or DFF4 2-bit LUT2_2 or DFF6 2-bit LUT2_1 or DFF5 2-bit LUT2_3 or DFF7 3-bit LUT3_3 or DFF3 3bit LUT3_2 or DFF2 4-bit LUT4_1 or CNT3 4-bit LUT4_0 or CNT2 FILTER_1

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1.0 Overview

The SLG46169 provides a small, low power component for commonly used mixed-signal functions. The user creates their circuit design by programming the one time Non-Volatile Mem ory (NVM) to configure the interconnect logic, the I/O Pins and the macrocells of the SLG46169. This highly versatile device allows a wide variety of mixed-signal functions to be designed within a very small, low power single integrated circuit. The macrocells in the device include the following:

• Two Analog Comparators (ACMP)
• Two Voltage References (Vref)
• Nine Combinatorial Look Up Tables (LUTs)
• Two 2-bit LUTs
• Seven 3-bit LUTs
• Nine Combination Function Macrocells
• Four Selectable DFF/Latch or 2-bit LUTs
• Two Selectable DFF/Latch or 3-bit LUTs
• One Selectable Pipe Delay or 3-bit LUT
• Two Selectable CNT/DLY or 4-bit LUTs
• Five Counter / Delay Generators (CNT/DLY)
• One 14-bit delay/counter
• One 14-bit delay/counter with external clock/reset
• Three 8-bit delays/counters
• Pipe Delay – 16 stage/3 output (Part of Combinatio n Function Macrocell)
• Programmable Delay
• Additional Logic Functions – 2 Inverters / 2 Degli tch Filters
• RC Oscillator (RC OSC)

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2.0 Pin Description

2.1 Functional and Programming Pin Description

Pin # Pin Name Function Programming Function

1 VDD Power Supply Power Supply

2 GPI General Purpose Input VPP (Programming Voltage)

3 GPIO General Purpose I/O N/A

4 GPIO General Purpose I/O with OE N/A

5 GPIO General Purpose I/O or Analog Comparator 0 (+) N/A

6 GPIO General Purpose I/O with OE or Analog Comparat or 0 (-) N/A

7 GPIO General Purpose I/O with OE N/A

8 GPIO General Purpose I/O or Analog Comparator 1 (+) N/A

9 GND Ground Ground

10 GPIO General Purpose I/O with OE Programming Mode C ontrol

11 GPIO General Purpose I/O Programming ID Pin

12 GPIO General Purpose I/O with OE Programming SDIO P in

13 GPIO General Purpose I/O with OE and Vref output ( VREF) Programming SRDWB Pin

14 GPIO General Purpose I/O or External Clock Input Pr ogramming SCL Pin

3.0 User Programmability

will remain active on the device as long as it remains powered and can be re-written as needed to facilitate rapid design changes. Figure 1. Steps to create a custom Renesas Electronics Corporation GreenPAK device

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4.0 Ordering Information

Note 1: Use SLG46169V to order. Shipments are automatically in Tape and Reel. Note 2: “TR” suffix is no longer used. It is a legacy naming convention shown here only for informational purposes. Part Number Type SLG46169V 14-pin STQFN SLG46169VTR 14-pin STQFN - Tape and Reel (3k units)

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5.0 Electrical Specifications

5.1 Absolute Maximum Conditions

5.2 Electrical Characteristics (1.8 V ±5% V DD ) Parameter Min. Max. Unit Supply voltage on VDD relative to GND -0.5 7 V DC Input voltage GND - 0.5 VDD + 0.5 V Maximum Average or DC Current (Through pin) Push-Pull 1x -- 8 mA Push-Pull 2x -- 10 OD 1x -- 8 OD 2x -- 12 OD 4x -- 25 Current at Input Pin -1.0 1.0 mA Storage Temperature Range -65 150 °C Junction Temperature -- 150 °C ESD Protection (Human Body Model) 2000 -- V ESD Protection (Charged Device Model) 1300 -- V Moisture Sensitivity Level 1 Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 1.71 1.80 1.89 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.1 V VIH HIGH-Level Input Voltage Logic Input 1.100 -- -- V Logic Input with Schmitt Trigger 1.270 -- -- V Low-Level Logic Input 0.980 -- -- V V IL LOW-Level Input Voltage Logic Input -- -- 0.690 V Logic Input with Schmitt Trigger -- -- 0.440 V Low-Level Logic Input -- -- 0.520 V I LKG Input Leakage (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage Push-Pull 1X, Open Drain PMOS 1X, I OH = 100 µA 1.690 1.789 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 100 µA 1.700 1.794 -- V

000-0046169-111 Page 6 of 101 SLG46169 VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 100 µA -- 0.008 0.030 V Push-Pull 2X, I OL = 100 µA -- 0.004 0.010 V Open Drain NMOS 1X, I OL = 100 µA -- 0.005 0.020 V Open Drain NMOS 2X, I OL = 100 µA -- 0.003 0.010 V Open Drain NMOS 4X, I OL = 100 µA -- 0.003 0.004 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = V DD - 0.2 V 1.066 1.703 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = V DD - 0.2 V 2.216 3.406 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.15 V 0.917 1.689 -- mA Push-Pull 2X, V OL = 0.15 V 1.834 3.378 -- mA Open Drain NMOS 1X, V OL = 0.15 V 1.375 2.534 -- mA Open Drain NMOS 2X, V OL = 0.15 V 2.750 5.068 -- mA Open Drain NMOS 4X Drive, V OL = 0.15 V 5.500 10.136 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.3 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V RPUP Pull Up Resistance

1 M Pull Up -- 1 -- M Ω

100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance

1 M Pull Down -- 1 -- M Ω

100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

000-0046169-111 Page 7 of 101 SLG46169 5.3 Electrical Characteristics (3.3 V ±10% V DD ) Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 3.0 3.3 3.6 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 1.780 -- -- V Logic Input with Schmitt Trigger 2.130 -- -- V Low-Level Logic Input 1.130 -- -- V V IL LOW-Level Input Voltage Logic Input -- -- 1.210 V Logic Input with Schmitt Trigger -- -- 0.950 V Low-Level Logic Input -- -- 0.690 V I LKG Input Leakage (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 3 mA 2.735 3.120 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 3 mA 2.870 3.210 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 3 mA -- 0.130 0.228 V Push-Pull 2X, I OL = 3 mA -- 0.060 0.108 V Open Drain NMOS 1X, I OL = 3 mA -- 0.080 0.147 V Open Drain NMOS 2X, I OL = 3 mA -- 0.040 0.080 V Open Drain NMOS 4X, I OL = 3 mA -- 0.027 0.034 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 6.045 12.080 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 11.522 24.160 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 4.875 8.244 -- mA Push-Pull 2X, V OL = 0.4 V 9.750 16.488 -- mA Open Drain NMOS 1X, V OL = 0.4 V 7.313 12.370 -- mA Open Drain NMOS 2X, V OL = 0.4 V 14.541 24.740 -- mA Open Drain NMOS 4X Drive, V OL = 0.4 V 25.801 49.480 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T

000-0046169-111 Page 8 of 101 SLG46169 IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.3 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

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5.4 Electrical Characteristics (5 V ±10% V DD )

Symbol Parameter Condition/Note Min. Typ. Max. Unit VDD Supply Voltage 4.5 5.0 5.5 V TA Operating Temperature -40 25 85 °C VPP Programming Voltage 7.25 7.50 7.75 V VACMP ACMP Input Voltage Range Positive Input 0 -- V DD V Negative Input 0 -- 1.2 V VIH HIGH-Level Input Voltage Logic Input 2.640 -- -- V Logic Input with Schmitt Trigger 3.160 -- -- V Low-Level Logic Input 1.230 -- -- V V IL LOW-Level Input Voltage Logic Input -- -- 1.840 V Logic Input with Schmitt Trigger -- -- 1.510 V Low-Level Logic Input -- -- 0.780 V I LGK Input leakage (Absolute Value) -- 1 1000 nA V OH HIGH-Level Output Voltage Push-Pull 1X,Open Drain PMOS 1X, I OH = 5 mA 4.190 4.780 -- V Push-Pull 2X, Open Drain PMOS 2X, I OH = 5 mA 4.320 4.890 -- V VOL LOW-Level Output Voltage Push-Pull 1X, I OL = 5 mA -- 0.157 0.270 V Push-Pull 2X, I OL = 5 mA -- 0.076 0.130 V Open Drain NMOS 1X, I OL = 5 mA -- 0.102 0.180 V Open Drain NMOS 2X, I OL = 5 mA -- 0.051 0.110 V Open Drain NMOS 4X, I OL = 5 mA -- 0.035 0.045 V IOH HIGH-Level Output Current (see Note 1) Push-Pull 1X, Open Drain PMOS 1X, V OH = 2.4 V 22.080 34.040 -- mA Push-Pull 2X, Open Drain PMOS 2X, V OH = 2.4 V 41.690 68.080 -- mA IOL LOW-Level Output Current (see Note 1) Push-Pull 1X, V OL = 0.4 V 7.215 11.580 -- mA Push-Pull 2X, V OL = 0.4 V 13.831 23.160 -- mA Open Drain NMOS 1X, V OL = 0.4 V 10.820 17.380 -- mA Open Drain NMOS 2X, V OL = 0.4 V 17.343 34.760 -- mA Open Drain NMOS 4X Drive, V OL = 0.4 V 30.964 69.520 -- mA IVDD Maximum Average or DC Current Through VDD Pin (Per chip side, see Note 2) T

000-0046169-111 Page 10 of 101 SLG46169 IGND Maximum Average or DC Current Through GND Pin (Per chip side, see Note 2) T TSU Startup Time from VDD rising past 1.35 V -- 0.3 -- ms PON THR Power On Threshold V DD Level Required to Start Up the Chip 1.180 1.353 1.516 V POFF THR Power Off Threshold VDD Level Required to Switch Off the Chip 0.730 0.914 1.103 V RPUP Pull Up Resistance 100 k Pull Up -- 100 -- k Ω 10 k Pull Up -- 10 -- k Ω RPDWN Pull Down Resistance 100 k Pull Down -- 100 -- k Ω 10 k Pull Down -- 10 -- k Ω Note 1: DC or average current through any pin should not exceed value given in Absolute Maximum Conditions. Note 2: The GreenPAK’s power rails are divided in two sides. Pins 2, 3, 4, 5, 6, 7 and 8 are connected to one side, pins 10, 11, 12, 13 and 14 to another. Symbol Parameter Condition/Note Min. Typ. Max. Unit

5.5 IDD Estimator

5.6 Timing Estimator

Table 1. Typical Current estimated for each macrocell Table 2. Typical Delay estimated for each macrocell

5.7 Typical Counter/Delay Offset Measurements

5.8 Expected Delays and Widths

Table 3. Typical Counter/Delay Offset Measurements Table 4. Expected Delays and Widths for Programmable Delay (typical)

5.9 Typical Pulse Width Performance

5.10 OSC Specifications

Table 5. Typical Pulse Width Performance Table 6. 25 kHz RC OSC frequency limits Table 7. 25 kHz RC OSC frequency error (error calculated relative to nominal value)

Table 8. 2 MHz RC OSC frequency limits Table 9. 2 MHz RC OSC frequency error (error calculated relative to nominal value)

5.10.2 OSC Power On delay

Table 10. Oscillators Power On delay at T=(-40..+85) °C, DLY/CNT Counter data = 100; RC OSC power setting: "Auto

5.11 ACMP Specifications

Table 11. ACMP Specifications

000-0046169-111 Page 17 of 101 SLG46169 Rsin Series Input Resistance Gain = 1x -- 100.0 -- ΜΩ Gain = 0.5x -- 1.0 -- ΜΩ Gain = 0.33x -- 0.8 -- ΜΩ Gain = 0.25x -- 1.0 -- ΜΩ PROP Propagation Delay, Response Time Low Bandwidth - Disable, Gain = 1, VDD=(1.71..3.3)V, Overdrive=2 mV Low to High, T = 25°C -- 2.87 5.69 µS High to Low, T = 25°C -- 2.79 5.12 µS G Gain error (including threshold and internal Vref error), T = (-40…+85)°C G = 1, Vref = (50…1200) mV -- 1 -- G = 0.5, G = 0.33, G = 0.25, Vref Internal Vref error, Symbol Parameter Description/Note Conditions Min. Typ. Max. Unit

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6.0 Summary of Macrocell Function

6.1 I/O Pins

• Digital Input (low voltage or normal voltage, with or without Schmitt Trigger)
• Open Drain Outputs
• Push Pull Outputs
• Analog I/O
• 10 k Ω /100 k Ω /1 M Ω pull-up/pull-down resistors
• 40 mA Open Drain 4X Drive output

6.2 Connection Matrix

• Digital matrix for circuit connections based on us er design

6.3 Analog Comparators (2 total)

• Selectable hysteresis 0 mV/25 mV/50 mV/200 mV
• Bandwidth control
• Selectable gain

6.4 Voltage Reference

• Used for references on Analog Comparators
• Can also be driven to external pins

6.5 Combinational Logic Look Up Tables (LUTs – 9 total)

• Two 2-bit Lookup Tables
• Seven 3-bit Lookup Tables

6.6 Combination Function Macrocells (9 total)

• Four Selectable DFF/Latch or 2-bit LUTs
• Two Selectable DFF/Latch or 3-bit LUTs
• One Selectable Pipe Delay or 3-bit LUT
• Two Selectable CNT/DLY or 4-bit LUTs

6.7 Delays/Counters (5 total)

• Two 14-bit delay/counters: Range 1-16384 clock cyc les
• Three 8-bit delays/counters: Range 1-255 clock cyc les

6.8 Pipe Delay (Part of Combination Function Macrocell)

• 16 stage / 3 output
• One 1 stage fixed output
• Two 1-16 stage selectable outputs.

6.9 Programmable Delay

• 150 ns/300 ns/450 ns /600 ns @ 3.3 V
• Includes Edge Detection function

6.10 Additional Logic Functions (4 total)

• Two Inverter macrocells
• Two Deglitch filter macrocells

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6.11 RC Oscillator

• 25 kHz and 2 MHz selectable frequency
• First stage divider (4): OSC/1, OSC/2, OSC/4, and OSC/8
• Second stage divider (5): OSC/1, OSC/4, selectable (OSC/8, OSC/12, OSC/24, or OSC/64), OSC/3, and additional OSC/3 (from selectable output)

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7.0 I/O Pins

The SLG46169 has a total of 12 multi-function I/O p ins which can function as either a user defined Inp ut or Output, as well as serving as a special function (such as outputting t he voltage reference), or serving as a signal for p rogramming of the on-chip Non Volatile Memory (NVM). Normal Mode pin definitions are as follows:

• Pin 1: V DD power supply
• Pin 2: general purpose input
• Pin 3: general purpose input or output
• Pin 4: general purpose input or output with OE
• Pin 5: general purpose input or output or analog c omparator 0(+)
• Pin 6: general purpose input or output with OE or analog comparator 0(-)
• Pin 7: general purpose input or output with OE
• Pin 8: general purpose input or output or analog c omparator 1(+)
• Pin 9: ground
• Pin 10: general purpose input or output with OE
• Pin 11: general purpose input or output
• Pin 12: general purpose input or output with OE
• Pin 13: general purpose input or output with OE an d Vref output (VREF)
• Pin 14: general purpose input or output or externa l clock input Programming Mode pin definitions are as follows:
• Pin1: V DD power supply
• Pin 2: V PP programming voltage
• Pin 9: ground
• Pin 10: programming mode control
• Pin 11: programming ID pin
• Pin 12: programming SDIO pin
• Pin 13: programming SRDWB pin
• Pin 14: programming SCL pin Of the 12 user defined I/O pins on the SLG46169, all but one of the pins (Pin 2) can serve as both digital input and digital output. Pin 2 can only serve as a digital input pin.

7.1 Input Modes

Each I/O pin can be configured as a digital input p in with/without buffered Schmitt Trigger, or can al so be configured as a low voltage digital input. Pins 5, 6 and 8 can also be configured to serve as analog inputs to the on-chip comparators. Pins 12 and 13 can also be configured as analog reference voltage outputs.

7.2 Output Modes

Pins 3, 4, 5, 6, 7, 8, 10, 11, 12, 13 and 14 can all be configured as digital output pins.

7.3 Pull Up/Down Resistors

All I/O pins have the option for user selectable resistors connected to the input structure. The selectable values on these resistors are 10 k Ω , 100 k Ω and 1 M Ω . In the case of Pin 2, the resistors are fixed to a pull-down configuration. In the case of all other I/O pins, the internal resistors can be configured as either pull-up or pull-downs.

7.4 I/O Register Settings

7.4.1 PIN 2 Register Settings

Table 12. PIN 2 Register Settings

7.4.2 PIN 3 Register Settings

7.4.3 PIN 4 Register Settings

Table 13. PIN 3 Register Settings Table 14. PIN 4 Register Settings

7.4.4 PIN 5 Register Settings

7.4.5 PIN 6 Register Settings

7.4.6 PIN 7 Register Settings

Table 15. PIN 5 Register Settings Table 16. PIN 6 Register Settings Table 17. PIN 7 Register Settings

7.4.7 PIN 8 Register Settings

7.4.8 PIN 10 Register Settings

Table 18. PIN 8 Register Settings Table 19. PIN 10 Register Settings

7.4.9 PIN 11 Register Settings

7.4.10 PIN 12 Register Settings

Table 20. PIN 11 Register Settings Table 21. PIN 12 Register Settings

7.4.11 PIN 13 Register Settings

7.4.12 PIN 14 Register Settings

Table 22. PIN 13 Register Settings Table 23. PIN 14 Register Settings

7.5 GPI Structure

7.5.1 GPI Structure (for Pin 2)

Figure 2. PIN 2 GPI Structure Diagram

7.6 Matrix OE IO Structure

7.6.1 Matrix OE IO Structure (for Pins 4, 6, 7, 10, 12, 13)

Figure 3. Matrix OE IO Structure Diagram

7.7 Register OE IO Structure

7.7.1 Register OE IO Structure (for Pins 3, 5, 11, 14)

Figure 4. Register OE IO Structure Diagram

7.8 Register OE IO Structure with 4X Drive

7.8.1 Register OE IO Structure with 4X Drive (for Pin 8)

Figure 5. Register OE IO with 4X Drive Structure Diagram

8.0 Connection Matrix

macrocell uses a 6-bit register to select one of these 64 input lines. Figure 6. Connection Matrix

8.1 Matrix Input Table

Table 24. Matrix Input Table

0 GND 0 0 0 0 0 0

2 Reserved 0 0 0 0 1 0

7 Reserved 0 0 0 1 1 1

10 ACMP_0 output 0 0 1 0 1 0

11 ACMP_1 output 0 0 1 0 1 1

12 Reserved 0 0 1 1 0 0

13 CNT_DLY0(14bit) output 0 0 1 1 0 1

14 CNT_DLY1(14bit with ext CK/Reset) output 0 0 1 1 1 0

15 CNT_DLY4(8 bit) output 0 0 1 1 1 1

16 CNT_DLY5(8 bit) output 0 1 0 0 0 0

17 CNT_DLY6(8 bit) output 0 1 0 0 0 1

18 Reserved 0 1 0 0 1 0

19 Inverting of DFF/LATCH_2 output 0 1 0 0 1 1

20 GND (spare) 0 1 0 1 0 0

21 Inverting of DFF/LATCH_3 output 0 1 0 1 0 1

22 LUT4_0 output (CNT_DLY2 output (8 bit w/ ext CK a nd reset)) 0 1 0 1 1 0

23 LUT4_1 output (CNT_DLY3 output (8 bit w/ ext CK a nd reset)) 0 1 0 1 1 1

24 LUT3_0 output 0 1 1 0 0 0

25 LUT3_1 output 0 1 1 0 0 1

26 LUT3_2 output (DFF/LATCH_2 output with nRST or nS ET) 0 1 1 0 1 0

27 LUT3_3 output (DFF/LATCH_3 output with nRST or nS ET) 0 1 1 0 1 1

28 LUT3_4 output 0 1 1 1 0 0

29 LUT3_5 output 0 1 1 1 0 1

30 LUT3_6 output 0 1 1 1 1 0

31 LUT3_7 output 0 1 1 1 1 1

32 LUT3_8 output(1st stage pipe 1 delay output) 1 0 0 0 0 0

33 LUT2_0 output (DFF/LATCH_4 output) 1 0 0 0 0 1

34 LUT2_1 output (DFF/LATCH_5 output) 1 0 0 0 1 0

35 LUT2_2 output (DFF/LATCH_6 output) 1 0 0 0 1 1

36 LUT2_3 output (DFF/LATCH_7 output) 1 0 0 1 0 0

37 LUT2_4 output 1 0 0 1 0 1

38 LUT2_5 output 1 0 0 1 1 0

39 LUT3_9 output 1 0 0 1 1 1

43 Edge detect output 1 0 1 0 1 1

44 Programmable delay with edge detector output 1 0 1 1 0 0

50 Reserved 1 1 0 0 1 0

51 Reserved 1 1 0 0 1 1

52 Reserved 1 1 0 1 0 0

53 Reserved 1 1 0 1 0 1

62 Resetb_core (POR) as matrix input 1 1 1 1 1 0

63 VDD 1 1 1 1 1 1

8.2 Matrix Output Table

Table 25. Matrix Output Table

9.0 Combinatorial Logic

Section 10.0 Combination Function Macrocells . devices (AND, NAND, OR, NOR, XOR, XNOR). created within each of the two 2-bit LUT logic cells. Figure 7. 2-bit LUTs Table 28. 2-bit LUT Standard Digital Functions Table 26. 2-bit LUT4 Truth Table Table 27. 2-bit LUT5 Truth Table

Figure 8. 3-bit LUTs

Table 29. 3-bit LUT0 Truth Table Table 30. 3-bit LUT1 Truth Table Table 31. 3-bit LUT4 Truth Table Table 32. 3-bit LUT5 Truth Table. Table 33. 3-bit LUT6 Truth Table. Table 34. 3-bit LUT7 Truth Table. Table 35. 3-bit LUT9 Truth Table.

created within each of the six 3-bit LUT logic cells. Table 36. 3-bit LUT Standard Digital Functions.

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10.0 Combination Function Macrocells

The SLG46169 has nine combination function macrocel ls that can serve more than one logic or timing fun ction. In each case, they can serve as a Look Up Table (LUT), or as another logic or timing function. See the list below fo r the functions that can be implemented in these macrocells;

• Four macrocells that can serve as either 2-bit LUT s or as D Flip Flops.
• Two macrocells that can serve as either 3-bit LUTs or as D Flip Flops.
• One macrocell that can serve as either 3-bit LUT o r as Pipe Delay
• Two macrocells that can serve as either 4-bit LUTs or as 8-Bit Counter / Delays Inputs/Outputs for the nine combination function macrocells are configured from the connection matrix with specific logic functions being defined by the state of NVM bits. When used as a LUT to implement combinatorial logic functions, the outputs of the LUTs can be configured to any user defined function, including the following standard digital logic devices (AND, NAND, OR, NOR, XOR, XNOR, Inver ter, Buffer and MUX for 3-bit and 4-bit LUTs). When used as a D Flip Flop / Latch, the source and destination of the inputs and outputs for the DFF/Latches are configured from the connection matrix. All DFF/Latch macrocells have user selection for initial state, and all have th e option to connect both the Q and Q Bar outputs to the connection matrix. The m acrocells DFF2, DFF3 have an additional input from the matrix that can serve as a nSet or nReset function to the macrocell. The operation of the D Flip-Flop and Latch will follow the functional descriptions below: DFF: CLK is rising edge triggered, then Q = D; otherwise Q will not change Latch: if CLK = 0, then Q = D 10.1 2-Bit LUT or D Flip Flop Macrocells There are four macrocells that can serve as either 2-bit LUTs or as D Flip Flops. When used to implement LUT functions, the 2-bit LUTs each take in two input signals from the connection matrix and produce a single output, which goes back into the connection

Table 41. 2-bit LUT Standard Digital Functions Table 37. 2-bit LUT0 Truth Table. Table 38. 2-bit LUT1 Truth Table. Table 39. 2-bit LUT2 Truth Table. Table 40. 2-bit LUT3 Truth Table.

Table 42. DFF4 Register Settings Table 43. DFF5 Register Settings Table 44. DFF6 Register Settings Table 45. DFF7 Register Settings

Table 48. DFF2 Register Settings Table 49. DFF3 Register Settings Table 46. 3-bit LUT2 Truth Table. Table 47. 3-bit LUT3 Truth Table.

There is one macrocell that can serve as either a 3-bit LUT or as a Pipe Delay. single output, which goes back into the connection matrix. by reg <666:663> for OUT0 and reg <670:667> for OUT1. The 4-input mux is used to control the selection of the amount of delay. be the total time delay of the Pipe Delay logic cell. Figure 15. 3-bit LUT8 or Pipe Delay

16 Flip-Flops IN

Table 51. 3-bit LUT Standard Digital Functions Table 52. Pipe Delay Register Settings Table 50. 3-bit LUT8 Truth Table.

connection matrix. For timing diagrams refer to section 13.1 CNT/DLY Timing Diagrams . Figure 16. 4-bit LUT0 or CNT/DLY2

Figure 17. 4-bit LUT1 or CNT/DLY3

Table 55. 4-bit LUT Standard Digital Functions. Table 53. 4-bit LUT0 Truth Table. Table 54. 4-bit LUT1 Truth Table.

Table 56. CNT/DLY2 Register Settings Table 57. CNT/DLY3 Register Settings

11.0 Analog Comparators (ACMP)

coming from the Connection Matrix. When ACMP is powered down, output is low. either created from an internal VREF or provided by way of the external sources. PWR UP = 1 => ACMP is powered up. PWR UP = 0 => ACMP is powered down. Bandwidth option enabled, then the ACMP output initializes in the high state. Vref accuracy is optimized near 1000 mV selection. use Vref selection VDD/4 and VDD/3 to maintain this input range. use the input buffer when the gain divider is not used. . Note: the input buffer gain depends on VDD, see Figure 19. . Figure 18. Maximum Analog Buffer Input Voltage vs. VDD

signals are input into the analog comparator. frequency > 200 kHz, the output will retain its previous value. Enabling the Analog buffer will influence the ACMP response time. Note that power supply control options have influence on Analog macrocells operation. Each cell also has a hysteresis selection, to offer hysteresis of 0 mV, 25 mV, 50 mV or 200 mV. Hysteresis: Input signal hysteresis options are disable, 25mV, 50mV, 200mV. Figure 19. Input Buffer Gain Error vs. VDD

11.1 ACMP0 Block Diagram

Figure 20. ACMP0 Block Diagram

11.2 ACMP0 Register Settings

Table 58. ACMP0 Register Settings

11.3 ACMP1 Block Diagram

Figure 21. ACMP1 Block Diagram

11.4 ACMP1 Register Settings

Table 59. ACMP1 Register Settings

12.0 Digital Storage Elements (DFFs/Latches)

of this Combination Function macrocell.

12.1 Initial Polarity Operations

Figure 22. DFF Polarity Operations

13.0 Counters/Delay Generators (CNT/DLY)

CNT/DLY macrocell, to implement longer count / delay circuits. more information please see Section 10.4 4-Bit LUT or 8- Bit Counter / Delay Macrocells. Figure 23. CNT/DLY0

13.1 CNT/DLY Timing Diagrams

Figure 28. Delay Mode Timing Figure 29. Counter Mode Timing

13.2 CNT/DLY0 Register Settings

13.3 CNT/DLY1 Register Settings

Table 60. CNT/DLY0 Register Settings Table 61. CNT/DLY1 Register Settings

13.4 CNT/DLY4 Register Settings

13.5 CNT/DLY5 Register Settings

Table 62. CNT/DLY4 Register Settings Table 63. CNT/DLY5 Register Settings

13.6 CNT/DLY6 Register Settings

Table 64. CNT/DLY6 Register Settings

000-0046169-111 Page 69 of 101 SLG46169

14.0 Pipe Delay (PD)

The SLG46169 has a pipe delay logic cell that is shared with the 3-bit LUT8 in one of the Combination Function macrocells. The user can select one of these functions to use in a design, but not both. Please see Section 10.3 3-Bit LUT or Pipe Delay Macrocell for the description of this Combination Function macrocell.

15.0 Programmable Delay / Edge Detector

period. See the timing diagrams below for further information. Note : The input signal must be longer than the delay, otherwise it will be filtered out.

15.1 Programmable Delay Timing Diagram - Edge Detector Output

Figure 30. Programmable Delay Figure 31. Edge Detector Output

Note: For delays and widths refer to Table 4.

15.2 Programmable Delay Timing Diagram - Glitch Filtering For Edge Detector Output

Figure 32. Delayed Edge Detector Output Figure 33. Glitch Filtering for Edge Detector Output

15.3 Programmable Delay Register Settings

Table 65. Programmable Delay Register Settings

16.0 Additional Logic Functions

are two inverters, which can switch the polarity of any Connection Matrix signal, and there are also two deglitch filters.

16.1 Inverter 0 (INV_0 Gate)

16.2 Inverter 1 (INV_1 Gate)

16.3 Deglitch Filter

Figure 34. INV_0 Gate Figure 35. INV_1 Gate Figure 36. Deglitch Filter

17.0 Voltage Reference (VREF)

17.1 Voltage Reference Overview

supplied voltage references from PIN 6. The macroce ll also has the option to output reference voltages on PIN 12 and PIN 13.

17.2 VREF Selection Table

Table 66. VREF Selection Table.

11011 PIN 6: ACMP0(-) Reserved

11001 VDD / 4 VDD / 4

11000 VDD / 3 VDD / 3

17.3 VREF Block Diagram

Figure 37. Voltage Reference Block Diagram

000-0046169-111 Page 76 of 101 SLG46169

18.0 RC Oscillator (RC Osc)

18.1 RC Oscillator Overview

The SLG46169 has two internal RC oscillators, one that runs at 25 kHz and one that runs at 2 MHz. The user can select one of these fundamental frequencies for the RC OSC Macroc ell, or the fundamental frequency can also come fro m an external clock input (PIN 14). There are two divider stages that allow the user flexibility for introducing clock signals on various Connection Matrix Input lines. The first stage divider allows the selection of /1, /2, /4 or /8 divide down frequency from the fundamental. The second stage divider has an input of one frequency from the first stage divider, and outputs five different frequencies on Connection Matrix Input lines <45>, <46>, <47>, <48>, and <49>. See Figure 38. below for details of the frequencies for each of t hese five Connection Matrix Inputs. If PWR DOWN input of oscillator is LOW, the oscillator will be turned on. If PWR DOWN input of oscillator is HIGH the oscillator will be turned off. The PWR DOWN signal has the highest priority. The user can select two OSC POWER MODEs (reg<707>):

• If AUTO POWER ON <0> is selected, the OSC will run when the SLG46169 is powered on.
• If FORCE POWER ON <1> is selected, the OSC will run only when any macrocell that uses OSC is powered on. OSC can be turned on by:
• Register control (force power on)
• Delay mode, when delay requires OSC
• CNT

18.2 RC OSC Block Diagram

Figure 38. RC OSC Block Diagram

18.3 Oscillator Power On delay

Note 1: OSC power mode: "Auto Power On”. Note 2: ‘OSC enable’ signal appears when any macrocell that uses OSC is powered on. Figure 39. Oscillator Startup Diagram Figure 40. RC Oscillator Maximum Power On Delay vs. VDD at room temperature

2 MHz

18.4 Oscillator Accuracy

Note: OSC power setting: Force Power On; Clock to matrix input - enable; Bandgap: turn on by register - enable. Note: For more information see section 5.10 OSC Specifications. Figure 41. RC Oscillator Frequency vs. Temperature, RC OSC0=2 MHz Figure 42. RC Oscillator Frequency vs. Temperature, RC OSC0=25 kHz

19.0 Power On Reset (POR)

19.1 POR Overview

19.2 POR Timing Diagram

19.2.1 Initialization

1. Input PINs, ACMP , pull up/down;
2. DFFs, Delays/Counters, Pipe Delay;
3. Output PIN corresponds to the internal logic

the mentioned powerup sequence is complete. on the input PIN.There is no effect from input pin when input voltage is applied at the same time as VDD. Figure 43. POR Timing Diagram

19.2.2 Power Down

During powerdown, macrocells in SLG46169 are powere d off and logic macrocells may switch states after falling below 1.4 V. switch state during this time. Figure 44. Power Down

1 V VREF Out Signal

000-0046169-111 Page 82 of 101 SLG46169

20.0 Appendix A - SLG46169 Register Definition

Address Signal Function Register Bit Definition reg<5:0> Reserved reg<11:6> Reserved reg<17:12> Matrix Out PIN3 Digital Output Source reg<23:18> Matrix Out PIN4 Digital Output Source reg<29:24> Matrix Out Output Enable of PIN4 reg<35:30> Matrix Out PIN5 Digital Output Source reg<41:36> Matrix Out PIN6 Digital Output Source reg<47:42> Matrix Out Output Enable of PIN6 reg<53:48> Reserved reg<59:54> Matrix Out PIN7 Digital Output Source reg<65:60> Matrix Out Output Enable of PIN7 reg<71:66> Matrix Out PIN8 Digital Output Source (4X Drive) reg<77:72> Matrix Out pdb (power down) for ACMP0 reg<83:78> Matrix Out pdb (power down) for ACMP1 reg<89:84> Reserved reg<95:90> Matrix Out Input for delay0 or Counter0 external clock reg<101:96> Matrix Out Input for delay1 or counter1 reset input reg<107:102> Matrix Out Input for Counter1 external clock or delay1 external clock reg<113:108> Matrix Out Input for delay4 or Counter4 external clock reg<119:114> Matrix Out Input for delay5 or Counter5 external clock reg<125:120> Matrix Out Input for delay6 or Counter6 external clock reg<131:126> Matrix Out Input for filter_0 reg<137:132> Matrix Out Input for filter_1 reg<143:138> Reserved reg<149:144> Matrix Out In0 of LUT3_9 reg<155:150> Matrix Out In1 of LUT3_9 reg<161:156> Matrix Out In2 of LUT3_9 reg<167:162> Matrix Out In0 of LUT4_0 or Input for Counter2(delay2) external clock reg<173:168> Matrix Out In1 of LUT4_0 or Input for delay2(counter2 reset in- put) reg<179:174> Matrix Out In2 of LUT4_0 reg<185:180> Matrix Out In3 of LUT4_0 reg<191:186> Matrix Out In0 of LUT4_1 or Input for Counter3(delay3) external clock reg<197:192> Matrix Out In1 of LUT4_1 or Input for delay3(counter3 reset in- put) reg<203:198> Matrix Out In2 of LUT4_1

000-0046169-111 Page 83 of 101 SLG46169 reg<209:204> Matrix Out In3 of LUT4_1 reg<215:210> Matrix Out In0 of LUT3_0 reg<221:216> Matrix Out In1 of LUT3_0 reg<227:222> Matrix Out In2 of LUT3_0 reg<233:228> Matrix Out In0 of LUT3_1 reg<239:234> Matrix Out In1 of LUT3_1 reg<245:240> Matrix Out In2 of LUT3_1 reg<251:246> Matrix Out In0 of LUT3_2 or Clock Input of DFF2 reg<257:252> Matrix Out In1 of LUT3_2 or Data Input of DFF2 reg<263:258> Matrix Out In2 of LUT3_2 or Resetb Input of DFF2 reg<269:264> Matrix Out In0 of LUT3_3 or Clock Input of DFF3 reg<275:270> Matrix Out In1 of LUT3_3 or Data Input of DFF3 reg<281:276> Matrix Out In2 of LUT3_3 or Resetb (Setb) of DFF3 reg<287:282> Matrix Out In0 of LUT3_4 reg<293:288> Matrix Out In1 of LUT3_4 reg<299:294> Matrix Out In2 of LUT3_4 reg<305:300> Matrix Out In0 of LUT3_5 reg<311:306> Matrix Out In1 of LUT3_5 reg<317:312> Matrix Out In2 of LUT3_5 reg<323:318> Matrix Out In0 of LUT3_6 reg<329:324> Matrix Out In1 of LUT3_6 reg<335:330> Matrix Out In2 of LUT3_6 reg<341:336> Matrix Out In0 of LUT3_7 reg<347:342> Matrix Out In1 of LUT3_7 reg<353:348> Matrix Out In2 of LUT3_7 reg<359:354> Matrix Out In0 of LUT3_8 or Input of Pipe delay reg<365:360> Matrix Out In1 of LUT3_8 or Resetb of Pipe delay reg<371:366> Matrix Out In2 of LUT3_8 or Clock of Pipe delay reg<377:372> Matrix Out In0 of LUT2_0 or Clock Input of DFF4 reg<383:378> Matrix Out In1 of LUT2_0 or Data Input of DFF4 reg<389:384> Matrix Out In0 of LUT2_1 or Clock Input of DFF5 reg<395:390> Matrix Out In1 of LUT2_1 or Data Input of DFF5 reg<401:396> Matrix Out In0 of LUT2_2 or Clock Input of DFF6 reg<407:402> Matrix Out In1 of LUT2_2 or Data Input of DFF6 reg<413:408> Matrix Out In0 of LUT2_3 or Clock Input of DFF7 reg<419:414> Matrix Out In1 of LUT2_3 or Data Input of DFF7 reg<425:420> Matrix Out In0 of LUT2_4 reg<431:426> Matrix Out In1 of LUT2_4 reg<437:432> Matrix Out In0 of LUT2_5 reg<443:438> Matrix Out In1 of LUT2_5 reg<449:444> Matrix Out Input for programmable delay & edge detector reg<455:450> Matrix Out Power down for osc Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 84 of 101 SLG46169 reg<461:456> Reserved reg<467:462> Reserved reg<473:468> Reserved reg<479:474> Reserved reg<485:480> Reserved reg<491:486> Reserved reg<497:492> Matrix Out Pin10 Digital Output Source reg<503:498> Matrix Out Pin10 Output Enable reg<509:504> Matrix Out Pin11 Digital Output Source reg<515:510> Matrix Out Pin12 Digital Output Source reg<521:516> Matrix Out Pin12 Output Enable reg<527:522> Matrix Out Pin13 Digital Output Source reg<533:528> Matrix Out Pin13 Output Enable reg<539:534> Matrix Out Pin14 Digital Output Source reg<545:540> Matrix Out Input of INV_0 reg<551:546> Matrix Out Input of INV_1 reg<556:552> Reserved reg<558:557> Reserved reg<560:559> Reserved reg<561> Reserved reg<562> Reserved reg<563> Reserved reg<564> VDD bypass enable 0: Regulator auto on 1: Regulator off (VDD bypass) reg<566:565> OSC clock pre-divider 00: Div1 01: Div2 10: Div4 11: Div8 reg<568:567> Reserved Reserved reg<569> Analog buffer at ACMP0 enable 0: Disable analog buffer 1: Enable analog buffer reg<570> Analog buffer at ACMP1 enable 0: Disable analog buffer 1: Enable analog buffer Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 85 of 101 SLG46169 reg<574:571> LUT2_0 Data (if reg.<595>=0) or DFF4 / Latch Select reg<571> DFF4 or Latch select 0: DFF function 1: Latch function reg<572> DFF4 output select 0: Q output 1: nQ output reg<573> DFF4 initial polarity select 0: Low 1: High reg<578:575> LUT2_1 Data (if reg.<596>=0) or DFF5 / Latch Select reg<575> DFF5 or Latch select 0: DFF function 1: Latch function reg<576> DFF5 output select 0: Q output 1: nQ output reg<577> DFF5 initial polarity select 0: Low 1: High reg<582:579> LUT2_2 Data (if reg.<597>=0) or DFF6 / Latch Select reg<579> DFF6 or Latch select 0: DFF function 1: Latch function reg<580> DFF6 output select 0: Q output 1: nQ output reg<581> DFF6 initial polarity select 0: Low 1: High reg<586:583> LUT2_3 Data (if reg.<598>=0) or DFF7 / Latch Select reg<583> DFF7 or Latch select 0: DFF function 1: Latch function reg<584> DFF7 output select 0: Q output 1: nQ output reg<585> DFF7 initial polarity select 0: Low 1: High reg<590:587> LUT2_4 data reg<594:591> LUT2_5 data reg<595> LUT2_0 or DFF4 select 0: LUT2_0 1: DFF4 reg<596> LUT2_1 or DFF5 select 0: LUT2_1 1: DFF5 reg<597> LUT2_2 or DFF6 select 0: LUT2_2 1: DFF6 reg<598> LUT2_3 or DFF7 select 0: LUT2_3 1: DFF7 reg<606:599> LUT3_0 data reg<614:607> LUT3_1 data reg<622:615> LUT3_2 Data (if reg.<671>=0) or DFF2 / Latch Select) reg<615> DFF2 or Latch select 0: DFF function 1: Latch function reg<616> DFF2 output select 0: Q output 1: nQ output reg<617> DFF2 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<618> DFF2 initial polarity select 0: Low 1: High Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 86 of 101 SLG46169 reg<630:623> LUT3_3 Data (if reg.<672>=0) or DFF3 / Latch Select reg<623> DFF3 or Latch select 0: DFF function 1: Latch function reg<624> DFF3 output select 0: Q output 1: nQ output reg<625> DFF3 rstb/setb select 0: resetb from matrix output 1: setb from matrix output reg<626> DFF3 initial polarity select 0: Low 1: High reg<638:631> LUT3_4 data reg<646:639> LUT3_5 data reg<654:647> LUT3_6 data reg<662:655> LUT3_7 data reg<670:663> LUT3_8 data or pipe number select reg<666:663>: OUT0 select reg<670:667>: OUT1 select reg<671> LUT3_2 or DFF2 select 0: LUT3_2 1: DFF2 reg<672> LUT3_3 or DFF3 select 0: LUT3_3 1: DFF3 reg<688:673> LUT4_0 data or Counter / Delay 2 mode selection reg<673> Counter/delay2 mode selection 0: Delay Mode 1: Counter Mode reg<676:674> Counter/delay2 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter1 Overflow reg<684:677> Counter/delay2 Control Data 1-256: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<686:685> Delay2 Mode Select or asynchronous counter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 87 of 101 SLG46169 reg<704:689> LUT4_1 data or Counter / Delay 3 mode selection reg<689> Counter/delay3 mode selection 0: Delay Mode 1: Counter Mode reg<692:690> Counter/delay3 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter2 Overflow reg<700:693> Counter/delay3 Control Data 1-256: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<702:701> Delay3 Mode Select or asynchronous counter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset reg<705> LUT4_0 or Counter2 select 0: LUT4_0 1: Counter2 reg<706> LUT4_1 or Counter3 select 0: LUT4_1 1: Counter3 reg<707> Force RC oscillator on 0: Auto Power on 1: Force Power on reg<708> RC Oscillator frequency control 0: 25 k 1: 2 M reg<709> Filter_0 output polarity select 0: Filter_0 output 1: Filter_0 output inverted reg<711:710> Internal Oscillator frequency divider c ontrol 00: OSC/8 01: OSC/12 10: OSC/24 11: OSC/64 reg<712> External Clock Source Select 0: Internal Oscillator 1: External Clock from Pin20 reg<713> Counter/delay0 mode selection 0: Delay Mode 1: Counter Mode reg<716:714> Counter/delay0 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter6 Overflow reg<730:717> Counter0 Control Data/Delay0 Time Contr ol 1-16384: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<732:731> Delay0 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 88 of 101 SLG46169 reg<733> Counter/delay1 mode selection 0: Delay Mode 1: Counter Mode reg<736:734> Counter/delay1 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter0 Overflow reg<750:737> Counter1 Control Data/Delay1 Time Contr ol 1-16384: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<752:751> Delay1 Mode Select or asynchronous coun ter reset 00: on both falling and rising edges (for delay & counter reset) 01: on falling edge only (for delay & counter reset) 10: on rising edge only (for delay & counter reset) 11: no delay on either falling or rising edges / high level reset for counter mode reg<753> Counter/delay4 mode selection 0: Delay Mode 1: Counter Mode reg<756:754> Counter/delay4 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter3 Overflow reg<764:757> Counter4 Control Data/Delay4 Time Contr ol 1-256: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<766:765> Delay4 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<767> Counter/delay5 mode selection 0: Delay Mode 1: Counter Mode reg<770:768> Counter/delay5 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter4 Overflow reg<778:771> Counter5 Control Data/Delay5 Time Contr ol 1-256: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<780:779> Delay5 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<781> Counter/Delay6 output source select 0: Delay Output 1: Counter Output Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 89 of 101 SLG46169 reg<784:782> Counter/delay6 Clock Source select 000: Internal OSC Clock 001: OSC/4 010: OSC/12 011: OSC/24 100: OSC/64 101: External Clock 110: External Clock/8 111: Counter5 Overflow reg<792:785> Counter6 Control Data/Delay6 Time Contr ol 1-256: (delay time = (counter data + 2 + variable)/freq), where 0 < variable < 1 reg<794:793> Delay6 Mode Select 00: Delay on both falling and rising edges 01: Delay on falling edge only 10: Delay on rising edge only 11: No delay on either falling or rising edges reg<799:795> ACMP0 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: Reserved 11011: EXT_VREF(PIN6) reg<801:800> ACMP0 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg<803:802> ACMP0 positive Input divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X reg<804> ACMP0 low bandwidth (Max: 1 MHz) enable 0: off 1: on reg<805> ACMP0 positive input source select VDD 0: Disabled 1: Enabled reg<810:806> ACMP1 IN voltage select 00000: 50 mV 00001: 100 mV 00010: 150 mV 00011: 200 mV 00100: 250 mV 00101: 300 mV 00110: 350 mV 00111: 400 mV 01000: 450 mV 01001: 500 mV 01010: 550 mV 01011: 600 mV 01100: 650 mV 01101: 700 mV 01110: 750 mV 01111: 800 mV 10000: 850 mV 10001: 900 mV 10010: 950 mV 10011: 1 V 10100: 1.05 V 10101: 1.1 V 10110: 1.15 V 10111: 1.2 V 11000: VDD/3 11001: VDD/4 11010: Reserved 11011: Reserved Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 90 of 101 SLG46169 reg<812:811> ACMP1 hysteresis Enable 00: Disabled (0 mV) 01: Enabled (25 mV) 10: Enabled (50 mV) 11: Enabled (200 mV) reg<814:813> ACMP1 positive Input divider 00: 1.0X 01: 0.5X 10: 0.33X 11: 0.25X reg<815> Reserved must be set to 0 reg<816> ACMP1 low bandwidth (typ: Max.1Mhz) enable 0: off 1: on reg<817> ACMP1 positive input source select PIN6 0: Disabled 1: Enabled reg<822:818> Reserved reg<824:823> Reserved reg<826:825> Reserved reg<827> Reserved reg<828> Reserved reg<830:829> PIN2 mode control 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved reg<832:831> PIN2 pull down resistor value selection 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<834:833> Reserved reg<836:835> Reserved reg<838:837> Reserved reg<839> Reserved reg<842:840> PIN3 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS reg<844:843> PIN3 pull up/down resistor value select ion 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<845> PIN3 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<846> PIN3 driver strength selection 0: 1X 1: 2X reg<848:847> PIN4 mode control (sig_pin4_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 91 of 101 SLG46169 reg<850:849> PIN4 mode control (sig_pin4_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg<852:851> PIN4 pull up/down resistor value select ion 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<853> PIN4 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<856:854> PIN5 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input/Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain reg<858:857> PIN5 pull up/down resistor value select ion 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<859> PIN5 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<860> PIN5 driver strength selection 0: 1X 1: 2X reg<862:861> PIN6 mode control (sig_pin6_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output reg<864:863> PIN6 mode control (sig_pin6_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg<866:865> PIN6 pull up/down resistor value select ion 00: Floating 01: 10 10: 100 K 11: 1 M reg<867> PIN6 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<870:868> Reserved reg<872:871> Reserved reg<873> Reserved reg<874> Reserved reg<876:875> PIN7 mode control (sig_pin7_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved reg<878:877> PIN7 mode control (sig_pin7_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 92 of 101 SLG46169 reg<880:879> PIN7 pull up/down resistor value select ion 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<881> PIN7 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<884:882> PIN8 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Analog Input/Output 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Analog Input & Open Drain reg<886:885> PIN8 pull up/down resistor value select ion 00: Floating 01: 10K 10: 100K 11: 1M reg<887> PIN8 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<888> PIN8 driver strength selection 0: 1X 1: 2X reg<889> PIN8 4X Drive(4X, NMOS open drain) selectio n 0: 4X Drive off 1: 4X Drive on (if reg<884:882> = 101) reg<892:890> Reserved reg<894:893> Reserved reg<895> Reserved reg<896> Reserved reg<897> Reserved reg<899:898> Reserved reg<901:900> Reserved reg<903:902> Reserved reg<904> Reserved reg<906:905> Reserved reg<908:907> Reserved reg<910:909> Reserved reg<911> Reserved reg<914:912> Reserved reg<916:915> Reserved reg<917> Reserved reg<918> Reserved Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 93 of 101 SLG46169 reg<920:919> PIN10 mode control (sig_pin10_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Reserved reg<922:921> PIN10 mode control (sig_pin10_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg<924:923> PIN10 pull up/down resistor value selec tion 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<925> PIN10 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<928:926> PIN11 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS reg<930:929> PIN11 pull up/down resistor value selec tion 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<931> PIN11 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<932> PIN11 driver strength selection 0: 1X 1: 2X reg<934:933> PIN12 mode control (sig_pin12_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output reg<936:935> PIN12 mode control (sig_pin12_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X reg<938:937> PIN12 pull up/down resistor value selec tion 00: Floating 01: 10 K 10: 100 K 11: 1 M reg<939> PIN12 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<941:940> PIN13 mode control (sig_pin13_oe =0) 00: Digital Input without Schmitt Trigger 01: Digital Input with Schmitt Trigger 10: Low Voltage Digital Input 11: Analog Input/Output reg<943:942> PIN13 mode control (sig_pin13_oe =1) 00: Push Pull 1X 01: Push Pull 2X 10: Open Drain NMOS 1X 11: Open Drain NMOS 2X Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 94 of 101 SLG46169 reg<945:944> PIN13 pull up/down resistor value selec tion 00: Floating 01: 10K 10: 100K 11: 1M reg<946> PIN13 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<949:947> PIN14 mode control 000: Digital Input without Schmitt Trigger 001: Digital Input with Schmitt Trigger 010: Low Voltage Digital Input 011: Reserved 100: Push Pull 101: Open Drain NMOS 110: Open Drain PMOS 111: Open Drain NMOS reg<951:950> PIN14 pull up/down resistor value selec tion 00: Floating 01: 10K 10: 100K 11: 1M reg<952> PIN14 pull up/down resistor select 0: pull down resistor enable 1: pull up resistor enable reg<953> PIN14 driver strength selection 0: 1X 1: 2X reg<961:954> LUT3_9 data reg<962> Filter_1 output polarity select 0: Filter_1 output 1: Filter_1 output inverted reg<963> LUT3_8 or pipe delay output select 0: LUT3_8 1: 1pipe delay output reg<964> Pipe delay OUT1 polarity select bit 0: non-inverted 1: inverted reg<966:965> Delay value select for programmable delay & edge de- tector (VDD = 3.3V, typical condition) 00: 125 ns 01: 250 ns 10: 375 ns 11: 500 ns reg<968:967> Select the edge mode of programmable delay & edge detector 00: rising edge detector 01: falling edge detector 10: both edge detector 11: both edge delay reg<969> Select edge detector output mode 0: edge detector output 1: delayed edge detector output reg<977:970> 8-bit pattern id reg<978> GPIO quick charge enable 0: Disable 1: Enable reg<979> NVM data read disable 0: Disable (program data can be read) 1: Enable (Program data cannot be read) reg<980> NVM power down 0: None (or programming enable) 1: Power Down (or programming disable) reg<981> Force bandgap on 0: Auto-mode 1: Enable reg<982> VREF Output Active Buffer Control 0: Disabled (bypass Active Buffer) 1: Enabled reg<983> Reserved reg<991:984> Reserved Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 95 of 101 SLG46169 reg<994:992> VREF Output Source Select 000: ACMP0 reference voltage 001: ACMP1 reference voltage 100: VDD/2 101: VDD/3 110: VDD/4 111: Hi-Z reg<997:995> Reserved reg<998> Power Divider Power 0: Power down 1: Power On reg<999> POR Auto Power detect 0: Enable 1: Disable reg<1000> Charge pump for analog macrocell enable (when VDD <=2.7V turn on) 0: Disable (automatic on/off control) 1: Enable (always on) reg<1002:1001> Reserved reg<1007:1003> Reserved reg<1013:1008> Reserved Reg<1015:1014> Reserved reg<1023:1016> Reserved Register Bit Address Signal Function Register Bit Definition

000-0046169-111 Page 96 of 101 SLG46169

21.0 Package Top Marking System Definition

21.1 Before February 1, 2021

21.2 After February 1, 2021

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22.0 Package Drawing and Dimensions

STQFN 14L 2 x 2.2mm 0.4P COL Package JEDEC MO-220, Variation WECE

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23.0 Tape and Reel Specifications

23.1 Carrier Tape Drawing and Dimensions

# of Pins Nominal Package Size [mm] Max Units Reel & Hub Size [mm] Leader (min) Trailer (min) Tape Width [mm] Part Pitch [mm] per Reel per Box Pockets Length [mm] Pockets Length [mm] STQFN 14L 2x2.2 mm 0.4P COL 14 2 x 2.2 x 0.55 3,000 3,000 178 / 60 100 400 100 400 8 4 Package Type Pocket BTM Length Pocket BTM Width Pocket Depth Index Hole Pitch Pocket Pitch Index Hole Diameter Index Hole to Tape Edge Index Hole to Pocket Center Tape Width A0 B0 K0 P0 P1 D0 E F W STQFN 14L 2x2.2 mm 0.4P COL Refer to EIA-481 specification

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24.0 Recommended Landing Pattern

25.0 Recommended Reflow Soldering Profile

Please see IPC/JEDEC J-STD-020: latest revision for reflow profile based on package volume of 2.42 mm 3 (nominal). More information can be found at www.jedec.org.

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26.0 Revision History

3/10/2023 1.11 Added notes to section Ordering Inform ation 3/4/2022 1.10 Added R PUP and R PDWN in section Electrical Specifications Renesas rebranding Updated tables CNT/DLY Register Settings [778:771], [792:785] in Appendix A - SLG46169 Register Definition 2/2/2021 1.09 Updated section Package Top Marking Sys tem Definition 10/30/2019 1.08 Added pre front page Updated last page with disclaimer and contacts 4/16/2019 1.07 Updated Chip Quiescent Value 5/10/2018 1.06 Fixed ACMP‘s hysteresis formula 12/4/2017 1.05 Fixed typos 10/10/2017 1.04 Updated Electrical Spec Fixed typos 7/5/2017 1.03 Updated Electrical Spec 4/13/2017 1.02 Fixed typos Updated Silego Website & Support Updated Section Programmable Delay / Edge Detector 10/20/2016 1.01 Removed references to GPAK families 9/28/2016 1.00 Production Release

000-0046169-111 Page 101 of 101 SLG46169 RoHS Compliance Renesas Electronics Corporation’s suppliers certify that its products are in compliance with the requirements of Directive 2011/65/EU of the European Parliament on the restriction of the use of certain hazardous sub stances in electrical and electronic equipment. RoH S certificates from our suppliers are available on request.

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