SAA7108AE

NXP Semiconductors

HD-CODEC Rev. 03-6 February 2007

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SAA7108AE NXP

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General description The SAA7108AE; SAA7109AE is a new multistandard video decoder and encoder chip, offering high quality video input and TV output processing as required by PC-99 speciﬁcations. It enables hardware manufacturers to implement versatile video functions on a signiﬁcantly reduced printed-circuit board area at very competitive costs. Separate pins for supply voltages as well as for I 2C-bus control and boundary scan test have been provided for the video encoder and decoder sections to ensure both ﬂexible handling and optimized noise behavior. The video encoder is used to encode PC graphics data at maximum 1280× 1024 resolution (optionally 1920× 1080 interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and anti-ﬂicker ﬁlter (maximum 5 lines) ensures properly sized and ﬂicker-free TV display as CVBS or S-video output. Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals together with a TTL composite sync to feed SCART connectors. When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor at maximum 1280× 1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port can provide Y , P B and PR signals for HDTV monitors. The encoder section includes a sync/clock generator and on-chip DACs. All inputs intended to interface to the host graphics controller are designed for low-voltage signals down to 1.1 V and up to 3.45 V. The video decoder, a 9-bit video input processor, is a combination of a 2-channel analog pre-processing circuit including source selection, anti-aliasing ﬁlter and Analog-to-Digital Converter (ADC), automatic clamp and gain control, a Clock Generation Circuit (CGC), and a digital multistandard decoder (PAL BGHI, PAL M, PAL N, combination PAL N, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM). The decoder includes a brightness, contrast and saturation control circuit, a multistandard VBI data slicer and a 27 MHz VBI data bypass. The pure 3.3 V (5 V compatible) CMOS circuit SAA7108AE; SAA7109AE, consisting of an analog front-end and digital video decoder, a digital video encoder and analog back-end, is a highly integrated circuit especially designed for desktop video applications. The decoder is based on the principle of line-locked clock decoding and is able to decode the color of PAL, SECAM and NTSC signals into ITU-R BT.601 compatible color component values. SAA7108AE; SAA7109AE HD-CODEC Rev. 03 — 6 February 2007 Product data sheet

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 2 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC The encoder can operate fully independently at its own variable pixel clock, transporting graphics input data, and at the line-locked, single crystal-stable video encoding clock. As an option, it is possible to slave the video PAL/NTSC encoding to the video decoder clock with the encoder FIFO acting as a buffer to decouple the line-locked decoder clock from the crystal-stable encoder clock. 2. Features

2.1 Video decoder

n Six analog inputs, internal analog source selectors, e.g. 6× CVBS or (2× Y/C and 2 × CVBS) or (1× Y/C and 4× CVBS) n Two analog preprocessing channels in differential CMOS style for best S/N performance n Fully programmable static gain or Automatic Gain Control (AGC) for the selected CVBS or Y/C channel n Switchable white peak control n Two built-in analog anti-aliasing ﬁlters n Two 9-bit video CMOS Analog-to-Digital Converters (ADCs), digitized CVBS or Y/C signals are available on the Image Port Data (IPD) port under I2C-bus control n On-chip clock generator n Line-locked system clock frequencies n Digital PLL for horizontal sync processing and clock generation, horizontal and vertical sync detection n Requires only one crystal (either 24.576 MHz or 32.11 MHz) for all standards n Automatic detection of 50 Hz and 60 Hz ﬁeld frequency, and automatic switching between PAL and NTSC standards n Luminance and chrominance signal processing for PAL BGHI, PAL N, combination PAL N, PAL M, NTSC M, NTSC-Japan, NTSC N, NTSC 4.43 and SECAM n User programmable luminance peaking or aperture correction n Cross-color reduction for NTSC by chrominance comb ﬁltering n PAL delay line for correcting PAL phase errors n Brightness Contrast Saturation (BCS) and hue control on-chip n Two multifunctional real-time output pins controlled by the I2C-bus n Multistandard VBI data slicer decoding World Standard Teletext (WST), North-American Broadcast Text System (NABTS), Closed Caption (CC), Wide Screen Signalling (WSS), Video Programming System (VPS), Vertical Interval Time Code (VITC) variants (EBU/SMPTE) etc. n Standard ITU 656 Y -C B-CR 4 : 2 : 2 format (8-bit) on IPD output bus n Enhanced ITU 656 output format on IPD output bus containing: u Active video u Raw CVBS data for INTERCAST applications (27 MHz data rate) u Decoded VBI data n Detection of copy protected input signals according to the Macrovision standard. Can be used to prevent unauthorized recording of pay-TV or video tape signals

2.2 Video scaler

n Conversion to square pixel format n NTSC to 288 lines (video phone) n Phase accuracy better than1⁄64 pixel or line, horizontally or vertically n Independent scaling deﬁnitions for odd and even ﬁelds n Anti-alias ﬁlter for horizontal scaling n Provides output as: u Scaled active video u Raw CVBS data for INTERCAST, WAVE-PHORE, POPCON applications or general VBI data decoding (27 MHz or sample rate converted) n Local video output for Y -CB-CR 4:2:2 f o rmat (VMI, VIP and ZV)

2.3 Video encoder

n Digital PAL/NTSC encoder with integrated high quality scaler and anti-ﬂicker ﬁlter for TV output from a PC n Supports Intel Digital Video Out (DVO) low-voltage interfacing to graphics controller n 27 MHz crystal-stable subcarrier generation n Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip or from external source n Programmable assignment of clock edge to bytes (in double edged mode) n Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as reference clock for the VGC, as well n PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible) n Hot-plug detection through dedicated interrupt pin n Supported VGA resolutions for PAL or NTSC legacy video output up to 1280× 1024 graphics data at 60 Hz or 50 Hz frame rate n Supported VGA resolutions for HDTV output up to 1920× 1080 interlaced graphics data at 60 Hz or 50 Hz frame rate n Three Digital-to-Analog Converters (DACs) for CVBS (BLUE, CB), VBS (GREEN, CVBS) and C (RED, CR ) at 27 MHz sample rate (signals in parenthesis are optionally selected), all at 10-bit resolution n Non-interlaced CB-Y -CR or RGB input at maximum 4 : 4 : 4 sampling n Downscaling and upscaling from 50 % to 400 % n Optional interlaced CB-Y -CR input of Digital Versatile Disk (DVD) signals n Optional non-interlaced RGB output to drive second VGA monitor (bypass mode, maximum 85 MHz) n 3 × 256 bytes RGB Look-Up Table (LUT) n Support for hardware cursor n HDTV up to 1920× 1080 interlaced and 1280× 720 progressive, including 3-level sync pulses n Programmable border color of underscan area n Programmable 5-line anti-ﬂicker ﬁlter n On-chip 27 MHz crystal oscillator (3rd harmonic or fundamental 27 MHz crystal) n Fast I2C-bus control port (400 kHz)

2.4 Common features

[1] Power dissipation is extremely dependent on programming and selected application. Table 1. Quick reference data

27 MHz

TTX_SRES XTALIe HSVGC CBO TTXRQ_XCLKO2 F1 G3 G2 SDAe SCLe E2 D2E3 C4 PIXEL CLOCK SYNTHESIZER INPUT FORMATTER C1, C2, B1, B2, A2, B4, B3, A3, F3, H1, H2, H3 PD11 to PD0 PIXCLKI G4PIXCLKO mbl785 SAA7108AE SAA7109AE RESe

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 7 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC (1) The pins RTCO and ALRCLK are used for conﬁguration of the I2C-bus interface and the deﬁnition of the crystal oscillator frequency at RESET (pin strapping). Fig 3. Block diagram (video decoder part) FIR-PREFILTER PRESCALER AND SCALER BCS GENERAL PURPOSE VBI DATA SLICER VIDEO/TEXT ARBITER TEXT FIFO VIDEO FIFO PROGRAMMING REGISTER ARRAY A/B REGISTER MUX EVENT CONTROLLER IMAGE PORT PIN MAPPING X PORT I/O FORMATTING EXPANSION PORT PIN MAPPING I/O CONTROL I2C-BUSREAL-TIME OUTPUT LLC P8AI2D LINE FIFO BUFFER VERTICAL SCALING HORIZONTAL FINE (PHASE) SCALING 32 to 8(16) MUX G14 ITRI N10AGND P12AI1D M10AOUT P6AI24 P7AI23 P9AI22 P10AI21 P11AI12 P13AI11 P3XTALOd P2XTALId P4XTOUTd N14CE M12 M14 TCKd TMSd TDId VDDXd VSSXd VDDId D11, F11, J4, J11, L4, L11 VDDEd D10, G11, L7, L9 VDDAd M8, M9, N11 VSSId E11, K4, K11 VSSEd H4, H11, L6, M13 VSSAd M7, N7 to N9, N12, N13 AMXCLK J12 TDOd AMCLK K12 ALRCLK J13 ASCLK K14 LLC2 L14 RTCO L13 RTS0 K13 RTS1 L10 XCLK XDQ M4 K2, K3, L1 to L3, M1, M2, N1 XRH XRV XRDY SDAd L12 SCLd M11 TEST5 TEST4 TEST3 TEST2 C10 TEST1 B10 TEST0 H13A13, D12, C12, B12, A12, C11, B11, A11 XTRI chrominance of 16-bit input BOUNDARY SCAN TEST CLOCK GENERATION AND POWER-ON CONTROL ANALOG DUAL ADC DIGITAL DECODER WITH ADAPTIVE COMB FILTER AUDIO CLOCK GENERATION J14 ITRDY H12 ICLK G13 IGP1 F14 IGP0 F13 IGPV G12 IGPH H14 IDQ E14, D14, C14, B14, E13, D13, C13, B13 IPD[7:0] HPD [7:0] XPD [7:0]RESd SAA7108AE SAA7109AE TRSTd (1) (1) mbl791

7.1 Pinning

Fig 4. Pin conﬁguration (LBGA156) 001aae257 SAA7108AE SAA7109AE Transparent top view P N M L K J G E H F D C B A 2468 1 0 1 2 1 3 1 413579 1 1 ball A1 index area

7.2 Pin description

Table 3. Pin allocation table …continued Table 4. Pin description

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] Pin type: I = input, O = output, S = supply, pu = pull-up. [2] For board design without boundary scan implementation connectTRST e andTRSTd to ground. Port (TAP) controller to the TEST_LOGIC_RESET state (normal operation) at once. with an internal pull-up resistor and TDOe (TDOd) is a 3-state output pin. are switched to input mode to read the strapping level. For the default setting no strapping resistor is necessary (internal pull-down). [6] Pin ALRCLK = LOW for 24.576 MHz crystal (default); pin ALRCLK = HIGH for 32.110 MHz crystal.

Functional description of digital video encoder part

C R -Y -CB signals. NTSC M, PAL B/G and sub-standards are supported. ﬁlter for a ﬂicker-free display at a very high sharpness.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 16 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Besides the most common 16-bit 4:2:2 CB-Y -CR input format (using 8 pins with double edge clocking), other CB-Y -CR and RGB formats are also supported; seeTable12 to Table18. A complete 3 bytes× 256 bytes Look-Up Table (LUT), which can be used, for example, as a separate gamma corrector, is located in the RGB domain; it can be loaded either through the video input port Pixel Data (PD) or via the I 2C-bus. The SAA7108AE; SAA7109AE supports a 32-bit× 32-bit× 2-bit hardware cursor, the pattern of which can also be loaded through the video input port or via the I2C-bus. It is also possible to encode interlaced4:2:2 video signals such as PC-DVD; for that the anti-ﬂicker ﬁlter, and in most cases the scaler, will simply be bypassed. Besides the applications for video output, the SAA7108AE; SAA7109AE can also be used for generating a kind of auxiliary VGA output, when the RGB non-interlaced input signal is fed to the DACs. This may be of interest for example, when the graphics controller provides a second graphics window at its video output port. The basic encoder function consists of subcarrier generation, color modulation and insertion of synchronization signals at a crystal-stable clock rate of 13.5 MHz (independent of the actual pixel clock used at the input side), corresponding to an internal 4:2:2 bandwidth in the luminance/color difference domain. Luminance and chrominance signals are ﬁltered in accordance with the standard requirements of ‘RS-170-A’and ‘ITU-R BT.470-3’. For ease of analog post ﬁltering the signals are twice oversampled to 27 MHz before digital-to-analog conversion. The total ﬁlter transfer characteristics (scaler and anti-ﬂicker ﬁlter are not taken into account) are illustrated inFigure6 toFigure11. All three DACs are realized with full 10-bit resolution. The CR -Y -CB to RGB dematrix can be bypassed (optionally) in order to provide the upsampled CR -Y -CB input signals. The 8-bit multiplexed CB-Y -CR formats are‘ITU-R BT.656’(D1 format) compatible, but the SAV and EAV codes can be decoded optionally, when the device is operated in Slave mode. For assignment of the input data to the rising or falling clock edge see Table12 toTable18. In order to display interlaced RGB signals through a euro-connector TV set, a separate digital composite sync signal (pin HSM_CSYNC) can be generated; it can be advanced up to 31 periods of the 27 MHz crystal clock in order to be adapted to the RGB processing of a TV set. The SAA7108AE; SAA7109AE synthesizes all necessary internal signals, color subcarrier frequency and synchronization signals from that clock. Wide screen signalling data can be loaded via the I 2C-bus and is inserted into line 23 for standards using a 50 Hz ﬁeld rate. VPS data for program dependent automatic start and stop of such featured VCRs is loadable via the I2C-bus.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 17 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC The IC also contains closed caption and extended data services encoding (line 21), and supports teletext insertion for the appropriate bit stream format at a 27 MHz clock rate (see Figure66). It is also possible to load data for the copy generation management system into line 20 of every ﬁeld (525/60 line counting). A number of possibilities are provided for setting different video parameters such as:

Black and blanking level control
Color subcarrier frequency
Variable burst amplitude etc. (1) SCBW = 1. (2) SCBW = 0. Fig 6. Chrominance transfer characteristic f (MHz) mbe737 −30 −18 −42 0G v (dB) −54 −24 −12 −36 −48 0 1410 128246 (1) (2)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 18 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC (1) SCBW = 1. (2) SCBW = 0. Fig 7. Chrominance transfer characteristic (enlargement ofFigure6) Fig 8. Luminance transfer characteristic (excluding scaler) 0 0.4 0.8 1.6 1.2 f (MHz) G v (dB) (1) (2) mbe735 f (MHz) mgd672 −30 −18 −42 0G v (dB) −54 0 1410 128246 (1) (2) (4) (3) −24 −12 −36 −48

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 19 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 9. Luminance transfer characteristic (excluding scaler) (enlargement ofFigure8) Fig 10. Luminance transfer characteristic in RGB (excluding scaler) (1) mbe736 4 f (MHz) G v (dB) f (MHz) mgb708 −30 −18 −42 0G v (dB) −54 0 1410 128246 −24 −12 −36 −48

8.1 Reset conditions

To activate the reset, a pulse of at least 2 crystal clocks duration is required. sets it into receive condition. an I2C-bus access redeﬁnes the corresponding registers; seeTable5. Table 5. Strapping pins

8.2 Input formatter

to a common internal RGB or Y -CB-CR data stream. and EDGE for correct operation. be used directly to feed the video encoder block.

8.3 RGB LUT

event that the indexed color data is applied, the RAMs are addressed in parallel. active line. The ﬁrst 3 bytes represent the ﬁrst RGB LUT data, and so on.

8.4 Cursor insertion

column, followed by the row; index 0,0 is the upper left corner. Table 6. Layout of a byte in the cursor bit map

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. registers describe the co-ordinates of the hot spot. Again 0,0 is the upper left corner. the cursor position is described relative to the input resolution.

8.5 RGB Y-C B -CR matrix

formatted to a ITU-R BT.601 like 4:2:2 data stream for further processing. 0 to 255) to the required range of 16 to 235. immediately directed to the triple DAC.

8.6 Horizontal scaler

compensate the color phase offset automatically. pixel (XINC/4096). A special case is XINC = 0, this sets the scaling factor to 1. Table 7. Cursor bit map Table 8. Cursor modes

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 23 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC If the SAA7108AE; SAA7109AE input data is in accordance with‘ITU-R BT.656’, the scaler enters another mode. In this event, XINC needs to be set to 2048 for a scaling factor of 1. With higher values, upscaling will occur. The phase resolution of the circuit is 12 bits, giving a maximum offset of 0.2 after 800 input pixels. Small FIFOs rearrange a 4:2:2 data stream at the scaler output.

8.7 Vertical scaler and anti-ﬂicker ﬁlter

The functions scaling, Anti-Flicker Filter (AFF) and re-interlacing are implemented in the vertical scaler. Besides the entire input frame, it receives the ﬁrst and last lines of the border to allow anti-ﬂicker ﬁltering. The circuit generates the interlaced output ﬁelds by scaling down the input frames with different offsets for odd and even ﬁelds. Increasing the YSKIP setting reduces the anti-ﬂicker function. A YSKIP value of 4095 switches it off; see Table107. An additional, programmable vertical ﬁlter supports the anti-ﬂicker function. This ﬁlter is not available at upscaling factors of more than 2. The programming is similar to the horizontal scaler. For the re-interlacing, the resolutions of the offset registers are not sufﬁcient, so the weighting factors for the ﬁrst lines can also be adjusted. YINC = 0 sets the scaling factor to 1; YIWGTO and YIWGTE must not be 0. Due to the re-interlacing, the circuit can perform upscaling by a maximum factor of 2. The maximum factor depends on the setting of the anti-ﬂicker function and can be derived from the formulae given in Section8.20. An additional upscaling mode allows to increase the upscaling factor to maximum 4 as it is required for the old VGA modes like 320× 240.

8.8 FIFO

The FIFO acts as a buffer to translate from the PIXCLK clock domain to the XTAL clock domain. The write clock is PIXCLK and the read clock is XTAL. An underﬂow or overﬂow condition can be detected via the I 2C-bus read access. In order to avoid underﬂows and overﬂows, it is essential that the frequency of the synthesized PIXCLK matches to the input graphics resolution and the desired scaling factor.

8.9 Border generator

When the graphics picture is to be displayed as interlaced PAL, NTSC, S-video or RGB on a TV screen, it is desired in many cases not to lose picture information due to the inherent overscanning of a TV set. The desired amount of underscan area, which is achieved through appropriate scaling in the vertical and horizontal direction, can be ﬁlled in the border generator with an arbitrary true color tint.

8.10 Oscillator and Discrete Time Oscillator (DTO)

The master clock generation is realized as a 27 MHz crystal oscillator, which can operate with either a fundamental wave crystal or a 3rd harmonic crystal. The crystal clock supplies the DTO of the pixel clock synthesizer, the video encoder and the I2C-bus control block. It also usually supplies the triple DAC, with the exception of the auxiliary VGA mode, where the triple DAC is clocked by the pixel clock (PIXCLK). The DTO can be programmed to synthesize all relevant pixel clock frequencies between circa 40 MHz and 85 MHz. Two programmable dividers provide the actual clock to be used externally and internally. The dividers can be programmed to factors of 1, 2, 4 and 8. For the internal pixel clock, a divider ratio of 8 makes no sense and is thus forbidden. The internal clock can be switched completely to the pixel clock input. In this event, the input FIFO is useless and will be bypassed. The entire pixel clock generation can be locked to the vertical frequency. Both pixel clock dividers get re-initialized every ﬁeld. Optionally, the DTO can be cleared with each V-sync. At proper programming, this will make the pixel clock frequency a precise multiple of the vertical and horizontal frequencies. This is required for some graphic controllers.

8.11 Low-pass Clock Generation Circuit (CGC)

This block reduces the phase jitter of the synthesized pixel clock. It works as a tracking ﬁlter for all relevant synthesized pixel clock frequencies.

8.12 Encoder

8.12.1 Video path

The encoder generates luminance and color subcarrier output signals from the Y, C B and CR baseband signals, which are suitable for use as CVBS or separate Y and C signals. Input to the encoder, at 27 MHz clock (e.g. DVD), is either originated from computer graphics at pixel clock, fed through the FIFO and border generator, or a ITU-R BT.656 style signal. Luminance is modiﬁed in gain and in offset (the offset is programmable in a certain range to enable different black level set-ups). A blanking level can be set after insertion of a ﬁxed synchronization pulse tip level, in accordance with standard composite synchronization schemes. Other manipulations used for the Macrovision anti-taping process, such as additional insertion of AGC super-white pulses (programmable in height), are supported by the SAA7108AE only. To enable easy analog post ﬁltering, luminance is interpolated from a 13.5 MHz data rate to a 27 MHz data rate, thereby providing luminance in a 10-bit resolution. The transfer characteristics of the luminance interpolation ﬁlter are illustrated in Figure8 and Figure9. Appropriate transients at start/end of active video and for synchronization pulses are ensured.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 25 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Chrominance is modiﬁed in gain (programmable separately for CB and CR ), and a standard dependent burst is inserted, before baseband color signals are interpolated from a 6.75 MHz data rate to a 27 MHz data rate. One of the interpolation stages can be bypassed, thus providing a higher color bandwidth, which can be used for the Y and C output. The transfer characteristics of the chrominance interpolation ﬁlter are illustrated in Figure6 andFigure7. The amplitude (beginning and ending) of the inserted burst, is programmable in a certain range that is suitable for standard signals and for special effects. After the succeeding quadrature modulator, color is provided on the subcarrier in 10-bit resolution. The numeric ratio between the Y and C outputs is in accordance with the standards.

8.12.2 Teletext insertion and encoding (not simultaneously with real-time control)

Pin TTX_SRES receives a WST or NABTS teletext bitstream sampled at the crystal clock. At each rising edge of the output signal (TTXRQ) a single teletext bit has to be provided after a programmable delay at input pin TTX_SRES. Phase variant interpolation is achieved on this bitstream in the internal teletext encoder, providing sufﬁcient small phase jitter on the output text lines. TTXRQ_XCLKO2 provides a fully programmable request signal to the teletext source, indicating the insertion period of bitstream at lines which can be selected independently for both ﬁelds. The internal insertion window for text is set to 360 (PAL WST), 296 (NTSC WST) or 288 (NABTS) teletext bits including clock run-in bits. The protocol and timing are illustrated in Figure66. Alternatively, this pin can be provided with a buffered crystal clock (XCLK) of 13.5 MHz.

8.12.3 Video Programming System (VPS) encoding

Five bytes of VPS information can be loaded via the I2C-bus and will be encoded in the appropriate format into line 16.

8.12.4 Closed caption encoder

Using this circuit, data in accordance with the speciﬁcation of closed caption or extended data service, delivered by the control interface, can be encoded (line 21). Two dedicated pairs of bytes (two bytes per ﬁeld), each pair preceded by run-in clocks and framing code, are possible. The actual line number in which data is to be encoded, can be modiﬁed in a certain range. The data clock frequency is in accordance with the deﬁnition for NTSC M standard 32 times horizontal line frequency. Data LOW at the output of the DACs corresponds to 0 IRE, data HIGH at the output of the DACs corresponds to approximately 50 IRE. It is also possible to encode closed caption data for 50 Hz ﬁeld frequencies at 32 times the horizontal line frequency.

8.12.5 Anti-taping (SAA7108AE only)

For more information contact your nearest NXP Semiconductors sales ofﬁce.

8.13 RGB processor

This block contains a dematrix in order to produce RED, GREEN and BLUE signals to be fed to a SCART plug. Before Y , CB and CR signals are de-matrixed, individual gain adjustment for Y and color difference signals and 2 times oversampling for luminance and 4 times oversampling for color difference signals is performed. The transfer curves of luminance and color difference components of RGB are illustrated in Figure10 andFigure11.

8.14 Triple DAC

Both Y and C signals are converted from digital-to-analog in a 10-bit resolution at the output of the video encoder. Y and C signals are also combined into a 10-bit CVBS signal. The CVBS output signal occurs with the same processing delay as the Y , C and optional RGB or CR -Y -CB outputs. Absolute amplitude at the input of the DAC for CVBS is reduced by 15⁄16 with respect to Y and C DACs to make maximum use of the conversion ranges. RED, GREEN and BLUE signals are also converted from digital-to-analog, each providing a 10-bit resolution. The reference currents of all three DACs can be adjusted individually in order to adapt for different output signals. In addition, all reference currents can be adjusted commonly to compensate for small tolerances of the on-chip band gap reference voltage. Alternatively, all currents can be switched off to reduce power dissipation. All three outputs can be used to sense for an external load (usually 75Ω ) during a pre-deﬁned output. A ﬂag in the I 2C-bus status byte reﬂects whether a load is applied or not. In addition, an automatic sense mode can be activated which indicates a 75Ω load at any of the three outputs at the dedicated interrupt pin TVD. If the SAA7108AE; SAA7109AE is required to drive a second (auxiliary) VGA monitor or an HDTV set, the DACs receive the signal coming from the HD data path. In this event, the DACs are clocked at the incoming PIXCLKI instead of the 27 MHz crystal clock used in the video encoder.

8.15 HD data path

This data path allows the SAA7108AE; SAA7109AE to be used with VGA or HDTV monitors. It receives its data directly from the cursor generator and supports RGB and Y- P B-PR output formats (RGB not with Y -PB-PR input formats). No scaling is done in this mode. A gain adjustment either leads the full level swing to the digital-to-analog converters or reduces the amplitude by a factor of 0.69. This enables sync pulses to be added to the signal as it is required for display units expecting signals with sync pulses, either regular or 3-level syncs.

8.16 Timing generator

The synchronization of the SAA7108AE; SAA7109AE is able to operate in two modes; Slave mode and Master mode. In Slave mode, the circuit accepts sync pulses on the bidirectional FSVGC (frame sync), VSVGC (vertical sync) and HSVGC (horizontal sync) pins: the polarities of the signals can be programmed. The frame sync signal is only necessary when the input signal is interlaced, in other cases it may be omitted. If the frame sync signal is present, it is possible to derive the vertical and the horizontal phase from it by setting the HFS and VFS bits. HSVGC and VSVGC are not necessary in this case, so it is possible to switch the pins to output mode. Alternatively, the device can be triggered by auxiliary codes in a ITU-R BT.656 data stream via PD7 to PD0. Only vertical frequencies of 50 Hz and 60 Hz are allowed with the SAA7108AE; SAA7109AE. In Slave mode, it is not possible to lock the encoders color carrier to the line frequency with the PHRES bits. In the (more common) Master mode, the time base of the circuit is continuously free-running. The IC can output a frame sync at pin FSVGC, a vertical sync at pin VSVGC, a horizontal sync at pin HSVGC and a composite blanking signal at pin CBO. All of these signals are deﬁned in the PIXCLK domain. The duration of HSVGC and VSVGC are ﬁxed, they are 64 clocks for HSVGC and 1 line for VSVGC. The leading slopes are in phase and the polarities can be programmed. The input line length can be programmed. The ﬁeld length is always derived from the ﬁeld length of the encoder and the pixel clock frequency that is being used. CBO acts as a data request signal. The circuit accepts input data at a programmable number of clocks after CBO goes active. This signal is programmable and it is possible to adjust the following (seeFigure64 andFigure65):

The horizontal offset
The length of the active part of the line
The distance from active start to ﬁrst expected data
The vertical offset separately for odd and even ﬁelds
The number of lines per input ﬁeld In most cases, the vertical offsets for odd and even ﬁelds are equal. If they are not, then the even ﬁeld will start later. The SAA7108AE; SAA7109AE will also request the ﬁrst input lines in the even ﬁeld, the total number of requested lines will increase by the difference of the offsets. As stated above, the circuit can be programmed to accept the look-up and cursor data in the ﬁrst 2 lines of each ﬁeld. The timing generator provides normal data request pulses for these lines; the duration is the same as for regular lines. The additional request pulses will be suppressed with LUTL set to logic 0; see Table132. The other vertical timings do not change in this case, so the ﬁrst active line can be number 2, counted from 0.

8.17 Pattern generator for HD sync pulses

The pattern generator provides appropriate synchronization patterns for the video data path in auxiliary monitor or HDTV mode. It provides maximum ﬂexibility in terms of raster generation for all interlaced and non-interlaced computer graphics or ATSC formats. The sync engine is capable of providing a combination of event-value pairs which can be used to insert certain values in the outgoing data stream at speciﬁed times. It can also be used to generate digital signals associated with time events. These can be used as digital horizontal and vertical synchronization signals on pins HSM_CSYNC and VSM. The picture position is adjustable through the programmable relationship between the sync pulses and the video contents. The generation of embedded analog sync pulses is bound to a number of events which can be deﬁned for a line. Several of these line timing deﬁnitions can exist in parallel. For the ﬁnal sync raster composition a certain sequence of lines with different sync event properties has to be deﬁned. The sequence speciﬁes a series of line types and the number of occurrences of this speciﬁc line type. Once the sequence has been completed, it restarts from the beginning. All pulse shapes are ﬁltered internally in order to avoid ringing after analog post ﬁlters. The sequence of the generated pulse stream must ﬁt precisely to the incoming data stream in terms of the total number of pixels per line and lines per frame. The sync engines ﬂexibility is achieved by using a sequence of linked lists carrying the properties for the image, the lines as well as fractions of lines. Figure12 illustrates the context between the various tables. The ﬁrst table serves as an array to hold the correct sequence of lines that compose the synchronization raster; it can contain up to 16 entries. Each entry holds a 4-bit index to the next table and a 10-bit counter value which speciﬁes how often this particular line is invoked. If the necessary line count for a particular line exceeds the 10 bits, it has to use two table entries. The 4-bit index in the line count array points to the line type array. It holds up to 15 entries (index 0 is not used), index 1 points to the ﬁrst entry, index 2 to the second entry of the line type array etc. Each entry of the line type array can hold up to 8 index pointers to another table. These indices point to portions of a line pulse pattern: A line could be split up e.g. into a sync, a blank, and an active portion followed by another blank portion, occupying four entries in one table line. Each index of this table points to a particular line of the next table in the linked list. This table is called the line pattern array and each of the up to seven entries stores up to four pairs of a duration in pixel clock cycles and an index to a value table. The table entries are used to deﬁne portions of a line representing a certain value for a certain number of clock cycles. The value speciﬁed in this table is actually another 3-bit index into a value array which can hold up to eight 8-bit values. If bit 4 (MSB) of the index is logic 1, the value is inserted into the G or Y signal only; if bit 4 = 0, the associated value is inserted into all three signals. Two additional bits of the entries in the value array (LSBs of the second byte) determine if the associated events appear as a digital pulse on the HSM_CSYNC and/or VSM outputs.

8.18 I2C-bus interface

only a single byte per address. 2C-bus slave address is deﬁned as 88h.

8.19 Power-down modes

(DOWNA = 1) turns off the digital-to-analog converters and the pixel clock synthesizer. can still be accessed in this mode, however not all registers can be read from or written to. valid pixel clock. The typical supply current in full power-down is approximately 5 mA. simultaneously. If the EIDIV bit is logic 1, it should be set to logic 0 before power-down.

8.20 Programming the graphics acquisition scaler of the video encoder

frame memory isolating the data streams, restrictions apply to the input frame timings. to the input processing. In Slave mode, the encoder receives them. active video times (and the vertical frequencies) need to be the same.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 32 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC The second rule is that there has to be data in the buffer FIFO when the encoder enters the active video area. Therefore, the vertical offset in the input path needs to be a bit shorter than the offset of the encoder. The following gives the set of equations required to program the IC for the most common application: A post processor in Master mode with non-interlaced video input data. Some variables are deﬁned below:

InPix: the number of active pixels per input line
InPpl: the length of the entire input line in pixel clocks
InLin: the number of active lines per input ﬁeld/frame
TPclk: the pixel clock period
RiePclk: the ratio of internal to external pixel clock
OutPix: the number of active pixels per output line
OutLin: the number of active lines per output ﬁeld
TXclk: the encoder clock period (37.037 ns)

8.20.1 TV display window

At 60 Hz, the ﬁrst visible pixel has the index 256, 710 pixels can be encoded; at 50 Hz, the index is 284, 702 pixels can be visible. The output lines should be centred on the screen. It should be noted that the encoder has 2 clocks per pixel; seeTable76. ADWHS = 256 + 710− OutPix (60 Hz); ADWHS = 284 + 702− OutPix (50 Hz); ADWHE = ADWHS + OutPix × 2 (all frequencies) For vertical, the procedure is the same. At 60 Hz, the ﬁrst line with video information is number 19, 240 lines can be active. For 50 Hz, the numbers are 23 and 287; see Table84. (60 Hz); (50 Hz); LAL = FAL + OutLin (all frequencies) Most TV sets use overscan, and not all pixels are visible. There is no standard for the factor, it is highly recommended to make the number of output pixels and lines adjustable. A reasonable underscan factor is 10 %, giving approximately 640 output pixels per line.

8.20.2 Input frame and pixel clock

The total number of pixel clocks per line and the input horizontal offset need to be chosen next. The only constraint is that the horizontal blanking has at least 10 clock pulses. The required pixel clock frequency can be determined in the following way: Due to the limited internal FIFO size, the input path has to provide all pixels in the same time frame as the encoders vertical active time. The scaler also has to process the ﬁrst and last border lines for the anti-ﬂicker function. Thus: FAL 19 240 OutLin–

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 33 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC (60 Hz) (50 Hz) and for the pixel clock generator (all frequencies); seeTable88 and Table89. The divider PCLE should be set according toTable89. PCLI may be set to a lower or the same value. Setting a lower value means that the internal pixel clock is higher and the data get sampled up. The difference may be 1 at 640× 480 pixels resolution and 2 at resolutions with 320 pixels per line as a rule of thumb. This allows horizontal upscaling by a maximum factor of 2 respectively 4 (this is the parameter RiePclk). (all frequencies) The equations ensure that the last line of the ﬁeld has the full number of clock cycles. Many graphic controllers require this. Note that the bit PCLSY needs to be set to ensure that there is not even a fraction of a clock left at the end of the ﬁeld.

8.20.3 Horizontal scaler

XOFS can be chosen arbitrarily, the condition being that XOFS + XPIX≤ HLEN is fulﬁlled. Values given by the VESA display timings are preferred. HLEN = InPpl× RiePclk− 1 XINC needs to be rounded up, it needs to be set to 0 for a scaling factor of 1.

8.20.4 Vertical scaler

The input vertical offset can be taken from the assumption that the scaler should just have ﬁnished writing the ﬁrst line when the encoder starts reading it: (60 Hz) (50 Hz) In most cases the vertical offsets will be the same for odd and even ﬁelds. The results should be rounded down. YPIX = InLin YSKIP deﬁnes the anti-ﬂicker function. 0 means maximum ﬂicker reduction but minimum vertical bandwidth, 4095 gives no ﬂicker reduction and maximum bandwidth. Note that the maximum value for YINC is 4095. It might be necessary to reduce the value of YSKIP to fulﬁl this requirement. TPclk 262.5 1716× TXclk× InPpl integer× InLin 2+ TPclk 312.5 1728× TXclk× InPpl integer× InLin 2+ PCL TXclk

20 PCLE+×=

YOFS FAL 1716× TXclk×

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 34 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC When YINC = 0 it sets the scaler to scaling factor 1. The initial weighting factors must not be set to 0 in this case. YIWGTE may go negative. In this event, YINC should be added and YOFSE incremented. This can be repeated as often as necessary to make YIWGTE positive. It should be noted that these equations assume that the input is non-interlaced but the output is interlaced. If the input is interlaced, the initial weighting factors need to be adapted to obtain the proper phase offsets in the output frame. If vertical upscaling beyond the upper capabilities is required, the parameter YUPSC may be set to logic 1. This extends the maximum vertical scaling factor by a factor of 2. Only the parameter YINC is affected, it needs to be divided by two to get the same effect. There are restrictions in this mode:

The vertical ﬁlter YFIL is not available in this mode; the circuit will ignore this value
The horizontal blanking needs to be long enough to transfer an output line between 2 memory locations. This is 710 internal pixel clocks Or the upscaling factor needs to be limited to 1.5 and the horizontal upscaling factor is also limited to less than∼1.5. In this case a normal blanking length is sufﬁcient

8.21 Input levels and formats

The SAA7108AE; SAA7109AE accepts digital Y , CB,C R or RGB data with levels (digital codes) in accordance with‘ITU-R BT.601’. An optional gain adjustment also allows to accept data with the full level swing of 0 to 255. For C and CVBS outputs, deviating amplitudes of the color difference signals can be compensated for by independent gain control setting, while gain for luminance is set to predeﬁned values, distinguishable for 7.5 IRE set-up or without set-up. The RGB, respectively C R -Y -CB path features an individual gain setting for luminance (GY) and color difference signals (GCD). Reference levels are measured with a color bar, 100 % white, 100 % amplitude and 100 % saturation. The encoder section of the SAA7108AE; SAA7109AE has special input cells for the VGC port. They operate at a wider supply voltage range and have a strict input threshold at 1⁄2VDD(DVO) . To achieve full speed of these cells, the EIDIV bit needs to be set to logic 1. Note that the impedance of these cells is approximately 6 kΩ . This may cause trouble with the bootstrapping pins of some graphic chips. So the power-on reset forces the bit to logic 0, the input impedance is regular in this mode. YINC OutLin × 4096×= YIWGTO YINC YIWGTE YINC YSKIP–

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 10. ‘ITU-R BT.601’ signal component levels Table 11. Usage of bits SLOT and EDGE Table 12. Pin assignment for input format 0

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 13. Pin assignment for input format 1 Table 14. Pin assignment for input format 2 Table 15. Pin assignment for input format 3 Table 16. Pin assignment for input format 4

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 17. Pin assignment for input format 5[1] Table 18. Pin assignment for input format 6 Table 16. Pin assignment for input format 4 …continued

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 38 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC 9. Functional description of digital video decoder part

9.1 Decoder

9.1.1 Analog input processing

The SAA7108AE; SAA7109AE offers six analog signal inputs, two analog main channels with source switch, clamp circuit, analog ampliﬁer, anti-alias ﬁlter and video 9-bit CMOS ADC; see Figure16.

9.1.2 Analog control circuits

The anti-alias ﬁlters are adapted to the line-locked clock frequency via a ﬁlter control circuit. The characteristic is shown inFigure13. During the vertical blanking period gain and clamping control are frozen.

9.1.2.1 Clamping

The clamp control circuit controls the correct clamping of the analog input signals. The coupling capacitor is also used to store and ﬁlter the clamping voltage. An internal digital clamp comparator generates the information with respect to clamp-up or clamp-down. The clamping levels for the two ADC channels are ﬁxed for luminance (60) and chrominance (128). Clamping time in normal use is set with the HCL pulse on the back porch of the video signal; see Figure14 andFigure15.

9.1.2.2 Gain control

The gain control circuit receives (via the I2C-bus) the static gain levels for the two analog ampliﬁers or controls one of these ampliﬁers automatically via a built-in Automatic Gain Control (AGC) as part of the Analog Input Control (AICO). The AGC for luminance is used to amplify a CVBS or Y signal to the required signal amplitude, matched to the ADCs input voltage range. The AGC active time is the sync bottom of the video signal. Fig 13. Anti-alias ﬁlter f (MHz) 0 1242 6 10 14 8 mgd138 -18 -30 -12 -24 -36 V (dB) -42

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 39 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Signal (white) peak control limits the gain at signal overshoots. The inﬂuence of supply voltage variation within the speciﬁed range is automatically eliminated by clamping and automatic gain control. The ﬂow charts show more details of the AGC; see Figure17 and Figure18. Fig 14. Analog line with clamp (HCL) and gain range (HSY) Fig 15. Automatic gain range HCL mgl065HSY analog line blanking TV line 255 GAIN CLAMP analog input level controlled ADC input level maximum minimum range 9 dB0 dB 0 dB mhb325 +3 dB -6 dB

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 41 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC X = system variable. Y= AGV − FGV  > GUDL. GUDL = gain update level (adjustable). VBLK = vertical blanking pulse. HSY = horizontal sync pulse. AGV = actual gain value. FGV = frozen gain value. Fig 17. Gain ﬂow chart ANALOG INPUT AMPLIFIER ANTI-ALIAS FILTER ADC LUMA/CHROMA DECODER X HSY > 510 > 510 < 1< 4 > 496 X = 0 X = 1 −1/LLC2 +1/LLC2 −1/LLC2 +/− 0+1/F +1/L GAIN ACCUMULATOR (18 BITS) ACTUAL GAIN VALUE 9-BIT (AGV) [−3/+6 dB] X STOP HSY Y UPDATE FGV mhb728 AGV GAIN VALUE 9-BIT 1 0 1 0 1 0 1 0 1 0 1 0 VBLK1 0NO ACTION DACgain HOLDG

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 42 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC WIPE = white peak level (254). SBOT = sync bottom level (1). CLL = clamp level [60 Y (128 C)]. HSY = horizontal sync pulse. HCL = horizontal clamp pulse. Fig 18. Clamp and gain ﬂow + CLAMP − CLAMP NO CLAMP 10 10 01 10 mgc647 fast − GAIN slow + GAIN+ GAIN − GAIN HCL HSY ADC < SBOT > WIPE< CLL ANALOG INPUT GAIN -><- CLAMP VBLKNO BLANKING ACTIVE 10

9.1.3 Chrominance and luminance processing

Fig 19. Chrominance and luminance processing mhb532 CVBS-IN or CHR-IN CODE BRIG[7:0] CONT[7:0] SATN[7:0] HUEC[7:0] DCVF QUADRATURE DEMODULATOR PAL DELAY LINE SECAM RECOMBINATION PHASE DEMODULATOR AMPLITUDE DETECTOR BURST GATE ACCUMULATOR LOOP FILTER LOW-PASS 1 DOWNSAMPLING SUBCARRIER GENERATION 2 FCTC ACGC CGAIN [6:0] IDEL[3:0]RTCO C B-C R ADJUSTMENT SECAM PROCESSING fH /2 switch signal ADAPTIVE COMB FILTER CCOMB YCOMB LDEL BYPS LUFI[3:0] CSTD [2:0] YDEL [2:0] LOW-PASS 2 CHBW CHROMA GAIN CONTROL INTERPOLATION LOW-PASS 3 LUBW QUADRATURE MODULATOR CDTO CSTD [2:0] SUBCARRIER GENERATION 1 CHROMINANCE INCREMENT DTO RESET SUBCARRIER INCREMENT GENERATION AND DIVIDER CHROMINANCE INCREMENT DELAY LDEL YCOMB C B-CR SUBTRACTORDELAY COMPENSATION CVBS-IN or Y-IN CHR LUMINANCE-PEAKING OR LOW-PASS, Y-DELAY ADJUSTMENT LCBW [2:0] Y Y/CVBS DBRI [7:0] DCON [7:0] DSAT [7:0] RAWG [7:0] RAWO [7:0] COLO BRIGHTNESS CONTRAST SATURATION CONTROL RAW DATA GAIN AND OFFSET CONTROL LDEL YCOMB Y-OUT/ CVBS-OUT C B-C R -OUT HREF-OUT SET_RAW SET_VBI SET_RAW SET_VBI SET_RAW SET_VBI SET_RAW SET_VBI C B-C R C B-C R C B-C R

9.1.3.1 Chrominance path

The 9-bit CVBS or chrominance input signal is fed to the input of a quadrature demodulator, where it is multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 1 (0° and 90° phase relationship to the demodulator axis). The frequency is dependent on the chosen color standard. The time-multiplexed output signals of the multipliers are low-pass ﬁltered (low-pass 1). Eight characteristics are programmable via LCBW2 to LCBW0 to achieve the desired bandwidth for the color difference signals (PAL, NTSC) or the 0° and 90° FM signals (SECAM). The chrominance low-pass 1 characteristic also inﬂuences the grade of cross luminance reduction during horizontal color transients (large chrominance bandwidth means strong suppression of cross luminance). If the Y -comb ﬁlter is disabled by YCOMB = 0 the ﬁlter inﬂuences directly the width of the chrominance notch within the luminance path (a large chrominance bandwidth means wide chrominance notch resulting in a lower luminance bandwidth). The low-pass ﬁltered signals are fed to the adaptive comb ﬁlter block. The chrominance components are separated from the luminance via a two-line vertical stage (four lines for PAL standards) and a decision logic between the ﬁltered and the non-ﬁltered output signals. This block is bypassed for SECAM signals. The comb ﬁlter logic can be enabled independently for the succeeding luminance and chrominance processing by YCOMB (subaddress 09h, bit 6) and/or CCOMB (subaddress 0Eh, bit 0). It is always bypassed during VBI or raw data lines programmable by the LCRn registers (subaddresses 41h to 57h); see Section9.2. The separated CB-CR components are further processed by a second ﬁlter stage (low-pass 2) to modify the chrominance bandwidth without inﬂuencing the luminance path. Its characteristic is controlled by CHBW (subaddress 10h, bit 3). For the complete transfer characteristic of low-pass ﬁlters 1 and 2, see Figure20 andFigure21. The SECAM processing (bypassed for QAM standards) contains the following blocks:

Baseband ‘bell’ ﬁlters to reconstruct the amplitude and phase equalized 0° and 90° FM signals
Phase demodulator and differentiator (FM-demodulation)
De-emphasis ﬁlter to compensate the pre-emphasized input signal, including frequency offset compensation (DB or DR white carrier values are subtracted from the signal, controlled by the SECAM switch signal) The succeeding chrominance gain control block ampliﬁes or attenuates the C B-CR signal according to the required ITU 601/656 levels. It is controlled by the output signal from the amplitude detection circuit within the burst processing block. The burst processing block provides the feedback loop of the chrominance PLL and contains the following:
Burst gate accumulator
Color identiﬁcation and color killer
Comparison nominal/actual burst amplitude (PAL/NTSC standards only)
Loop ﬁlter chrominance gain control (PAL/NTSC standards only)

Loop ﬁlter chrominance PLL (only active for PAL/NTSC standards)
PAL/SECAM sequence detection, H/2-switch generation The increment generation circuit produces the Discrete Time Oscillator (DTO) increment for both subcarrier generation blocks. It contains a division by the increment of the line-locked clock generator to create a stable phase-locked sine signal under all conditions (e.g. for non-standard signals). The PAL delay line block eliminates crosstalk between the chrominance channels in accordance with the PAL standard requirements. For NTSC color standards the delay line can be used as an additional vertical ﬁlter. If desired, it can be switched off by DCVF = 1. It is always disabled during VBI or raw data lines programmable by the LCRn registers (subaddresses 41h to 57h); see Section9.2. The embedded line delay is also used for SECAM recombination (cross-over switches).

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 46 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 20. Transfer characteristics of the chrominance low-pass at CHBW = 0 mhb533 -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) (1) (2) (3) (4) (5) (6) (7) (8)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 47 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 21. Transfer characteristics of the chrominance low-pass at CHBW = 1 mhb534 -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) (1) (2) (3) (4) (5) (6) (7) (8)

9.1.3.2 Luminance path

The rejection of the chrominance components within the 9-bit CVBS or Y input signal is achieved by subtracting the remodulated chrominance signal from the CVBS input. The comb ﬁltered CB-CR components are interpolated (upsampled) by the low-pass 3 block. Its characteristic is controlled by LUBW (subaddress 09h, bit 4) to modify the width of the chrominance ‘notch’ without inﬂuencing the chrominance path. The programmable frequency characteristics available, in conjunction with the LCBW2 to LCBW0 settings, can be seen in Figure22 toFigure25. It should be noted that these frequency curves are only valid for Y -comb disabled ﬁlter mode (YCOMB = 0). In comb ﬁlter mode the frequency response is ﬂat. The center frequency of the notch is automatically adapted to the chosen color standard. The interpolated C B-CR samples are multiplied by two time-multiplexed subcarrier signals from the subcarrier generation block 2. This second DTO is locked to the ﬁrst subcarrier generator by an increment delay circuit matched to the processing delay, which is different for PAL and NTSC standards according to the chosen comb ﬁlter algorithm. The two modulated signals are ﬁnally added to build the remodulated chrominance signal. The frequency characteristic of the separated luminance signal can be further modiﬁed by the succeeding luminance ﬁlter block. It can be conﬁgured as peaking (resolution enhancement) or low-pass block by LUFI3 to LUFI0 (subaddress 09h, bits 3 to 0). The 16 resulting frequency characteristics can be seen in Figure26. The LUFI3 to LUFI0 settings can be used as a user programmable sharpness control. The luminance ﬁlter block also contains the adjustable Y -delay part; programmable by YDEL2 to YDEL0 (subaddress 11h, bits 2 to 0).

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 49 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 22. Transfer characteristics of the luminance notch ﬁlter in 3.58 MHz mode (Y-comb ﬁlter disabled) at LUBW = 0 mhb535 -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) (5) (6) (7) (8) (1) (2) (3) (4)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 50 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 23. Transfer characteristics of the luminance notch ﬁlter in 3.58 MHz mode (Y-comb ﬁlter disabled) at LUBW = 1 mhb536 -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) (5) (6) (7) (8) (1) (2) (3) (4)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 51 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 24. Transfer characteristics of the luminance notch ﬁlter in 4.43 MHz mode (Y-comb ﬁlter disabled) at LUBW = 0 mhb537 -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) (5) (6) (7) (8) (1) (2) (3) (4)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 52 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 25. Transfer characteristics of the luminance notch ﬁlter in 4.43 MHz mode (Y-comb ﬁlter disabled) at LUBW = 1 mhb538 -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) -60 -57 -54 -51 -48 -45 -42 -39 -36 -33 -30 -27 -24 -21 -18 -15 -12 V (dB) f (MHz) (5) (6) (7) (8) (1) (2) (3) (4)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 53 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 26. Transfer characteristics of the luminance peaking/low-pass ﬁlter (sharpness) mhb539 V (dB) V (dB) f (MHz) f (MHz) (8) (7) (6) (5) (4) (3) (2) (1) (9) (10) (11) (12) (13) (14) (15) (16) −39 −36 −33 −30 −27 −24 −21 −18 −15 −12

9.1.3.3 Brightness Contrast Saturation (BCS) control and decoder output levels

The resulting Y (CVBS) and CB-CR signals are fed to the BCS block, which contains the following functions:

Chrominance saturation control by DSAT7 to DSAT0
Luminance contrast and brightness control by DCON7 to DCON0 and DBRI7 to DBRI0
Raw data (CVBS) gain and offset adjustment by RAWG7 to RAWG0 and R A W O 7t oR A W O 0
Limiting Y -CB-CR or CVBS to the values 1 (minimum) and 254 (maximum) to fulﬁl ‘ITU Recommendation 601/656’ ‘ITU Recommendation 601/656’digital levels with default BCS (decoder) settings DCON[7:0] = 44h, DBRI[7:0] = 80h and DSAT[7:0] = 40h. Equations for modiﬁcation to the Y -CB-CR levels via BCS control I2C-bus bytes DBRI, DCON and DSAT. Luminance: Chrominance: It should be noted that the resulting levels are limited to 1 to 254 in accordance with‘ITU Recommendation 601/656’ Fig 27. Y-CB -CR range for scaler input and X port output 001aac241 +128 LUMINANCE 100 % +16 +235 black white +255 001aac480 +255 +212 +128 C B-COMPONENT +44 +240 +16 blue 100 % blue 75 % yellow 75 % yellow 100 % colorless 001aac481 +255 +212 +128 C R -COMPONENT +44 +240 +16 red 100 % red 75 % cyan 75 % cyan 100 % colorless Y OUT Int DCON C R C B() OUT Int DSAT

9.1.4 Synchronization

The preﬁltered luminance signal is fed to the synchronization stage. Its bandwidth is further reduced to 1 MHz by a low-pass ﬁlter. The sync pulses are sliced and fed to the phase detectors where they are compared with the sub-divided clock frequency. The resulting output signal is applied to the loop ﬁlter to accumulate all phase deviations. Internal signals (e.g. HCL and HSY) are generated in accordance with analog front-end requirements. The loop ﬁlter signal drives an oscillator to generate the line frequency control signal LFCO; see Figure29. The detection of ‘pseudo syncs’ as part of the Macrovision copy protection standard is also achieved within the synchronization circuit. The result is reported as ﬂag COPRO within the decoder status byte at subaddress 1Fh.

9.1.5 Clock generation circuit

The internal CGC generates all clock signals required for the video input processor. The internal signal LFCO is a digital-to-analog converted signal provided by the horizontal PLL. It is the multiple of the line frequency:

6.75 MHz = 429× fH (50 Hz), or
6.75 MHz = 432× fH (60 Hz) The LFCO signal is multiplied by a factor of 2 and 4 in the internal PLL circuit (including phase detector, loop ﬁltering, VCO and frequency divider) to obtain the output clock signals. The rectangular output clocks have a 50 % duty factor. CVBS levels with default settings RAWG[7:0] = 64 and RAWO[7:0] = 128. Equation for modiﬁcation of the raw data levels via bytes RAWG and RAWO: It should be noted that the resulting levels are limited to 1 to 254 in accordance with ‘ITU Recommendation 601/656’. a. Sources containing 7.5 IRE black level offset (e.g. NTSC M). b. Sources not containing black level offset. Fig 28. CVBS (raw data) range for scaler input, data slicer and X port output LUMINANCE +255 +209 +71 +60 white sync bottom black shoulder black SYNC 001aac244 LUMINANCE +255 +199 +60 white sync bottom black shoulder = black SYNC 001aac245 CVBS OUT Int RAWG

9.1.6 Power-on reset and CE input

reset other circuits of the digital TV system. to active, while the other signals have to be activated via programming. Table 19. Decoder clock frequencies

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 57 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC POC = power-on control. CE = chip enable input. XTALO = crystal oscillator output. LLCINT = internal system clock. RESINT = internal reset. LLC = line-locked clock output. RES = reset output. Fig 30. Power-on control circuit 001aad709

128 LLC896 LLC

digital delaysome ms 20 µs to 200 µs PLL delay < 1 ms RES (internal reset) LLC RESINT LLCINT XTALO CE POC V DDA POC LOGIC ANALOG POC V DDD DIGITAL POC DELAY CLOCK PLL CE LLC CLK0 RESINT RES

9.2 Decoder output formatter

RTS0 and RTS1) and the expansion port (XRH, XRV and XDQ). Section 11.2.4.2 “Subaddresses 41hto57h”).

50 Hz sources (with FOFF = 0) and VOFF[8:0] = 06h for 60 Hz sources (with FOFF = 1),

Table 20. Data formats at decoder output

1 European closed caption raw

2 Video Programming Service (VPS) raw

4 US teletext (WST) raw

5 US closed caption (line 21) raw

7 CVBS data raw

9 VITC/EBU time codes (Europe) raw

10 VITC/SMPTE time codes (USA) raw

12 US NABTS raw

13 MOJI (Japanese) raw

14 Japanese format switch (L20/22) raw

xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 59 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Vertical line offset, VOFF[8:0] = 06h (subaddresses 5Bh[4] and 5Ah[7:0]); horizontal pixel offset, HOFF[10:0] = 347h (subaddresses 5Bh[2:0] and 59h[7:0]); FOFF = 1 (subaddress 5Bh[7]) Fig 31. Relationship of LCR to line numbers in 525 lines/60 Hz systems 521 522 active video active video equalization pulses equalization pulses equalization pulses equalization pulses serration pulses serration pulses 5 2 3 5 2 4 5 2 5 12 345 6789 259 260 261 2 4 2 345 6789 262 263 264 265 266 267 268 269 270 271 272 LINE NUMBER (1st FIELD) LINE NUMBER (2nd FIELD) LCR 001aad425 10 11 nominal VBI lines F1 nominal VBI lines F2 active video active video 12 13 14 15 16 17 18 19 20 21 22 23 24 25LINE NUMBER (1st FIELD) LINE NUMBER (2nd FIELD) LCR 273 274 275 276 277 278 279 280 281 282 283 284 285 286 287 288 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Vertical line offset, VOFF[8:0] = 03h (subaddresses 5Bh[4] and 5Ah[7:0]); horizontal pixel offset, HOFF[10:0] = 347h (subaddresses 5Bh[2:0] and 59h[7:0]); FOFF = 0 (subaddress 5Bh[7]) Fig 32. Relationship of LCR to line numbers in 625 lines/50 Hz systems 621 622 active video active video equalization pulses equalization pulses equalization pulses equalization pulses serration pulses serration pulses 623 624 625 1 2 3 4 5LINE NUMBER (1st FIELD) LINE NUMBER (2nd FIELD) LCR 309 310 311 312 313 314 315 316 317 318 224 34 5 001aad426 nominal VBI lines F1 nominal VBI lines F2 active video active video 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25LINE NUMBER (1st FIELD) LINE NUMBER (2nd FIELD) LCR 319 320 321 322 323 324 325 326 327 328 329 330 331 332 333 334 335 336 337 338 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 61 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC (1) The inactive going edge of the V123 signal indicates whether the ﬁeld is odd or even. If HREF is active during the falling edge of V123, the ﬁeld is ODD (ﬁeld 1). If HREF is inactive during the falling edge of V123, the ﬁeld is EVEN. The speciﬁc position of the slope is dependent on the internal processing delay and may change a few clock cycles from version to version. The control signals listed above are available on pins RTS0, RTS1, XRH and XRV according to Table21. For further information seeTable160,Table161 andTable162. Fig 34. Vertical timing diagram for 60 Hz/525 line systems mhb541 VGATE VSTO [8:0] = 101h VSTA [8:0] = 011h(a) 1st field CVBS ITU counting single field counting ... ... 525 262 FID HREF F_ITU656 V123 (1) VGATE CVBS ITU counting single field counting FID HREF F_ITU656 V123 (1) VSTO [8:0] = 101h VSTA [8:0] = 011h(b) 2nd field 266 267 268 269 270 271 272 ... ... 284 265 264 263 263 262 262 285

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 62 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC The signals HREF , HS, CREF2 and CREF are available on pins RTS0 and/or RTS1 (see Table160 andTable161); their polarity can be inverted via RTP0 and/or RTP1. The signals HREF and HS are available on pin XRH (seeTable162). Fig 35. Horizontal timing diagram (50/60 Hz) 108 −107 107 −106 mhb542 CVBS input 140 × 1/LLC 5 × 2/LLC expansion port data output 12 × 2/LLC 720 × 2/LLC 144 × 2/LLC 138 × 2/LLC720 × 2/LLC burst processing delay ADC to expansion port: 2 × 2/LLC 2 × 2/LLC HREF (60 Hz) HS (60 Hz) sync clipped 16 × 2/LLC 1 × 2/LLC programming range (step size: 8/LLC) programming range (step size: 8/LLC) HS (50 Hz) HREF (50 Hz) CREF CREF250 Hz CREF CREF2 60 Hz

9.3 Scaler

The High Performance video Scaler (HPS) is based on the system as implemented in previous products (e.g. SAA7140), but with some aspects enhanced. Vertical upsampling is supported and the processing pipeline buffer capacity is enhanced, to allow more ﬂexible video stream timing at the image port, discontinuous transfers and handshake. The internal data ﬂow from block to block is discontinuous dynamically, due to the scaling process. The ﬂow is controlled by internal data valid and data request ﬂags (internal handshake signalling) between the sub-blocks; therefore the entire scaler acts as a pipeline buffer. Depending on the actual programmed scaling parameters the effective buffer can exceed to an entire line. The access/bandwidth requirements to the VGA frame buffer are reduced signiﬁcantly. The high performance video scaler in the SAA7108AE; SAA7109AE has the following major blocks:

Acquisition control (horizontal and vertical timer) and task handling (the region/ﬁeld/frame based processing)
Prescaler, for horizontal downscaling by an integer factor, combined with appropriate band limiting ﬁlters, especially anti-aliasing for CIF format
Brightness, saturation and contrast control for scaled output data
Line buffer, with asynchronous read and write, to support vertical upscaling (e.g. for videophone application, converting 240 into 288 lines, Y -C B-CR 4:2:2 )
Vertical scaling, with phase accurate Linear Phase Interpolation (LPI) for zoom and downscale, or phase accurate Accumulation Mode (ACM) for large downscaling ratios and better anti-alias suppression
Variable Phase Delay (VPD), operates as horizontal phase accurate interpolation for arbitrary non-integer scaling ratios, supporting conversion between square and rectangular pixel sampling
Output formatter for scaled Y -CB-CR 4:2:2 ,Y - CB-CR 4:1:1a n dY only (format also used for raw data)
FIFO, 32-bit wide, with 64 pixel capacity in Y -CB-CR formats
Output interface, 8-bit or 16-bit (only if extended by H port) data pins wide, synchronous or asynchronous operation, with stream events on discrete pins, or coded in the data stream The overall H and V zooming (HV_zoom) is restricted by the input/output data rate relationships. With a safety margin of 2 % for running in and running out, the maximum HV_zoom is equal to: For example: 1. Input from decoder: 50 Hz, 720 pixel, 288 lines, 16-bit data at 13.5 MHz data rate, 1 cycle per pixel; output: 8-bit data at 27 MHz, 2 cycles per pixel; the maximum HV_zoom is equal to:

0.98 T _input_ field T _v_blanking–

0.98 20 ms 24– 64 µ s×

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 64 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC 2. Input from X port: 60 Hz, 720 pixel, 240 lines, 8-bit data at 27 MHz data rate (ITU 656), 2 cycles per pixel; output via I + H port: 16-bit data at 27 MHz clock, 1 cycle per pixel; the maximum HV_zoom is equal to: The video scaler receives its input signal from the video decoder or from the expansion port (X port). It gets 16-bit Y -CB-CR 4 : 2 : 2 input data at a continuous rate of 13.5 MHz from the decoder. A discontinuous data stream can be accepted from the expansion port (X port), normally 8-bit wide ITU 656 such as Y -C B-CR data, accompanied by a pixel qualiﬁer on XDQ. The input data stream is sorted into two data paths, one for luminance (or raw samples) and one for time-multiplexed chrominance CB and CR samples. A Y -CB-CR 4:1:1 input format is converted to 4:2:2 f o r the horizontal prescaling and vertical ﬁlter scaling operation. The scaler operation is deﬁned by two programming pages A and B, representing two different tasks, that can be applied ﬁeld alternating or to deﬁne two regions in a ﬁeld (e.g. with different scaling range, factors and signal source during odd and even ﬁelds). Each programming page contains control for:

Signal source selection and formats
Task handling and trigger conditions
Input and output acquisition window deﬁnition
H-prescaler, V-scaler and H-phase scaling Raw VBI data is handled as a speciﬁc input format and needs its own programming page (equals own task). In VBI pass through operation the processing of prescaler and vertical scaling has to be disabled, however, the horizontal ﬁne scaling VPD can be activated. Upscaling (oversampling, zooming), free of frequency folding, up to a factor of 3.5 can be achieved, as required by some software data slicing algorithms. These raw samples are transported through the image port as valid data and can be output as Y only format. The lines are framed by SAV and EAV codes.

9.3.1 Acquisition control and task handling (subaddresses 80h, 90h, 91h,

94h to 9Fh and C4h to CFh) The acquisition control receives horizontal and vertical synchronization signals from the decoder section or from the X port. The acquisition window is generated via pixel and line counters at the appropriate places in the data path. From X port only qualiﬁed pixels and lines (lines with qualiﬁed pixel) are counted. The acquisition window parameters are as follows:

Signal source selection regarding input video stream and formats from the decoder, or from the X port (programming bits SCSRC[1:0] 91h[5:4] and FSC[2:0] 91h[2:0]) Remark : The input of raw VBI data from the internal decoder should be controlled via the decoder output formatter and the LCR registers; seeSection9.2 0.98 16.666 ms 22– 64 µ s×

Vertical offset deﬁned in lines of the video source, parameter YO[11:0] 99h[3:0] 98h[7:0]
Vertical length deﬁned in lines of the video source, parameter YS[11:0] 9Bh[3:0] 9Ah[7:0]
Vertical length deﬁned in number of target lines, as a result of vertical scaling, parameter YD[11:0] 9Fh[3:0] 9Eh[7:0]
Horizontal offset deﬁned in number of pixels of the video source, parameter XO[11:0] 95h[3:0] 94h[7:0]
Horizontal length deﬁned in number of pixels of the video source, parameter XS[11:0] 97h[3:0] 96h[7:0]
Horizontal destination size deﬁned in target pixels after ﬁne scaling, parameter The source start offset (XO11 to XO0 and YO11to YO0) opens the acquisition window, and the target size (XD11 to XD0 and YD11 to YD0) closes the window, however the window is cut vertically if there are less output lines than expected. The trigger events for the pixel and line counts are the horizontal and vertical reference edges as deﬁned in subaddress 92h. The task handling is controlled by subaddress 90h; see Section9.3.1.2.

9.3.1.1 Input ﬁeld processing

The trigger event for the ﬁeld sequence detection from external signals (X port) are deﬁned in subaddress 92h. From the X port the state of the scalers horizontal reference signal at the time of the vertical reference edge is taken as ﬁeld sequence identiﬁer FID. For example, if the falling edge of the XRV input signal is the reference and the state of XRH input is logic 0 at that time, the detected ﬁeld ID is logic 0. The bits XFDV[92h[7]] and XFDH[92h[6]] deﬁne the detection event and state of the ﬂag from the X port. For the default setting of XFDV and XFDH at ‘00’ the state of the horizontal input at the falling edge of the vertical input is taken. The scaler directly gets a corresponding ﬁeld ID information from the SAA7108AE; SAA7109AE decoder path. The FID ﬂag is used to determine whether the ﬁrst or second ﬁeld of a frame is going to be processed within the scaler and it is also used as trigger condition for the task handling (see bits STRC[1:0] 90h[1:0]). According to ITU 656, when FID is at logic 0 means ﬁrst ﬁeld of a frame. To ease the application, the polarities of the detection results on the X port signals and the internal decoder ID can be changed via XFDH. As the V-sync from the decoder path has a half line timing (due to the interlaced video signal), but the scaler processing only knows about full lines, during 1st ﬁelds from the decoder the line count of the scaler possibly shifts by one line, compared to the 2nd ﬁeld. This can be compensated for by switching the vertical trigger event, as deﬁned by XDV0, to the opposite V-sync edge or by using the vertical scalers phase offsets. The vertical timing of the decoder can be seen in Figure33 andFigure34. As the horizontal and vertical reference events inside the ITU 656 data stream (from X port) and the real-time reference signals from the decoder path are processed differently, the trigger events for the input acquisition also have to be programmed differently.

9.3.1.2 Task handling

The task handler controls the switching between the two programming register sets. It is controlled by subaddresses 90h and C0h. A task is enabled via the global control bits TEA[80h[4]] and TEB[80h[5]]. The handler is then triggered by events which can be deﬁned for each register set. In the event of a programming error the task handling and the complete scaler can be reset to the initial states by setting the software reset bit SWRST[88h[5]] to logic 0. Especially if the programming registers, related acquisition window and scaler are reprogrammed while a task is active, a software resetmust be performed after programming. Contrary to the disabling/enabling of a task, which is evaluated at the end of a running task, when SWRST is at logic 0 it sets the internal state machines directly to their idle states. The start condition for the handler is deﬁned by bits STRC[1:0] 90h[1:0] and means: start immediately, wait for next V-sync, next FID at logic 0 or next FID at logic 1. The FID is evaluated, if the vertical and horizontal offsets are reached. When RPTSK[90h[2]] is at logic 1 the actual running task is repeated (under the deﬁned trigger conditions), before handing control over to the alternate task. To support ﬁeld rate reduction, the handler is also enabled to skip ﬁelds (bits FSKP[2:0] 90h[5:3]) before executing the task. A TOGGLE ﬂag is generated (used for the correct output ﬁeld processing), which changes state at the beginning of a task, every time a task is activated; examples are given in Section9.3.1.3. Remarks :

To activate a task the start condition must be fulﬁlled and the acquisition window offsets must be reached. For example, in case of ‘start immediately’, and two regions are deﬁned for one ﬁeld, the offset of the lower region must be greater than (offset + length) of the upper region, if not, the actual counted H and V position at the end of the upper task is beyond the programmed offsets and the processing will ‘wait for next V’.

Table 22. Processing trigger and start

Description

Internal decoder: The processing triggers at the falling edge of the V123 pulse [seeFigure33 (50 Hz) andFigure34 (60 Hz)], and starts earliest with the rising edge of the decoder HREF at line number: 0 1 0 4/7 (50/60 Hz, 1st ﬁeld), respectively 3/6 (50/60 Hz, 2nd ﬁeld) (decoder count) 0 0 0 2/5 (50/60 Hz, 1st ﬁeld), respectively 2/5 (50/60 Hz, 2nd ﬁeld) (decoder count)

000 External ITU 656 stream: The processing starts earliest with SAV at

line number 23 (50 Hz system), respectively line 20 (60 Hz system) (according to ITU 656 count)

Basically the trigger conditions are checked, when a task is activated. It is important to realize, that they are not checked while a task is inactive. So you can not trigger to next logic 0 or logic 1 with overlapping offset and active video ranges between the tasks (e.g. task A STRC[1:0] = 2, YO[11:0] = 310 and task B STRC[1:0] = 3, YO[11:0] = 310 results in an output ﬁeld rate of 50⁄3 Hz).
After power-on or software reset (via SWRST[88h[5]]) task B gets priority over task A

9.3.1.3 Output ﬁeld processing

As a reference for the output ﬁeld processing, two signals are available for the back-end hardware. These signals are the input ﬁeld ID from the scaler source and a TOGGLE ﬂag, which Using a single or both tasks and reducing the ﬁeld or frame rate with the task handling function, the TOGGLE information can be used to reconstruct an interlaced scaled picture at a reduced frame rate. The TOGGLE ﬂag is not synchronized to the input ﬁeld detection, as it is only dependent on the interpretation of this information by the external hardware, whether the output of the scaler is processed correctly; see Section9.3.3. When OFIDC = 0, the scalers input ﬁeld ID is available as output ﬁeld ID on bit 6 of SAV and EAV, respectively on pin IGP0 (IGP1), if the FID output is selected. When OFIDC[90h[6]] = 1, the TOGGLE information is available as output ﬁeld ID on bit 6 of SAV and EAV, respectively on pin IGP0 (IGP1), if the FID output is selected. Additionally the bit 7 of SAV and EAV can be deﬁned via CONLH[90h[7]]. CONLH[90h[7]] = 0 (default) sets bit 7 to logic 1, a logic 1 inverts the SAV/EAV bit 7. So it is possible to mark the output of both tasks by different SAV/EAV codes. This bit can also be seen as ‘task ﬂag’ on pins IGP0 (IGP1), if TASK output is selected.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] Single task every ﬁeld; OFIDC = 0; subaddress 90h at 40h; TEB[80h[5]] = 0. [2] Tasks are used to scale to different output windows, priority on task B after SWRST. 1⁄2 frame rate; OFIDC = 0; subaddresses 90h at 43h and C0h at 42h. [4] In examples 3 and 4 the association between input FID and tasks can be ﬂipped, dependent on which time the SWRST is de-asserted. subaddresses 90h at 41h and C0h at 45h. [6] Task A and B at1⁄3 frame rate of equidistant motion phases; OFIDC = 1; subaddresses 90h at 41h and C0h at 49h. [8] It is assumed that input/output FID = 0 (= upper lines); UP = upper lines; LO = lower lines. [9] O = data output; NO = no output.

9.3.2 Horizontal scaling

compromise between visible bandwidth and alias suppression can be determined. Table 23. Examples for ﬁeld processing

9.3.2.1 Horizontal prescaler (subaddresses A0h to A7h and D0h to D7h)

The prescaling function consists of an FIR anti-alias ﬁlter stage and an integer prescaler, which creates an adaptive prescale dependent low-pass ﬁlter to balance the sharpness and aliasing effects. The FIR preﬁlter stage implements different low-pass characteristics to reduce the anti-alias for downscales in the range of 1 to 1⁄2. A CIF optimized ﬁlter is built-in, which reduces artefacts for CIF output formats (to be used in combination with the prescaler set to 1⁄2 scale); seeTable24. The function of the prescaler is deﬁned by:

An integer prescaling ratio XPSC[5:0] A0h[5:0] (equals 1 to 63), which covers the integer downscale range 1 to1⁄63
An averaging sequence length XACL[5:0] A1h[5:0] (equals 0 to 63); range 1 to 64
A DC gain renormalization XDCG[2:0] A2h[2:0]; 1 down to1⁄128
The bit XC2_1[A2h[3]], which deﬁnes the weighting of the incoming pixels during the averaging process: The prescaler creates a prescale dependent FIR low-pass, with up to 64 + 7 ﬁlter taps. The parameter XACL[5:0] can be used to vary the low-pass characteristic for a given integer prescale of 1⁄XPSC[5:0]. The user can therefore decide between signal bandwidth (sharpness impression) and alias. The equation for the XPSC[5:0] calculation is: Where:
The range is 1 to 63 (value 0 is not allowed)
Npix_in = number of input pixel, and
Npix_out = number of desired output pixel over the complete horizontal scaler The use of the prescaler results in a XACL[5:0] and XC2_1 dependent gain ampliﬁcation. The ampliﬁcation can be calculated according to the equation: DC gain = [(XACL[5:0]− XC2_1) + 1]× (XC2_1 + 1) It is recommended to use sequence lengths and weights, which results in a 2N DC gain ampliﬁcation, as these amplitudes can be renormalized by the XDCG[2:0] controlled shifter of the prescaler. The renormalization range of XDCG[2:0] is 1,1⁄2 down to1⁄128. XPSC 5 :0[] lower integer of Npix _in

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. value = lower integer of4⁄3 × 64). The use of XACL[5:0] is XPSC[5:0] dependent. XACL[5:0] must be < 2× XPSC[5:0]. Figure38 andFigure39 show some resulting frequency characteristics of the prescaler.

2XDCG[2:0] ≥ DC gain
DC gain = [(XACL[5:0]− XC2_1) + 1]× (XC2_1 + 1) For example, if XACL[5:0] = 5, XC2_1 = 1, then the DC gain = 10 and the required XDCG[2:0] = 4. The horizontal source acquisition timing and the prescaling ratio is identical for both the luminance path and chrominance path, but the FIR ﬁlter settings can be deﬁned differently in the two channels. Fade-in and fade-out of the ﬁlters is achieved by copying an original source sample each as ﬁrst and last pixel after prescaling. Figure36 andFigure37 show the frequency characteristics of the selectable FIR ﬁlters.

Table 24. FIR preﬁlter functions

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 71 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 36. Luminance preﬁlter characteristic Fig 37. Chrominance preﬁlter characteristic mhb543 f_sig/f_clock −18 −21 −24 −27 −30 −33 −36 −39 −12 −15 V (dB) −42 (3) (2) (1) (1) PFY[1:0] = 01. (2) PFY[1:0] = 10. (3) PFY[1:0] = 11. mhb544 (3) (2) (1) f_sig/f_clock −18 −21 −24 −27 −30 −33 −36 −39 −12 −15 V (dB) −42

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 72 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC XC2_1 = 0; Zero’s at with XACL = (1), (2), (3), (4) or (5) Fig 38. Examples for prescaler ﬁlter characteristics: effect of increasing XACL[5:0] mhb545 (3)(4)(5) (2) (1) f_sig/f_clock −18 −21 −24 −27 −30 −33 −36 −39 −12 −15 V (dB) −42 fn 1 Fig 39. Examples for prescaler ﬁlter characteristics: setting XC2_1 mhb546 3 dB at 0.25 6 dB at 0.33 (1) XC2_1 = 0 and XACL[5:0] = 1. (2) XC2_1 = 1 and XACL[5:0] = 2. (3) XC2_1 = 0 and XACL[5:0] = 3. (4) XC2_1 = 1 and XACL[5:0] = 4. (5) XC2_1 = 0 and XACL[5:0] = 7. (6) XC2_1 = 1 and XACL[5:0] = 8. f_sig/f_clock −18 −21 −24 −27 −30 −33 −36 −39 −12 −15 V (dB) −42

9.3.2.2 Horizontal ﬁne scaling (variable phase delay ﬁlter; subaddresses A8h to AFh and

can be found. This is signal source and application dependent. chrominance a ﬁlter with 4 taps. Table 25. Example of XACL[5:0] usage

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 74 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Luminance and chrominance scale increments (XSCY[12:0] A9h[4:0] A8h[7:0] and XSCC[12:0] ADh[4:0] ACh[7:0]) are deﬁned independently, but must be set in a 2 : 1 relationship in the actual data path implementation. The phase offsets XPHY[7:0] AAh[7:0] and XPHC[7:0] AEh[7:0] can be used to shift the sample phases slightly. XPHY[7:0] and XPHC[7:0] covers the phase offset range 7.999T to 1⁄32T. The phase offsets should also be programmed in a 2 : 1 ratio. The underlying phase controlling DTO has a 13-bit resolution. According to the equations: and the VPD covers the scale range from 0.125 to zoom 3.5. VPD acts equivalent to a polyphase ﬁlter with 64 possible phases. In combination with the prescaler, it is possible to get very accurate samples from a highly anti-aliased integer downscaled input picture.

9.3.3 Vertical scaling

The vertical scaler of the SAA7108AE; SAA7109AE decoder part consists of a line FIFO buffer for line repetition and the vertical scaler block, which implements the vertical scaling on the input data stream in 2 different operational modes from theoretical zoom by 64 down to icon size 1⁄64. The vertical scaler is located between the BCS and horizontal ﬁne scaler, so that the BCS can be used to compensate the DC gain ampliﬁcation of the ACM mode (see Section9.3.3.2) as the internal RAMs are only 8-bit wide.

9.3.3.1 Line FIFO buffer (subaddresses 91h, B4h and C1h, E4h)

The line FIFO buffer is a dual ported RAM structure for 768 pixels, with asynchronous write and read access. The line buffer can be used for various functions, but not all functions may be available simultaneously. The line buffer can buffer a complete unscaled active video line or more than one shorter lines (only for non-mirror mode), for selective repetition for vertical zoom-up. For zooming up 240 lines to 288 lines e.g., every fourth line is requested (read) twice from the vertical scaling circuitry for calculation. For conversion of a 4:2:0 o r 4:1:0 input sampling scheme (MPEG, video phone, Indeo YUV-9) to ITU like sampling scheme 4: 2 : 2, the chrominance line buffer is read twice or four times, before being reﬁlled again by the source. It has to be preserved by means of the input acquisition window deﬁnition, so that the processing starts with a line containing luminance and chrominance information for4:2:0a n d4:1:0 input. The bits FSC[2:1] 91h[2:1] deﬁne the distance between the Y/C lines. In the event of 4:2:2 a n d 4:1:1 FSC2 and FSC1 have to be set to ‘00’. The line buffer can also be used for mirroring, i.e. for ﬂipping the image left to right, for the vanity picture in video phone applications (bit YMIR[B4h[4]]). In mirror mode only one active prescaled line can be held in the FIFO at a time. The line buffer can be utilized as an excessive pipeline buffer for discontinuous and variable rate transfer conditions at the expansion port or image port. XSCY 12 :0[] 1024 Npix _in

9.3.3.2 Vertical scaler (subaddresses B0h to BFh and E0h to EFh)

Vertical scaling of any ratio from 64 (theoretical zoom) to1⁄63 (icon) can be applied. The vertical scaling block consists of another line delay, and the vertical ﬁlter structure, that can operate in two different modes; Linear Phase Interpolation (LPI) and Accumulation (ACM) mode. These are controlled by YMODE[B4h[0]]:

LPI mode: In the LPI mode (YMODE = 0) two neighboring lines of the source video stream are added together, but weighted by factors corresponding to the vertical position (phase) of the target output line relative to the source lines. This linear interpolation has a 6-bit phase resolution, which equals 64 intra line phases. It interpolates between two consecutive input lines only. The LPI mode should be applied for scaling ratios around 1 (down to 1⁄2),it must be applied for vertical zooming .
ACM mode : The vertical ACM mode (YMODE = 1) represents a vertical averaging window over multiple lines, sliding over the ﬁeld. This mode also generates phase correct output lines. The averaging window length corresponds to the scaling ratio, resulting in an adaptive vertical low-pass effect, to greatly reduce aliasing artefacts. ACM can be applied for downscales only from ratio 1 down to 1⁄64. ACM results in a scale dependentDC gain ampliﬁcation, which has to be precorrected by the BCS control of the scaler part. The phase and scale controlling DTO calculates in 16-bit resolution, controlled by parameters YSCY[15:0] B1h[7:0] B0h[7:0] and YSCC[15:0] B3h[7:0] B2h[7:0], continuously over the entire ﬁeld. A start offset can be applied to the phase processing by means of the parameters YPY3[7:0] to YPY0[7:0] in BFh[7:0] to BCh[7:0] and YPC3[7:0] to YPC0[7:0] in BBh[7:0] to B8h[7:0]. The start phase covers the range of 255⁄32 to1⁄32 lines offset. By programming appropriate, opposite, vertical start phase values (subaddresses B8h to BFh and E8h to EFh) depending on odd or even ﬁeld ID of the source video stream and A or B page cycle, frame ID conversion and ﬁeld rate conversion are supported (i.e. de-interlacing, re-interlacing). Figure40 andFigure41 andTable26 andTable27 describe the use of the offsets. Remark: The vertical start phase, as well as the scaling ratio are deﬁned independently for the luminance and chrominance channel, but must be set to the same values in the actual implementation for accurate 4:2:2 output processing. The vertical processing communicates on its input side with the line FIFO buffer. The scale related equations are:
Scaling increment calculation for ACM and LPI mode, downscale and zoom: YSCY[15:0] and YSCC[15:0] = lower integer of
BCS value to compensate DC gain in ACM mode (contrast and saturation have to be set): CONT[7:0] A5h[7:0] respectively SATN[7:0] A6h[7:0] = lower integer of , or = lower integer of

1024 Nline_in

Nline_out  1024

9.3.3.3 Use of the vertical phase offsets

As described inSection9.3.1.3, the scaler processing may run randomly over the interlaced input sequence. Additionally the interpretation and timing between ITU 656 ﬁeld ID and real-time detection by means of the state of H-sync at the falling edge of V-sync may result in different ﬁeld ID interpretation. A vertically scaled interlaced output also gets a larger vertical sampling phase error, if the interlaced input ﬁelds are processed, without regard to the actual scale at the starting point of operation (see Figure40). Four events should be considered, they are illustrated inFigure41. InTable26 andTable27 PHO is a usable common phase offset. It should be noted that the equations ofFigure41 produce an interpolated output, also for the unscaled case, as the geometrical reference position for all conversions is the position of the ﬁrst line of the lower ﬁeld; see Table26. If there is no need for UP-LO and LO-UP conversion and the input ﬁeld ID is the reference for the back-end operation, then it is UP-LO = UP-UP and LO-UP = LO-LO and the1⁄2 line phase shift (PHO + 16) that can be skipped. This case is listed inTable27. The SAA7108AE; SAA7109AE supports 4 phase offset registers per task and component (luminance and chrominance). The value of 20h represents a phase shift of one line. The registers are assigned to the following events; e.g. subaddresses B8h to BBh:

B8h: 00 = input ﬁeld ID 0, task status bit 0 (toggle status; seeSection9.3.1.3)
B9h: 01 = input ﬁeld ID 0, task status bit 1
BAh: 10 = input ﬁeld ID 1, task status bit 0
BBh: 11 = input ﬁeld ID 1, task status bit 1 Depending on the input signal (interlaced or non-interlaced) and the task processing

50 Hz or ﬁeld reduced processing with one or two tasks (see examples in

Section9.3.1.3), other combinations may also be possible, but the basic equations are the same.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 77 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 40. Basic problem of interlaced vertical scaling (example: downscale3⁄5) mhb547 mismatched vertical line distancesscale dependent start offset correct scale dependent position unscaled input scaled output, no phase offset scaled output, with phase offset field 1 field 2 field 1 field 2 field 1 field 2 Offset = = 32 = 1 line shift A = input line shift = 16 B = input line shift + scale increment = C = scale increment + D = no offset = 0 Fig 41. Derivation of the phase related equations (example: interlace vertical scaling down to3⁄5, with ﬁeld conversion) mhb548 field 1 field 2 upper lower field 1 field 2 case UP-UP case LO-LO field 1 field 2 case UP-LO case LO-UP A B C D 1024 2--- 2--- 1 2--- YSCY[15:0] 2--- YSCY[15:0]

9.4 VBI data decoder and capture (subaddresses 40h to 7Fh)

The SAA7108AE; SAA7109AE contains a versatile VBI data decoder. built into the multimedia video data acquisition circuit SAA5284. Table 26. Examples for vertical phase offset usage: global equations Table 27. Vertical phase offset usage; assignment of the phase offsets

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. The supported VBI data standards are shown inTable28. VBI data slicer during active video. Table 28. Data types supported by the data slicer block

0010 VPS 5 9951h VPS

1001 VITC/EBU time codes

1010 VITC/SMPTE time codes

1110 Japanese format switch

9.5 Image port output formatter (subaddresses 84h to 87h)

The output interface consists of a FIFO for video and for sliced text data, an arbitration circuit, which controls the mixed transfer of video and sliced text data over the I port and a decoding and multiplexing unit, which generates the 8-bit or 16-bit wide output data stream and the accompanied reference and supporting information. The clock for the output interface can be derived from an internal clock, decoder, expansion port or an externally provided clock which is appropriate for e.g. VGA and frame buffer. The clock can be up to 33 MHz. The scaler provides the following video related timing reference events (signals), which are available on pins as deﬁned by subaddresses 84h and 85h:

Output ﬁeld ID
Start and end of vertical active video range
Start and end of active video line
Data qualiﬁer or gated clock
Actually activated programming page (if CONLH is used)
Threshold controlled FIFO ﬁlling ﬂags (empty, full and ﬁlled)
Sliced data marker The discontinuous data stream at the scaler output is accompanied by a data valid ﬂag (or data qualiﬁer), or is transported via a gated clock. Clock cycles with invalid data on the I port data bus (including the HPD pins in 16-bit output mode) are marked with code 00h. The output interface also arbitrates the transfer between scaled video data and sliced text data over the I port output. The bits VITX1 and VITX0 (subaddress 86h) are used to control the arbitration. As a further operation the serialization of the internal 32-bit double words to 8-bit or optional 16-bit output, as well as the insertion of the extended ITU 656 codes (SAV/EAV for video data, ANC or SAV/EAV codes for sliced text data) are done here. For handshake with the VGA controller, or other memory or bus interface circuitry, programmable FIFO ﬂags are provided; see Section9.5.2.

9.5.1 Scaler output formatter (subaddresses 93h and C3h)

The output formatter organizes the packing into the output FIFO. The following formats are available: Y -CB-CR 4:2:2 , Y - CB-CR 4:1:1 , Y - CB-CR 4:2:0 , Y - CB-CR 4:1:0 a n d Y only (e.g. for raw samples). The formatting is controlled by FSI[2:0] 93h[2:0], FOI[1:0] 93h[4:3] and FYSK[93h[5]]. The data formats are deﬁned on double words, or multiples, and are similar to the video formats as recommended for PCI multimedia applications (compares to SAA7146A), but planar formats are not supported. FSI[2:0] deﬁnes the horizontal packing of the data, FOI[1:0] deﬁnes how many Y only lines are expected, before a Y/C line will be formatted. If FYSK is set to logic 0 preceding Y only lines will be skipped, and the output will always start with a Y/C line.

9.5.2 Video FIFO (subaddress 86h)

appropriate for the VGA controller or attached frame buffer.

The FIFO Almost Empty (FAE) ﬂag
The FIFO Combined Flag (FCF) or FIFO ﬁlled, which is set at almost full level and reset, with hysteresis, only after the level crosses below the almost empty mark
The FIFO Almost Full (FAF) ﬂag
The FIFO Overﬂow (FOVL) ﬂag The trigger levels for FAE and FAF are programmable by FFL[1:0] 86h[3:2] (16, 24, 28, full) and FEL[1:0] 86h[1:0] (16, 8, 4, empty). The state of this ﬂag can be seen on pins IGP0 or IGP1. The pin mapping is deﬁned by subaddresses 84h and 85h; seeSection10.5.

Table 29. Byte stream for different output formats Table 30. Explanation toTable29 Table 31. Limiting range on I port

9.5.3 Text FIFO

The data of the internal VBI data slicer is collected in the text FIFO before the transmission over the I port is requested (normally before the video window starts). It is partitioned into two FIFO sections. A complete line is ﬁlled into the FIFO before a data transfer is requested. So normally, one line of text data is ready for transfer, while the next text line is collected. Thus sliced text data is delivered as a block of qualiﬁed data, without any qualiﬁcation gaps in the byte stream of the I port. The decoded VBI data is collected in the dedicated VBI data FIFO. After the capture of a line has been completed, the FIFO can be streamed through the image port, preceded by a header, giving line number and standard. The VBI data period can be signalled via the sliced data ﬂag on pin IGP0 or IGP1. The decoded VBI data is lead by the ITU ancillary data header (DID[5:0] 5Dh[5:0] at value < 3Eh) or by SAV/EAV codes selectable by DID[5:0] at value 3Eh or 3Fh. Pin IGP0 or IGP1 is set if the ﬁrst byte of the ANC header is valid on the I port bus. It is reset if an SAV occurs. So it may frame multiple lines of text data output, in the event that the video processing starts with a distance of several video lines to the region of text data. Valid sliced data from the text FIFO is available on the I port as long as the IGP0 or IGP1 ﬂag is set and the data qualiﬁer is active on pin IDQ. The decoded VBI data is presented in two different data formats, controlled by bit RECODE.

RECODE = 1: values 00h and FFh will be recoded to even parity values 03h and FCh
RECODE = 0: values 00h and FFh may occur in the data stream as detected

9.5.4 Video and text arbitration (subaddress 86h)

Sliced text data and scaled video data are transferred over the same bus, the I port. The mixed transfer is controlled by an arbitration circuit. If the video data is transferred without any interrupt and the video FIFO does not need to buffer any output pixel, the text data is inserted after the end of a scaled video line, normally during the blanking interval of the video.

9.5.5 Data stream coding and reference signal generation (subaddresses 84h,

85h and 93h) As horizontal and vertical reference signals are logic 1, active gate signals are generated, which frame the transfer of the valid output data. As an alternative to the gates, the horizontal and vertical trigger pulses are generated on the rising edges of the gates. Due to the dynamic FIFO behavior of the complete scaler path, the output signal timing has no ﬁxed timing relationship to the real-time input video stream. So ﬁxed propagation delays, in terms of clock cycles, related to the analog input cannot be deﬁned. The data stream is accompanied by a data qualiﬁer. Additionally invalid data cycles are marked with code 00h. If ITU 656 like codes are not required, they can be suppressed in the output stream.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. valid output data in bursts of a guaranteed length. modiﬁed. The default polarity for the qualiﬁer and reference signals is logic 1 (active). Table32 shows the relevant and supported SAV and EAV coding. [1] The leading byte sequence is: FFh-00h-00h. a) Scaler output data: task A⇒ MSB = CONLH[90h[7]]; task B⇒ MSB = CONLH[C0h[7]]. Table 32. SAV/EAV codes on the I port

00 IDQ pin inactive

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] Inverted EP (bit 7); for EP seeTable note2. [2] Even parity (bit 6) of bits 5 to 0. [3] Odd parity (bit 7) of bits 6 to 0. Table 33. Explanation toFigure42 It should be noted that the number of valid bytes inside the stream can be seen in the BC byte.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] NEP = inverted EP; seeTable note2. [2] EP = even parity of bits 5 to 0. [5] Subaddress 5Dh at 3Eh and 3Fh are used for ITU 656 like SAV/EAV header generation; recommended value. [6] V = 0: active video; V = 1: blanking. [7] H = 0: start of line; H = 1: end of line. [8] DC = data count in double words according to the data type. [9] OP = odd parity of bits 6 to 0.

9.6 Audio clock generation (subaddresses 30h to 3Fh)

9.6.1 Master audio clock

Audio master Clocks Per Field, ACPF[17:0] 32h[1:0] 31h[7:0] 30h[7:0] according to the equation:

Table 34. Bytes stream of the data slicer

1 FID [3] V[6] H [7] P3 P2 P1 P0

0 FID [3] V[6] H [7] P3 P2 P1 P0

Audio master Clocks Nominal Increment, ACNI[21:0] 36h[5:0] 35h[7:0] 34h[7:0] according to the equation: See Table35 for examples. Remark : For standard applications the synthesized audio clock AMCLK can be used directly as master clock and as input clock for port AMXCLK (short cut) to generate ASCLK and ALRCLK. For high-end applications it is recommended to use an external analog PLL circuit to enhance the performance of the generated audio clock.

9.6.2 Signals ASCLK and ALRCLK

SDIV[5:0] 38h[5:0] according to the equation: ⇒
LRDIV[5:0] 39h[5:0] according to the equation: ⇒ See Table36 for examples.

Table 35. Programming examples for audio master clock generation

9.6.3 Other control signals

Input/output interfaces and ports of digital video decoder part

Analog video input interface, for analog CVBS and/or Y and C input signals
Audio clock port
Digital real-time signal port (RT port)
Digital video expansion port (X port), for unscaled digital video input and output
Digital image port (I port) for scaled video data output and programming
Digital host port (H port) for extension of the image port or expansion port from 8-bit to 16-bit

Table 36. Programming examples for ASCLK/ALRCLK clock generation Table 37. Control signals

10.1 Analog terminals

Two anti-alias ﬁlters are integrated, and self adjusting via the clock frequency. (pin AOUT) is provided for testing purposes.

10.2 Audio clock signals

ASCLK: can be used as audio serial clock
ALRCLK: audio left/right channel clock The ratios are programmable; seeSection9.6.

Table 38. Analog pin description

10.3 Clock and real-time synchronization signals

For the generation of the line-locked video (pixel) clock LLC, and of the frame-locked audio serial bit clock, a crystal accurate frequency reference is required. An oscillator is built-in for fundamental or third harmonic crystals. The supported crystal frequencies are 32.11 MHz or 24.576 MHz (deﬁned during reset by strapping pin ALRCLK). Alternatively pins XTALId and XTALIe can be driven from an external single-ended oscillator. The crystal oscillation can be propagated as a clock to other ICs in the system via pin XTOUTd. The Line-Locked Clock (LLC) is the double pixel clock of nominal 27 MHz. It is locked to the selected video input, generating baseband video pixels according to “ITU recommendation 601”. In order to support interfacing circuits, a direct pixel clock (LLC2) is also provided. The pins for line and ﬁeld timing reference signals are RTCO, RTS1 and RTS0. Various real-time status information can be selected for the RTS pins. The signals are always available (output) and reﬂect the synchronization operation of the decoder part in the SAA7108AE; SAA7109AE. The function of the RTS1 and RTS0 pins can be deﬁned by bits RTSE1[3:0] 12h[7:4] and RTSE0[3:0] 12h[3:0]; see Table40. Table 39. Audio clock pin description

applications

ASCLK K14 O serial audio clock output, can be synchronized to rising or falling edge of AMXCLK SDIV[5:0] 38h[5:0] and SCPH[3Ah[0]] ALRCLK J13 O audio channel (left/right) clock output, can be synchronized to rising or falling edge of ASCLK LRDIV[5:0] 39h[5:0] and LRPH[3Ah[1]] Table 40. Clock and real-time synchronization signals

10.4 Video expansion port (X port)

8-bit data, I/O, regular components video Y -CB-CR 4:2:2 ,i . e .CB-Y -CR -Y , byte serial, exceptionally raw video samples (e.g. ADC test); in input mode the data bus can be extended to 16-bit by pins HPD7 to HPD0.
Clock, synchronization and auxiliary signals, accompanying the data stream, I/O As output, these are direct copies of the decoder signals. The data transfers through the expansion port represent a single D1 port, with half duplex mode. The SAV and EAV codes may be inserted optionally for data input (controlled by bit XCODE[92h[3]]). The input/output direction is switched for complete ﬁelds only. LLC2 L14 O line-locked pixel clock, nominal 13.5 MHz - RTCO L13 O real-time control output, transfers real-time status information supporting RTC level 3.1 (see document “How to use Real Time Control (RTC)”, available on request) RTS0 K13 O real-time status information line 0, can be programmed to carry various real-time information; see Table160 RTSE0[3:0] 12h[3:0] RTS1 L10 O real-time status information line 1, can be programmed to carry various real-time information; see Table161 RTSE1[3:0] 12h[7:4]

Table 40. Clock and real-time synchronization signals …continued Table 41. Signals dedicated to the expansion port

10.4.1 X port conﬁgured as output

CVBS samples are always transferred if any sliced data type is selected.

Active video (data type 15): contains component Y -CB-CR 4:2:2 signal, 720 active pixels per line. The amplitude and offsets are programmable via DBRI7 to DBRI0, DCON7 to DCON0, DSAT7 to DSAT0, OFFU1, OFFU0, OFFV1 and OFFV0. The nominal levels are illustrated in Figure27.
Test line (data type 6): is similar to the active video format, with some constraints within the data processing: – Adaptive chrominance comb ﬁlter, vertical ﬁlter (chrominance comb ﬁlter for NTSC standards, PAL phase error correction) within the chrominance processing are disabled – Adaptive luminance comb ﬁlter, peaking and chrominance trap are bypassed within the luminance processing This data type is deﬁned for future enhancements. It could be activated for lines containing standard test signals within the vertical blanking period. Currently most sources do not contain test lines. The nominal levels are illustrated in Figure27.
Raw samples (data types 0 to 5 and 7 to 14): CB-CR samples are similar to data type 6, but CVBS samples are transferred instead of processed luminance samples within the Y time slots. The amplitude and offset of the CVBS signal is programmable via RAWG7 to RAWG0 and RAWO7 to RAWO0; see Section11,Table167 and Table168. The nominal levels are illustrated inFigure28. The relationship of LCR programming to line numbers is described inSection9.2, Figure31 andFigure32. XRH N2 I/O horizontal reference signal for the X port: as output: HREF or HS from the decoder (see Figure35); as input: a reference edge for horizontal input timing and a polarity for input ﬁeld ID detection can be deﬁned XRHS[13h[6]], XFDH[92h[6]] and XDH[92h[2]] XRV L5 I/O vertical reference signal for the X port: as output: V123 or ﬁeld ID from the decoder (see Figure33 and Figure34); as input: a reference edge for vertical input timing and for input ﬁeld ID detection can be deﬁned XRVS[1:0] 13h[5:4], XFDV[92h[7]] and XDV[1:0] 92h[5:4] XTRI K1 I port control: switches X port input to 3-state XPE[1:0] 83h[1:0]

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. codes are generated in this mode. blanking period between EAV and SAV. via OFTS1 and OFTS0; seeTable162. The F and V bits change synchronously with the EAV code. sequence is replaced by the standard ‘- 80 - 10 -’ blanking values. [2] If raw samples or sliced data are selected by the line control registers (LCR2 to LCR24), the Y samples are replaced by CVBS samples. Table 42. Data format on the expansion port Table 43. SAV/EAV format on expansion port XPD7 to XPD0

6 F ﬁeld bit

5 V vertical blanking bit

4 H format

10.4.2 X port conﬁgured as input

signal) on the XRV pin (controlled by XFDV[92h[7]], XFDH[92h[6]] and XDV[1:0] 92h[5:4]). Table 44. 525 lines/60 Hz vertical timing Table 45. 625 lines/50 Hz vertical timing

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 94 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC The trigger events on XRH (rising/falling edge) and XRV (rising/falling/both edges) for the scalers acquisition window are deﬁned by XDV[1:0] 92h[5:4] and XDH[92h[2]]. The signal polarity of the qualiﬁer can also be deﬁned (bit XDQ[92h[1]]). Alternatively to a qualiﬁer, the input clock can be applied to a gated clock (clock gated with a data qualiﬁer, controlled by bit XCKS[92h[0]]). In this event, all input data will be qualiﬁed.

10.5 Image port (I port)

The image port transfers data from the scaler as well as from the VBI data slicer, if selected (maximum 33 MHz). The reference clock is available at the ICLK pin, as an output or as an input (maximum 33 MHz). As output, ICLK is derived from the line-locked decoder or expansion port input clock. The data stream from the scaler output is normally discontinuous. Therefore valid data during a clock cycle is accompanied by a data qualifying (data valid) ﬂag on pin IDQ. For pin constrained applications the IDQ pin can be programmed to function as a gated clock output (bit ICKS2[80h[2]]). The data formats at the image port are deﬁned in double words of 32 bits (4 bytes), such as the related FIFO structures. However, the physical data stream at the image port is only 16-bit or 8-bit wide; in 16-bit mode data pins HPD7 to HPD0 are used for chrominance data. The four bytes of the double words are serialized in words or bytes. Available formats are as follows:

Y- CB-CR 4:2:2
Y- CB-CR 4:1:1
Raw samples
Decoded VBI data For handshake with the receiving VGA controller, or other memory or bus interface circuitry, F , H and V reference signals and programmable FIFO ﬂags are provided. The information is provided on pins IGP0, IGP1, IGPH and IGPV. The functionality on these pins is controlled via subaddresses 84h and 85h. VBI data is collected over an entire line in its own FIFO and transferred as an uninterrupted block of bytes. Decoded VBI data can be signed by the VBI ﬂag on pin IGP0 or IGP1. As scaled video data and decoded VBI data may come from different and asynchronous sources, an arbitration scheme is needed. Normally the VBI data slicer has priority. The image port consists of the pins and/or signals, as listed in Table46. For pin constrained applications, or interfaces, the relevant timing and data reference signals can also be encoded into the data stream. Therefore the corresponding pins do not need to be connected. The minimum image port conﬁguration requires 9 pins only, i.e. 8 pins for data including codes, and 1 pin for clock or gated clock. The inserted codes are deﬁned in close relationship to the ITU-R BT.656 (D1) recommendation, where possible. The following deviations from “ITU 656 recommendation” are implemented at the SAA7108AE; SAA7109AEs image port interface:
SAV and EAV codes are only present in those lines, where data is to be transferred, i.e. active video lines, or VBI raw samples, no codes for empty lines

There may be more or less than 720 pixels between SAV and EAV
Data content and number of clock cycles during horizontal and vertical blanking is undeﬁned, and may not be constant
Data stream may be interleaved with not-valid data codes, 00h, but SAV and EAV 4-byte codes are not interleaved with not-valid data codes
There may be an irregular pattern of not-valid data, or IDQ, and as a result, CB-Y -CR -Y is not in a ﬁxed phase to a regular clock divider
VBI raw sample streams are enveloped with SAV and EAV, like normal video
Decoded VBI data is transported as Ancillary (ANC) data, two modes: – Direct decoded VBI data bytes (8-bit) are directly placed in the ANC data ﬁeld, 00h and FFh codes may appear in the data block (violation to ITU-R BT.656) – Recoded VBI data bytes (8-bit) directly placed in ANC data ﬁeld, 00h and FFh codes will be recoded to even parity codes 03h and FCh to suppress invalid ITU-R BT.656 codes There are no empty cycles in the ancillary code and its data ﬁeld. The data codes 00h and FFh are suppressed (changed to 01h or FEh respectively) in the active video stream, as well as in the VBI raw sample stream (VBI pass-through). Optionally, the number range can be further limited.

Table 46. Signals dedicated to the image port

10.6 Host port for 16-bit extension of video data I/O (H port)

The H port pins HPD can be used for extension of the data I/O paths to 16-bit.

10.7.1 I port output timing

qualiﬁer on pin IDQ. In addition, invalid cycles are marked with output code 00h.

10.7.2 X port input timing

It is not necessary to mark invalid cycles with a 00h code
No constraints on the input qualiﬁer (can be a random pattern)
XCLK may be a gated clock (XCLK AND external XDQ) Remark : All timings illustrated inFigure43 toFigure49 are given for an uninterrupted output stream (no handshake with the external hardware).

Table 47. Signals dedicated to the host port

00 FF 00 00 SAV 00 C B Y C R Y0 0 C B Y C R Y0 0

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 97 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 44. Output timing at the I port for serial 8-bit data at start of a line (ICODE = 0) IPD[7:0] IGPH IDQ ICLK

00 C B Y C R Y0 0 C B Y C R Y0 0

Fig 45. Output timing at the I port for serial 8-bit data at end of a line (ICODE = 1) IPD[7:0] IGPH IDQ ICLK

00 C B Y C R Y0 0 C B Y C R Y0 0 F F 0 0 0 0 E A V 0 0

Fig 46. Output timing at the I port for serial 8-bit data at end of a line (ICODE = 0) IPD[7:0] IGPH IDQ ICLK

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 98 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 47. Output timing for 16-bit data output via the I port and the H port with codes (ICODE = 1), timing is like 8-bit output, but packages of 2 bytes per valid cycle IPD[7:0] HPD [7:0] IGPH IDQ ICLK

00 FF 00 00 Y0 Y1 00 Y2 Y3 Yn-1 Yn 00 FF 00 00

00 00 SAV 00 00 C BC B C RC R C RC B 00 00 EAV 00 Fig 48. Horizontal and vertical gate output timing IGPV IGPH IDQ mhb555 Fig 49. Output timing for sliced VBI data in 8-bit serial output mode (dotted graphs for SAV/EAV mode) mhb733 IPD[7:0] HPD [7:0] sliced data flag on IGP0 or IGP1 IDQ ICLK 00 00 FF FF DID SDID XX YY ZZ CS BC 00 00 00

00 FF 00 SAV 00 00 00BC FF EAV

11.1 Digital video encoder part

Table 48. Slave receiver bit allocation map (slave address 88h)

70 ADWHS7 ADWHS6 ADWHS5 ADWHS4 ADWHS3 ADWHS2 ADWHS1 ADWHS0

71 ADWHE7 ADWHE6 ADWHE5 ADWHE4 ADWHE3 ADWHE2 ADWHE1 ADWHE0

11.1.1 I2C-bus format

a. to control registers b. to the HD line count array (subaddress D0h) c. to cursor bit map (subaddress FEh) d. to color look-up table (subaddress FFh) See Table49 for explanations. Fig 50. I2C-bus write access a. to control registers b. to cursor bit map or color LUT See Table49 for explanations. Fig 51. I2C-bus read access 001aad411 001aad412 001aad413 001aad414 001aad415 001aad416 FEh or FFh A A Sr A AmAm P

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] X is the read/write control bit; X = logic 0 is order to write; X = logic 1 is order to read. [2] If more than 1 byte of DATA is transmitted, then auto-increment of the subaddress is performed.

11.1.2 Slave receiver

Table 49. Explanations ofFigure50 andFigure51 Table 50. Common DAC adjust ﬁne register, subaddress 16h, bit description Legend: * = default value after reset.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 51. RGB DAC adjust coarse registers, subaddresses 17h to 19h, bit description Table 52. MSM threshold, subaddress 1Ah, bit description Table 53. Monitor sense mode register, subaddress 1Bh, bit description Legend: * = default value after reset.

7 MSM R/W monitor sense mode

6 MSA R/W automatic monitor sense mode

5 MSOE R/W 0 pin TVD is active

2 RCOMP R check comparator at DAC on pin RED_CR_C_CVBS

1 GCOMP R check comparator at DAC on pin GREEN_VBS_CVBS

0 BCOMP R check comparator at DAC on pin BLUE_CB_CVBS

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 54. Wide screen signal registers, subaddresses 26h and 27h, bit description Legend: * = default value after reset. Table 55. Real-time control and burst start register, subaddress 28h, bit description Legend: * = default value after reset. Table 56. Sync reset enable and burst end register, subaddress 29h, bit description Legend: * = default value after reset.

7 SRES R/W 0* pin TTX_SRES accepts a teletext bit stream (TTX)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 108 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Table 57. Copy generation 0, 1, 2 and CG enable registers, subaddresses 2Ah to 2Ch, bit Legend: * = default value after reset. Subaddress Bit Symbol Access Value Description 2Ch 7 CGEN R/W copy generation data output 0* disabled 1 enabled 6 to 4 - R/W 0 must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 CG[19:16] R/W - LSBs of the respective bytes are encoded immediately after run-in, the MSBs of the respective bytes have to carry the CRCC bits, in accordance with the deﬁnition of copy generation management system encoding format. 2Bh 7 to 0 CG[15:8] 2Ah 7 to 0 CG[7:0] Table 58. Output port control register, subaddress 2Dh, bit description Legend: * = default value after reset.

7 VBSEN R/W pin GREEN_VBS_CVBS provides a

6 CVBSEN1 R/W pin GREEN_VBS_CVBS provides a

1 CVBS signal

5 CVBSEN0 R/W pin BLUE_CB_CVBS provides a

4 CEN R/W pin RED_CR_C_CVBS provides a

3 ENCOFF R/W encoder

2 CLK2EN R/W pin TTXRQ_XCLKO2 provides

1 CVBSEN2 R/W pin RED_CR_C_CVBS provides a

6 YUPSC R/W vertical scaler

2 CZOOM R/W cursor generator

1 IGAIN R/W expected input level swing is

0 XINT R/W interpolation ﬁlter for horizontal upscaling

Table 60. Gain luminance for RGB register, subaddress 38h, bit description Legend: * = default value after reset. depending on external application. Table 61. Gain color difference for RGB register, subaddress 39h, bit description Legend: * = default value after reset. depending on external application.

7 CBENB R/W 0 data from input ports is encoded

5 SYNTV R/W in Slave mode

4 SYMP R/W horizontal and vertical trigger

3 DEMOFF R/W Y -C B-CR to RGB dematrix

2 CSYNC R/W pin HSM_CSYNC provides

1 Y2C R/W input luminance data

0 UV2C R/W input color difference data

Table 63. VPS enable, input control 2, subaddress 54h, bit description Legend: * = default value after reset.

7 VPSEN R/W video programming system data insertion

5 GPVAL R/W if GPEN = 1, pin VSM provides

0 LOW level

1 HIGH level

4 GPEN R/W pin VSM provides

1 EDGE R/W input data is sampled with

0 SLOT R/W 0* normal assignment of the input data to the clock edge

Table 64. VPS byte 5, 11, 12, 13 and 14 registers, subaddresses 55h to 59h, bit Table 65. Chrominance phase register, subaddress 5Ah, bit description Legend: * = default value after reset. Legend: * = default value after reset.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] Variable gain for CB signal; input representation in accordance with‘ITU-R BT.601’. [2] Variable black level; input representation in accordance with‘ITU-R BT.601’. [3] Output black level/IRE = BLCKL× 2/6.29 + 28.9. [4] Output black level/IRE = BLCKL× 2/6.18 + 26.5. [1] Variable gain for CR signal; input representation in accordance with‘ITU-R BT.601’. [2] Variable blanking level. [3] Output black level/IRE = BLNNL× 2/6.29 + 25.4. [4] Output black level/IRE = BLNNL× 2/6.18 + 25.9; default after reset: 35h. Table 66. Gain U and gain U MSB, black level registers, subaddresses 5Bh and 5Dh, bit description Table 67. Gain V and gain V MSB, blanking level registers, subaddresses 5Ch and 5Eh, bit description

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 68. CCR and blanking level VBI register, subaddress 5Fh, bit description Table 69. Standard control register, subaddress 61h, bit description Legend: * = default value after reset.

7 DOWND R/W digital core

6 DOWNA R/W DACs

5 INPI R/W PAL switch

4 YGS R/W luminance gain for white − black

2 SCBW R/W bandwidth for chrominance encoding (for overall transfer

1 PAL R/W encoding

0 NTSC (non-alternating V component)

1 PAL (alternating V component)

0 FISE R/W total pixel clocks per line

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 114 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC [1] Examples: a) NTSC M: ffsc= 227.5, fllc= 1716→ FSC = 569408543 (21F0 7C1Fh). b) PAL B/G: ffsc= 283.7516, fllc= 1728→ FSC = 705268427 (2A09 8ACBh). [1] LSBs of the respective bytes are encoded immediately after run-in and framing code, the MSBs of the respective bytes have to carry the parity bit, in accordance with the deﬁnition of line 21 encoding format. Table 70. Burst amplitude register, subaddress 62h, bit description Legend: * = default value after reset, ^ = recommended value.

7 RTCE R/W real-time control

Table 71. Subcarrier 0, 1, 2 and 3 registers, subaddresses 63h to 66h, bit description Table 72. Line 21 odd 0, 1 and even 0, 1 registers, subaddresses 67h to 6Ah, bit [1] Subaddress Bit Symbol Access Value Description 67h 7 to 0 L21O[07:00] R/W - ﬁrst byte of captioning data, odd ﬁeld 68h 7 to 0 L21O[17:10] R/W - second byte of captioning data, odd ﬁeld 69h 7 to 0 L21E[07:00] R/W - ﬁrst byte of extended data, even ﬁeld 6Ah 7 to 0 L21E[17:10] R/W - second byte of extended data, even ﬁeld FSC round ffsc fllc =

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. all internally generated timing signals. variation range of VTRIG=0t o3 1 (1Fh). Table 73. Trigger control registers, subaddresses 6Ch and 6Dh, bit description Legend: * = default value after reset. Table 74. Multi control register, subaddress 6Eh, bit description Legend: * = default value after reset.

7 NVTRIG R/W values of the VTRIG register are

6 BLCKON R/W 0* encoder in normal operation mode

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] Values above 1715 (FISE = 1) or 1727 (FISE = 0) are not allowed. Table 75. Closed caption, teletext enable register, subaddress 6Fh, bit description Legend: * = default value after reset.

5 TTXEN R/W teletext insertion

Table 76. Active Display Window Horizontal (ADWH) start and end registers, Table 77. TTX request horizontal start register, subaddress 73h, bit description Legend: * = default value after reset.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 78. TTX request horizontal delay register, subaddress 74h, bit description Legend: * = default value after reset and minimum value. Table 79. CSYNC advance register, subaddress 75h, bit description

0 XTAL clocks to 31 XTAL clocks

Table 80. TTX odd request vertical start register, subaddress 76h, bit description Legend: * = default value after reset. Table 81. TTX odd request vertical end register, subaddress 77h, bit description Legend: * = default value after reset. Table 82. TTX even request vertical start register, subaddress 78h, bit description Legend: * = default value after reset.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 83. TTX even request vertical end register, subaddress 79h, bit description Legend: * = default value after reset. Table 84. First active line register, subaddress 7Ah, bit description Table 85. Last active line register, subaddress 7Bh, bit description Table 86. TTX mode, MSB vertical register, subaddress 7Ch, bit description Legend: * = default value after reset.

7 TTX60 R/W 0* enables NABTS (FISE = 1) or European TTX (FISE = 0)

6 LAL8 R/W see Table85

5 TTXO R/W teletext protocol selected (see Figure66)

4 FAL8 R/W see

3 TTXEVE8 R/W see Table83

2 TTXOVE8 R/W see Table81

1 TTXEVS8 R/W see Table82

0 TTXOVS8 R/W see Table80

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] This bit mask is effective only if the lines are enabled by TTXOVS/TTXOVE and TTXEVS/TTXEVE. Table 87. Disable TTX line registers, subaddresses 7Eh and 7Fh, bit description[1] Table 88. Pixel clock 0, 1 and 2 registers, subaddresses 81h to 83h, bit description

20 F63Bh 640 × 480 to NTSC M

Table 89. Pixel clock control register, subaddress 84h, bit description Legend: * = default value after reset.

7 DCLK R/W 0* set to logic 1

6 PCLSY R/W pixel clock generator

5 IFRA R/W input FIFO gets reset

4 IFBP R/W input FIFO

7 EIDIV R/W 0* DVO compliant signals are applied

Table 91. Horizontal offset register, subaddress 90h, bit description Table 92. Pixel number register, subaddress 91h, bit description Table 93. Vertical offset odd register, subaddress 92h, bit description Table 94. Vertical offset even register, subaddress 93h, bit description Table 95. MSBs register, subaddress 94h, bit description Table 96. Line number register, subaddress 95h, bit description

7 EFS R/W in Slave mode frame sync signal at pin FSVGC

6 PCBN R/W polarity of

5 SLAVE R/W from the SAA7104E; SAA7105E the timing to the graphics

4 ILC R/W if hardware cursor insertion is active

3 YFIL R/W luminance sharpness booster

Table 98. Sync control register, subaddress 97h, bit description

7 HFS R/W horizontal sync is derived from

6 VFS R/W vertical sync (ﬁeld sync) is derived from

5 OFS R/W pin FSVGC is

4 PFS R/W polarity of signal at pin FSVGC in output mode (Master

3 OVS R/W pin VSVGC is

2 PVS R/W polarity of signal at pin VSVGC in output mode (Master

1 OHS R/W pin HSVGC is

0 PHS R/W polarity of signal at pin HSVGC in output mode (Master

Table 99. Line length register, subaddress 98h, bit description Table 100. Input delay, MSB line length register, subaddress 99h, bit description Table 101. Horizontal increment register, subaddress 9Ah, bit description Table 102. Vertical increment register, subaddress 9Bh, bit description Table 98. Sync control register, subaddress 97h, bit description …continued

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 123 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Table 103. MSBs vertical and horizontal increment register, subaddress 9Ch, bit description Table 104. Weighting factor odd register, subaddress 9Dh, bit description Table 105. Weighting factor even, subaddress 9Eh, bit description Table 106. Weighting factor MSB register, subaddress 9Fh, bit description Table 107. Vertical line skip register, subaddress A0h, bit description Table 108. Blank enable for NI-bypass, vertical line skip MSB register, subaddress A1h, bit Legend: * = default value after reset. Bit Symbol Access Value Description

7 BLEN R/W for non-interlaced graphics in bypass mode

0* no internal blanking 1 forced internal blanking 6 to 4 - R/W 000 must be programmed with logic 0 to ensure compatibility to future enhancements 3 to 0 YSKIP[11:8] R/W see Table107 Table 109. Border color Y register, subaddress A2h, bit description

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 110. Border color U register, subaddress A3h, bit description Table 111. Border color V register, subaddress A4h, bit description Table 112. Subaddress D0h Table113. The array has 15 entries. then start with the next entry in line count array. with the description of the current line. 0 means the entry is not used. Table 113. Layout of the data bytes in the line count array

0 HLC7 HLC6 HLC5 HLC4 HLC3 HLC2 HLC1 HLC0

1 HLT3 HLT2 HLT1 HLT0 0 0 HLC9 HLC8

Table 114. Subaddress D1h Table115. The array has 15 entries. from index 0 to 7. The value 0 means that the entry is not used. Table 115. Layout of the data bytes in the line type array

0 HPD07 HPD06 HPD05 HPD04 HPD03 HPD02 HPD01 HPD00

1 HPV03 HPV02 HPV01 HPV00 0 0 HPD09 HPD08

2 HPD17 HPD16 HPD14 HPD14 HPD13 HPD12 HPD11 HPD10

3 HPV13 HPV12 HPV11 HPV10 0 0 HPD19 HPD18

4 HPD27 HPD26 HPD25 HPD24 HPD23 HPD22 HPD21 HPD20

5 HPV23 HPV22 HPV21 HPV20 0 0 HPD29 HPD28

6 HPD37 HPD36 HPD35 HPD34 HPD33 HPD32 HPD31 HPD30

7 HPV33 HPV32 HPV31 HPV30 0 0 HPD39 HPD38

Table 118. Subaddress D3h consists of 2 bytes. The array has 8 entries. pin HSM_CSYNC; see Table119. Table 119. Layout of the data bytes in the value array

0 HPVE7 HPVE6 HPVE5 HPVE4 HPVE3 HPVE2 HPVE1 HPVE0

Table 120. HD sync trigger state 1 register, subaddress D4h, bit description

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 121. HD sync trigger state 2 register, subaddress D5h, bit description Table 122. HD sync trigger state 3 register, subaddress D6h, bit description Table 123. HD sync trigger state 4 register, subaddress D7h, bit description Table 124. HD sync trigger phase x registers, subaddresses D8h and D9h, bit description Table 125. HD sync trigger phase y registers, subaddresses DAh and DBh, bit description Table 126. HD output control register, subaddress DCh, bit description Legend: * = default value after reset.

3 HDSYE R/W HD sync engine

2 HDTC R/W HD output path processes

1 YUV

1 HDGY R/W 0* gain in the HD output path is reduced, insertion of sync pulses

1 full level swing at the input causes full level swing at the DACs in HD mode

0 HDIP R/W interpolator for the color difference signal in the HD output

0* active 1 off Table 127. Cursor color 1 R, G and B registers, subaddresses F0h to F2h, bit description Table 128. Cursor color 2 R, G and B registers, subaddresses F3h to F5h, bit description Table 129. Auxiliary cursor color R, G and B registers, subaddresses F6h to F8h, bit Subaddress Bit Symbol Description F6h 7 to 0 AUXR[7:0] RED portion of auxiliary cursor color F7h 7 to 0 AUXG[7:0] GREEN portion of auxiliary cursor color F8h 7 to 0 AUXB[7:0] BLUE portion of auxiliary cursor color Table 130. Horizontal cursor position and horizontal hot spot, MSB XCP registers, Table 131. Vertical cursor position and vertical hot spot, MSB YCP registers, subaddresses Table 126. HD output control register, subaddress DCh, bit description …continued Legend: * = default value after reset.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. In subaddresses 5Bh, 5Ch, 5Dh, 5Eh, 62h and D3h all IRE values are rounded up. Table 132. Input path control register, subaddress FDh, bit description

7 LUTOFF R/W color look-up table

6 CMODE R/W cursor mode

5 LUTL R/W LUT loading via input data stream

27 MHz clock) (in subaddresses 91h and 94h set

1 MATOFF R/W RGB to C R -Y -CB matrix

0 DFOFF R/W down formatter

Table 133. Cursor bit map register, subaddress FEh, bit description Table 134. Color look-up table register, subaddress FFh, bit description

11.1.3 Slave transmitter

Table 135. Status byte register, subaddress 00h, bit description

4 CCRDO R 1 set immediately after the closed caption bytes of the odd ﬁeld

3 CCRDE R 1 set immediately after the closed caption bytes of the even ﬁeld

1 FSEQ R 1 during ﬁrst ﬁeld of a sequence (repetition rate:

0 O_E R 1 during even ﬁeld

Table 136. Slave transmitter (slave address 89h) Table 137. Chip ID register, subaddress 1Ch, bit description

11.2 Digital video decoder part

11.2.1 I2C-bus format

Table 138. FIFO status register, subaddress 80h, bit description

3 IFERR R 0 normal FIFO state

2 BFERR R 0 normal FIFO state

1 OVFL R 0 no FIFO overﬂow

1 FIFO overﬂow has occurred; this bit is reset after this

0 UDFL R 0 no FIFO underﬂow

1 FIFO underﬂow has occurred; this bit is reset after this

b. Read procedure (combined).

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [2] If pin RTCO is strapped to VDDD via a 3.3 kΩ resistor. Table 139. Description of I2C-bus format[1] Table 140. Subaddress description and access

11.2.2 I2C-bus details

11.2.2.1 Subaddress 00h

11.2.2.2 Subaddress 01h

delays to the delay of the ADC. Use recommended position only.

11.2.2.3 Subaddress 02h

Table 142. Chip Version (CV) identiﬁcation; 00h[7:4]; read only register Table 143. Horizontal increment delay; 01h[3:0] Table 144. Analog input control 1 (AICO1); 02h[7:0]

0001 Mode 1: CVBS (automatic gain) from AI12

0010 Mode 2: CVBS (automatic gain) from AI21

0011 Mode 3: CVBS (automatic gain) from AI22

0100 Mode 4: CVBS (automatic gain) from AI23

0101 Mode 5: CVBS (automatic gain) from AI24

0110 Mode 6: Y (automatic gain) from AI11

0111 Mode 7: Y (automatic gain) from AI12

1000 Mode 8: Y (automatic gain) from AI11

1001 Mode 9: Y (automatic gain) from AI12

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 140 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 55. Mode 2 CVBS (automatic gain) Fig 56. Mode 3 CVBS (automatic gain) Fig 57. Mode 4 CVBS (automatic gain) Fig 58. Mode 5 CVBS (automatic gain) I2C-bus bit BYPS (subaddress 09h, bit D7) should be set to logic 1 (full luminance bandwidth). I 2C-bus bit BYPS (subaddress 09h, bit D7) should be set to logic 1 (full luminance bandwidth). Fig 59. Mode 6 Y + C (gain channel 2 adjusted via GAI2) Fig 60. Mode 7 Y + C (gain channel 2 adjusted via GAI2) I2C-bus bit BYPS (subaddress 09h, bit D7) should be set to logic 1 (full luminance bandwidth). I 2C-bus bit BYPS (subaddress 09h, bit D7) should be set to logic 1 (full luminance bandwidth). Fig 61. Mode 8 Y + C (gain channel 2 adapted to Y gain) Fig 62. Mode 9 Y + C (gain channel 2 adapted to Y gain) mhb561 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23 mhb562 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23 mhb563 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23 mhb564 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23 mhb565 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23 mhb566 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23 mhb567 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23 mhb568 AI12 AI11 AD2 AD1 CHROMA LUMA AI22 AI21 AI24 AI23

11.2.2.4 Subaddress 03h

[1] HLNRS = 1 should not be used in combination with WPOFF = 0.

11.2.2.5 Subaddress 04h

11.2.2.6 Subaddress 05h

Table 145. Analog input control 2 (AICO2); 03h[6:0]

6 HL not reference select HLNRS 0 normal clamping if decoder is in unlocked state

5 AGC hold during

1 AGC integration hold (freeze)

Table 146. Analog input control 3 (AICO3); static gain control channel 1; 03h[0] and 04h[7:0] Table 147. Analog input control 4 (AICO4); static gain control channel 2; 03h[1] and 05h[7:0]

11.2.2.7 Subaddress 06h

11.2.2.8 Subaddress 07h

11.2.2.9 Subaddress 08h

Table 148. Horizontal sync start; 06h[7:0] Table 149. Horizontal sync stop; 07h[7:0] Table 150. Sync control; 08h[7:0]

1 ODD/EVEN signal toggles ﬁeldwise even if

11.2.2.10 Subaddress 09h

01 VTR mode, recommended if a deﬂection

1 PLL open; horizontal frequency ﬁxed

Table 151. Luminance control; 09h[7:0]

11.2.2.11 Subaddress 0Ah

4.1 MHz

3.4 MHz

3.0 MHz

2.5 MHz

Table 152. Luminance brightness control: decoder part; 0Ah[7:0]

11.2.2.12 Subaddress 0Bh

11.2.2.13 Subaddress 0Ch

11.2.2.14 Subaddress 0Dh

Table 153. Luminance contrast control: decoder part; 0Bh[7:0] Table 154. Chrominance saturation control: decoder part; 0Ch[7:0] Table 155. Chrominance hue control; 0Dh[7:0]

11.2.2.15 Subaddress 0Eh

Table 156. Chrominance control 1; 0Eh[7:0]

1 Every time CDTO is set, the internal subcarrier

60 Hz/525 lines: reserved

11.2.2.16 Subaddress 0Fh

11.2.2.17 Subaddress 10h

11.2.2.18 Subaddress 11h

Table 157. Chrominance gain control; 0Fh[7:0] Table 158. Chrominance control 2; 10h[7:0] Table 159. Mode/delay control; 11h[7:0]

11.2.2.19 Subaddress 12h

Table 160. RT signal control: RTS0 output; 12h[3:0] The polarity of any signal on RTS0 can be inverted via RTP0[11h[3]].

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. a) HLSEL = 0: HL is standard horizontal lock indicator. a) HLSEL = 0: HL is standard horizontal lock indicator. Table 161. RT signal control: RTS1 output; 12h[7:4] The polarity of any signal on RTS1 can be inverted via RTP1[11h[6]].

11.2.2.20 Subaddress 13h

Table 162. RT/X port output control; 13h[7:0]

7 RTCO output enable RTCE 0 3-state

6 X port XRH output

1 HS:

01 ITU 656 related ﬁeld ID (seeFigure33 andFigure34)

001 ITU 656-like format with modiﬁed ﬁeld blanking according to

010 Y -C

11.2.2.21 Subaddress 14h

11.2.2.22 Subaddress 15h

Table 163. Analog/ADC/compatibility control; 14h[7:0]

01 AOUT connected to input AD1

10 AOUT connected to input AD2

11 AOUT connected to internal test point 2

3 XTOUTd output enable XTOUTE 0 pin P4 (XTOUTd) 3-stated

Table 164. VGATE start; FID polarity change; 17h[0] and 15h[7:0] Start of VGATE pulse (LOW-to-HIGH transition) and polarity change of FID pulse, VGPS = 0; seeFigure33 andFigure34.

50 Hz 1st 1 312 1 0 0 1 1 1 0 0 0

60 Hz 1st 4 262 1 0 0 0 0 0 1 1 0

11.2.2.23 Subaddress 16h

11.2.2.24 Subaddress 17h

11.2.2.25 Subaddress 18h

Table 165. VGATE stop; 17h[1] and 16h[7:0] Stop of VGATE pulse (HIGH-to-LOW transition), VGPS = 0; seeFigure33 andFigure34. Table 166. Miscellaneous/VGATE MSBs; 17h[7:6] and 17h[2:0]

7 LLC output enable LLCE 0 enable

6 LLC2 output enable LLC2E 0 enable

1 VGATE occurs one line earlier during ﬁeld 2

1 MSB VGATE stop VSTO8 see Table165

0 MSB VGATE start VSTA8 see Table164

Table 167. Raw data gain control; RAWG[7:0] 18h[7:0]; seeFigure28

11.2.2.26 Subaddress 19h

11.2.2.27 Subaddress 1Fh

Table 168. Raw data offset control; RAWO[7:0] 19h[7:0]; seeFigure28

0 L S B 10000000

Table 169. Status byte video decoder; 1Fh[7:0]; read only register

11.2.3 Programming register audio clock generation

See equations inSection9.6 and examples inTable35 andTable36.

11.2.3.1 Subaddresses 30h to 32h

11.2.3.2 Subaddresses 34h to 36h

11.2.3.3 Subaddress 38h

11.2.3.4 Subaddress 39h

11.2.3.5 Subaddress 3Ah

Table 170. Audio master clock (AMCLK) cycles per ﬁeld Table 171. Audio master clock (AMCLK) nominal increment Table 172. Clock ratio audio master clock (AMXCLK) to serial bit clock (ASCLK) Table 173. Clock ratio serial bit clock (ASCLK) to channel select clock (ALRCLK) Table 174. Audio clock control; 3Ah[3:0]

1 PLL open, AMCLK is free-running

1 ALRCLK phase LRPH 0 ALRCLK edges triggered by falling edges of ASCLK

1 ALRCLK edges triggered by rising edges of ASCLK

0 ASCLK phase SCPH 0 ASCLK edges triggered by falling edges of AMCLK

1 ASCLK edges triggered by rising edges of AMCLK

11.2.4 Programming register VBI data slicer

11.2.4.1 Subaddress 40h

11.2.4.2 Subaddresses 41h to 57h

Table 175. Slicer control 1; 40h[6:4]

6 Hamming check HAM_N 0 Hamming check for 2 bytes after framing

Table 176. Line control register; LCR2 to LCR24 (41h to 57h) See Section9.2 andSection9.4.

11.2.4.3 Subaddress 58h

11.2.4.4 Subaddress 59h

11.2.4.5 Subaddress 5Ah

11.2.4.6 Subaddress 5Bh

11.2.4.7 Subaddress 5Dh

Table 177. Programmable framing code; slicer set 58h[7:0]; seeTable28 andTable176 Table 178. Horizontal offset for slicer; slicer set 59h and 5Bh Table 179. Vertical offset for slicer; slicer set 5Ah and 5Bh Table 180. Field offset, and MSBs for horizontal and vertical offsets; slicer set 5Bh[7:6]

50 Hz 625 lines input sources)

Table 181. Header and data identiﬁcation (DID; ITU 656) code control; slicer set 5Dh[7:0]

1 F and V output is taken from decoder

11.2.4.8 Subaddress 5Eh

11.2.4.9 Subaddress 60h

11.2.4.10 Subaddresses 61h and 62h

11.2.5 Programming register interfaces and scaler part

11.2.5.1 Subaddress 80h

Table 182. Sliced data identiﬁcation (SDID) code; slicer set 5Eh[5:0] Table 183. Slicer status byte 0; 60h[6:2]; read only register

4 VPS valid VPSV 0 no VPS in the last frame

1 VPS detected

3 PALplus valid PPV 0 no PALplus in the last frame

1 PALplus detected

Table 184. Slicer status byte 1; 61h[5:0] and slicer status byte 2; 62h[7:0]; read only Table 185. Global control 1; global set 80h[6:4][1] SWRST moved to subaddress 88h[5].

11.2.5.2 Subaddresses 83h to 87h

Table 186. Global control 1; global set 80h[3:0][1] Table 187. X port I/O enable and output clock phase control; global set 83h[5:4] Table 188. X port I/O enable and output clock phase control; global set 83h[2:0]

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 189. I port signal deﬁnitions; global set 84h[7:6] and 86h[5] Table 190. I port signal deﬁnitions; global set 84h[5:4] and 86h[4] Table 191. I port output signal deﬁnitions; global set 84h[3:0]

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 192. X port signal deﬁnitions text slicer; global set 85h[7:5][1] Table 193. I port reference signal polarities; global set 85h[4:0][1] Table 194. I port FIFO ﬂag control and arbitration; global set 86h[7:4]

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [2] IPCK3 and IPCK2 only affects the gated clock (subaddress 80h, bit ICKS2 = 1). Table 195. I port FIFO ﬂag control and arbitration; global set 86h[3:0][1] Table 196. I port I/O enable, output clock and gated clock phase control; global set Table 197. I port I/O enable, output clock and gated clock phase control; global set 87h[1:0]

11.2.5.3 Subaddress 88h

[2] Bit SWRST is now located here.

11.2.5.4 Subaddress 8Fh

Table 198. Power save control; global set 88h[7:4][1] Table 199. Power save control; global set 88h[3] and 88h[1:0] Table 200. Status information scaler part; 8Fh[7:0]; read only register

7 XTRI status on input pin XTRI, if not used for 3-state control, usable as

6 ITRI status on input pin ITRI, if not used for 3-state control, usable as

5 FFIL status of the internal ‘FIFO almost ﬁlled’ ﬂag

4 FFOV status of the internal ‘FIFO overﬂow’ ﬂag

3 PRDON copy of bit DPROG, can be used to detect power-up and start-up fails

11.2.5.5 Subaddresses 90h and C0h

2 ERROF error ﬂag of scalers output formatter, normally set, if the output

1 FIDSCI status of the ﬁeld sequence ID at the scalers input

0 FIDSCO status of the ﬁeld sequence ID at the scalers output, scaler processing

Table 201. Task handling control; register set A [90h[7:6]] and B [C0h[7:6]][1] Table 202. Task handling control; register set A [90h[5:3]] and B [C0h[5:3]] Table 203. Task handling control; register set A [90h[2:0]] and B [C0h[2:0]]

11.2.5.6 Subaddresses 91h to 93h

line. X port input stream must contain dummy chroma bytes. Table 204. X port formats and conﬁguration; register set A [91h[7:3]] and B [C1h[7:3]][1]

0 X XXX

1 X XXX

Table 205. X port formats and conﬁguration; register set A [91h[2:0]] and B [C1h[2:0]][1]

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 206. X port input reference signal deﬁnitions; register set A [92h[7:4]] and Table 207. X port input reference signal deﬁnitions; register set A [92h[3:0]] and

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 208. I port output format and conﬁguration; register set A [93h[7:5]] and Table 209. I port output format and conﬁguration; register set A [93h[4:0]] and

11.2.5.7 Subaddresses 94h to 9Bh

[1] Reference for counting are luminance samples. [1] Reference for counting are luminance samples. conditions: YO > (number of input lines per ﬁeld− 2), will result in ﬁeld dropping. Table 210. Horizontal input window start; register set A [94h[7:0]; 95h[3:0]] and B [C4h[7:0]; C5h[3:0]] Table 211. Horizontal input window length; register set A [96h[7:0]; 97h[3:0]] and B [C6h[7:0]; C7h[3:0]] Table 212. Vertical input window start; register set A [98h[7:0]; 99h[3:0]] and B [C8h[7:0]; C9h[3:0]]

11.2.5.8 Subaddresses 9Ch to 9Fh

[1] Reference for counting are luminance samples. [2] If the desired output length is greater than the number of scaled output pixels, the last scaled pixel is repeated. [1] If the desired output length is greater than the number of scaled output lines, the processing is cut. Table 213. Vertical input window length; register set A [9Ah[7:0]; 9Bh[3:0]] and B [CAh[7:0]; CBh[3:0]] Table 214. Horizontal output window length; register set A [9Ch[7:0]; 9Dh[3:0]] and B [CCh[7:0]; CDh[3:0]] Table 215. Vertical output window length; register set A [9Eh[7:0]; 9Fh[3:0]] and B [CEh[7:0]; CFh[3:0]]

11.2.5.9 Subaddresses A0h to A2h

Table 216. Horizontal prescaling; register set A [A0h[5:0]] and B [D0h[5:0]] Table 217. Accumulation length; register set A [A1h[5:0]] and B [D1h[5:0]] Table 218. Prescaler DC gain and FIR preﬁlter control; register set A [A2h[7:4]] and Table 219. Prescaler DC gain and FIR preﬁlter control; register set A [A2h[3:0]] and

11.2.5.10 Subaddresses A4h to A6h

0 XXX

1 XXX

Table 220. Luminance brightness control; register set A [A4h[7:0]] and B [D4h[7:0]] Table 221. Luminance contrast control; register set A [A5h[7:0]] and B [D5h[7:0]] Table 222. Chrominance saturation control; register set A [A6h[7:0]] and B [D6h[7:0]]

11.2.5.11 Subaddresses A8h to AEh

[1] Bits XSCY[15:13] are reserved and are set to logic 0. [1] Bits XSCC[15:13] are reserved and are set to logic 0. Table 223. Horizontal luminance scaling increment; register set A [A8h[7:0]; A9h[7:0]] and Table 224. Horizontal luminance phase offset; register set A [AAh[7:0]] and B [DAh[7:0]] Table 225. Horizontal chrominance scaling increment; register set A [ACh[7:0]; ADh[7:0]] Table 226. Horizontal chrominance phase offset; register set A [AEh[7:0]] and B [DEh[7:0]]

11.2.5.12 Subaddresses B0h to BFh

Table 227. Vertical luminance scaling increment; register set A [B0h[7:0]; B1h[7:0]] and Table 228. Vertical chrominance scaling increment; register set A [B2h[7:0]; B3h[7:0]] and Table 229. Vertical scaling mode control; register set A [B4h[4 and 0]] and Table 230. Vertical chrominance phase offset ‘00’; register set A [B8h[7:0]] and B [E8h[7:0]]

Programming start setup of digital video decoder part

12.1 Decoder part

The analog input AI11 expects an NTSC M, PAL B, D, G, H and I or SECAM signal in CVBS format; analog anti-alias ﬁlter and AGC active
Automatic ﬁeld detection enabled
Standard ITU 656 output format enabled on expansion (X) port
Contrast, brightness and saturation control in accordance with ITU standards
Adaptive comb ﬁlter for luminance and chrominance activated
Pins LLC, LLC2, XTOUTd, RTS0, RTS1 and RTCO are set to 3-state

Table 231. Vertical luminance phase offset ‘00’; register set A [BCh[7:0]] and B [ECh[7:0]] Table 232. Decoder part start setup values for the three main standards

12.2 Audio clock generation part

Used crystal is 24.576 MHz
Expected ﬁeld frequency is 59.94 Hz (e.g. NTSC M standard)
Generated audio master clock frequency at pin AMCLK is 256 kHz× 44.1 kHz = 11.2896 MHz
AMCLK is externally connected to AMXCLK (short-cut between pins K12 and J12)
ASCLK = 32 kHz× 44.1 kHz = 1.4112 MHz
ALRCLK is 44.1 kHz 0F chrominance gain control ACGC and CGAIN6 to CGAIN0 2A 2A 80 10 chrominance control 2 OFFU1, OFFU0, OFFV1, OFFV0, CHBW and LCBW2 to LCBW0 0E 06 00 11 mode/delay control COLO, RTP1, HDEL1, HDEL0, RTP0 and YDEL2 to YDEL0 00 00 00

12 RT signal control RTSE13 to RTSE10 and

13 RT/X port output control RTCE, XRHS, XRVS1, XRVS0,

15 VGATE start, FID change VSTA7 to VSTA0 11 11 11

16 VGATE stop VSTO7 to VSTO0 FE FE FE

12.3 Data slicer and data type control part

Closed captioning data are expected at line 21 of ﬁeld 1 (60 Hz/525 line system)
All other lines are processed as active video
Sliced data are framed by ITU 656 like SAV/EAV sequence (DID[5:0] = 3Eh⇒ MSB of SAV/EAV = 1)

Table 233. Audio clock part setup values Table 234. Data slicer start setup values

12.4 Scaler and interfaces

prsc = prescale ratio
ﬁsc = ﬁne scale ratio
vsc = vertical scale ratio The ratio is deﬁned as: In the following settings the VBI data slicer is inactive. To activate the VBI data slicer, VITX[1:0] 86h[7:6] has to be set to ‘11’. Depending on the VBI data slicer settings, the sliced VBI data is inserted after the end of the scaled video lines, if the regions of VBI data slicer and scaler overlaps. To compensate the running-in of the vertical scaler, the vertical input window lengths are extended by 2 lines to 290 lines, respectively 242 lines for XS, but the scaler increment calculations are done with 288 lines, respectively 240 lines. 5B ﬁeld offset and MSBs for horizontal and vertical offset FOFF , RECODE, X, VOFF8, X, HOFF10 to HOFF8 100000118 3 [2] 5C reserved X, X, X, X, X, X, X, X 000000000 0 5D header and data identiﬁcation code control FVREF , X, DID5 to DID0 001111103 E 5E sliced data identiﬁcation code X, X, SDID5 to SDID0 000000000 0 5F reserved X, X, X, X, X, X, X, X 000000000 0 60 slicer status byte 0 -, FC8V, FC7V, VPSV, PPV, CCV, -, - read only register 61 slicer status byte 1 -, -, F21_N, LN8 to LN4 read only register 62 slicer status byte 2 LN3 to LN0, DT3 to DT0 read only register

Table 234. Data slicer start setup values …continued

12.4.1 Trigger condition

For trigger condition STRC[1:0] 90h[1:0] not equal ‘00’. the output ﬁeld rate is reduced to 30 Hz, respectively 25 Hz.

12.4.2 Maximum zoom factor

horizontal zoom is limited to approximately 3.5, due to internal data path restrictions.

12.4.3 Examples

Table 235. Example of conﬁgurations

3 X port input 8 bit with SAV/EAV codes, no

4 X port and H port for 16-bit Y -C

83 XCLK output phase and X port

84 IGPH, IGPV, IGP0 and IGP1

86 FIFO ﬂag thresholds and

87 ICLK and IDQ output phase

93 I port output formats and

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] Condition for maximum voltage at digital inputs or I/O pins: 3.0 V < VDDD < 3.6 V. [2] Class 2 according to JESD22-A114D. [3] Class A according to EIA/JESD22-A115-A. Table 237. Limiting values together and grounded (0 V); all supply pins connected together. Table 238. Thermal characteristics

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 239. Characteristics of the digital video encoder part Tamb =0 °C to 70°C (typical values measured at Tamb =2 5°C); unless otherwise speciﬁed.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 239. Characteristics of the digital video encoder part …continued Tamb =0 °C to 70°C (typical values measured at Tamb =2 5°C); unless otherwise speciﬁed.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] Minimum value for I2C-bus bit DOWNA = 1. [2] Minimum value for I2C-bus bit DOWND = 1. voltage1⁄2VDD(DVO) is generated on chip. [4] The data is for both input and output direction. [5] This parameter is arbitrary, if PIXCLKI is looped through the VGC. [6] Tested with programming IFBP = 1. o(L) = 37.5Ω and Cext= 20 pF (typical). Tamb =0 °C to 70°C (typical values measured at Tamb =2 5°C); unless otherwise speciﬁed.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Table 240. Characteristics of the digital video decoder part levels refer to drawings and conditions illustrated inFigure67; unless otherwise speciﬁed.

1 V (p-p),−3d B

60 Hz ﬁeld - 15734 - Hz

Table 240. Characteristics of the digital video decoder part …continued levels refer to drawings and conditions illustrated inFigure67; unless otherwise speciﬁed.

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. [1] 8-bit image port output mode, expansion port is 3-stated. [2] The levels must be measured with load circuits; 1.2 kΩ at 3 V (TTL load); CL =5 0p F . [4] The crystal oscillator drive level is typically 0.28 mW. levels refer to drawings and conditions illustrated inFigure67; unless otherwise speciﬁed.

16.1 Digital video encoder part

Fig 63. Input/output timing speciﬁcation Fig 64. Horizontal input timing PIXCLKO PIXCLKI PDn any output td(CLKD) tHIGH tf tr VOH 0.5VDD(DVO) VOL tHD;DATtHD;DAT to(h) to(d) tSU;DATtSU;DAT TPIXCLK mbl789 VIH 0.5VDD(DVO) VIL VOH VOL VIH VIL HSVGC PD CBO XOFS IDEL XPIX HLEN mhb905

16.1.1 Teletext timing

Time tFD is the time needed to interpolate input data TTX and insert it into the CVBS and VBS output signal, such that it appears at tTTX = 9.78µs (PAL) or tTTX = 10.5µs (NTSC) after the leading edge of the horizontal synchronization pulse. Time tPD is the pipeline delay time introduced by the source that is gated by TTXRQ_XCLKO2 in order to deliver TTX data. This delay is programmable by register TTXHD. For every active HIGH state at output pin TTXRQ_XCLKO2, a new teletext bit must be provided by the source. Since the beginning of the pulses representing the TTXRQ signal and the delay between the rising edge of TTXRQ and valid teletext input data are fully programmable (TTXHS and TTXHD), the TTX data is always inserted at the correct position after the leading edge of the outgoing horizontal synchronization pulse. Time t i(TTXW) is the internally used insertion window for TTX data; it has a constant length that allows insertion of 360 teletext bits at a text data rate of 6.9375 Mbit/s (PAL), 296 teletext bits at a text data rate of 5.7272 Mbit/s (world standard TTX) or 288 teletext bits at a text data rate of 5.7272 Mbit/s (NABTS). The insertion window is not opened if the control bit TTXEN is zero. Using appropriate programming, all suitable lines of the odd ﬁeld (TTXOVS and TTXOVE) plus all suitable lines of the even ﬁeld (TTXEVS and TTXEVE) can be used for teletext insertion. It is essential to note that the two pins used for teletext insertion must be conﬁgured for this purpose by the correct I 2C-bus register settings. Fig 65. Vertical input timing HSVGC VSVGC CBO YOFS YPIX mhb906

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 190 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 66. Teletext timing ti(TTXW)tTTX tPD tFD CVBS/Y TTX_SRES TTXRQ_XCLKO2 text bit #: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 mhb891

16.2 Digital video decoder part

Fig 67. Data input/output timing diagram (X port, RT port and I port) mhb735 tXCLKH tr tr tf tHD;DAT tSU;DAT tSU;DAT tHD;DAT Tcy tX(I)CLKH tX(I)CLKL tf clock input XCLK data and control inputs (X port) data and control outputs X port, I port clock outputs LLC, LLC2, XCLK, ICLK and ICLK input input XDQ 2.4 V 1.5 V 0.6 V 2.6 V 1.5 V 0.6 V 2.0 V 0.8 V tOHD;DAT to(d) 2.4 V 0.6 V 2.0 V 0.8 V not valid

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 192 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC 17. Application information Fig 68. Application circuit (decoder part) mbl790 24.576 MHz SAA7108AE SAA7109AE XPD3 XPD2 XPD1 XPD0 XPD7 XPD [0:7] XPD6 XPD5 XPD4 XPD3 XPD2 XPD1 XPD0 XPD7 XPD6 XPD5 XPD4 A12 C11 B11 A11 A13 D12 C12 B12 HPD3 HPD2 HPD1 HPD0 HPD7 HPD [0:7] HPD6 HPD5 HPD4 E13 D13 C13 B13 E14 D14 C14 B14 IPD3 IPD2 IPD1 IPD0 IPD7 IPD[0:7] IPD6 IPD5 IPD4 HPD3 HPD2 HPD1 HPD0 HPD7 HPD6 HPD5 HPD4 IPD3 IPD2 IPD1 IPD0 IPD7 IPD6 IPD5 IPD4 F14 H12 H14 J14 G14 F13 G12 G13 IPCON3 IPCON2 IPCON1 IPCON0 IPCON7 IPCON [0:7] IPCON6 IPCON5 IPCON4 J12 J13 K14 L14 TEST5 R38 33 Ω R37 33 Ω open 3PAD R49 0 Ω 4.7 kΩ M14 M12 TEST4J1 TEST3J3 TEST2C10 TEST1B10 TEST0 TEST5 TEST4 TEST3 TEST2 TEST1 TEST0 H13 N13 N12 N10 H11 M13 E11 K11 VSSAd VSSAd VSSAd VSSAd VSSAd VSSEd VSSEd VSSEd VSSEd VSSId VSSId VSSId VSSXd VSSAd AGND XTOUT C104 10 pF C103 10 pF C107 1 nF L34 10 µH K12 AUDIO3 AUDIO2 AUDIO1 AUDIO0 AUDIO [0:3] L13 K13 L10 RCON0 RCON1 RCON2 RCON [0:2] BSC0 BSC1 BSC2 BSC [0:2] RES LLC open R47N14 N6 TDI_D TDO_DN5 VDDP JP45 CE_Dec. DGND 24.576 MHz32.11 MHz R12 DGNDVDDP JP43 fXTALAUDIO2 'strapping' DXGND R26 56 Ω R25 56 Ω R24 56 Ω R23 56 Ω R22 56 Ω R21 56 Ω 18 Ω C100 47 nF R19 P6AI24 18 Ω C97 47 nF R17 P7AI23 18 Ω C98 47 nF R16 P9AI22 18 Ω C99 47 nF R18 P10AI21 C109 47 nF 18 Ω C101 47 nF R15 P11AI12 18 Ω C102 47 nF R20 P13AI11 0 Ω R29 M10AOUT AI24 AI23 AI22 AI21 AI2D AI12 AI11 AI1D AOUT C110 47 nF P12 AGND DGNDAGND AGNDDGND LLC2 R27 0 Ω L12 R28 0 ΩM11 SCL SDA AMXCLK ALRCLK ASCLK LLC2 LLC RESd XTOUTd XTALOd XTALId AMCLK RTCO RTS0 RTS1 TMSd TCLKd TRSTd CE TDId TDOd SDAd SCLd XRH XCLK XDQ XRDY XTRI XRV IGP0 ICLK IDQ ITRDY IGPH IGP1 ITRI IGPV XPCON3 XPCON2 XPCON1 XPCON0 XPCON [0:5] XPCON5 XPCON4 VDD (ID11) VDD (IF11) VDD (IJ4) VDD (IJ11) VDD (IL4) VDD (IL11) VDD (XL8) VDD (EL9) VDD (EL7) VDD (EG11) VDD (ED10) VDD (AM9) VDD (AM8) VDD (AN11) N11 D10 G11 D11 F11 J11 L11 E12 F12 VDDAd VDDAd VDDAd VDDEd VDDEd VDDEd VDDEd VDDId VDDId VDDId VDDId VDDId VDDId VDDXd n.c. TVD 4.7 kΩ I2C-BUS_Adr:40h/42h R13 DGNDVDDP JP44RCON0 'strapping'

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 193 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 69. Decoupling circuit supply voltages VDD (AM8) VDD (AM9) VDD (AN11) VDD (EG11) VDD (EL9) VDD (EL7) VDD (ED10) VDD (IJ4) VDD (ID11) VDD (IF11) VDD (IJ11) VDD (IL11) VDD (IL4) VDD (XL8) C61 100 nF C58 100 nF C57 100 nF C59 100 nF C56 100 nF C60 100 nF C50 100 nF C49 100 nF C51 100 nF C48 100 nF C52 100 nF C54 100 nF C53 100 nF C55 100 nF DXGNDDGNDAGND open ferrite L36 DGNDAGND 001aae256

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 194 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC Fig 70. Application circuit (encoder part) mbl784 FLTR0 AGND +3.3 V digital DGNDDGND AGND use one capacitor for each VDDAe and VDDXe 1 nF 10 pF 0.1 mH 0.1 mF0.1 mF 0.1 mF +3.3 V analog A5F4 C5, D5 A8 B8 A9 VDD(DVO) VDDIEe A6 A10, B6, B9, C9, D9 and D6 XTALIe XTALOe V DDAe and VDDXe

75 W75 W

GREEN_VBS_CVBS HSM_CSYNC FLTR1 RED_CR_C_CVBS FLTR2

12 W1 kW

BLUE_CB_CVBS VSM DUMP DUMPRSETVSSAeVSSXeVSSIe A7 B7 SAA7108AE SAA7109AE digital inputs and outputs U Y U C U CVBSE4 DGND VSSEe Fig 71. FLTR0, FLTR1 and FLTR2 as shown inFigure70 mhb912 2.7 µH 120 pF C16 JP11 JP12 FIN FOUT C10 390 pF C13 560 pF 2.7 µH FILTER 1 = byp. ll act. AGND

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 195 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC a. With 3rd harmonic quartz. Crystal load = 8 pF . b. With fundamental quartz. Crystal load = 20 pF . c. With fundamental quartz. Crystal load = 8 pF . d. With 3rd harmonic quartz. Crystal load = 8 pF . e. With fundamental quartz. Crystal load = 20 pF . f. With fundamental quartz. Crystal load = 8 pF . g. With direct clock. h. With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high, a resistance Rs can be placed in series with the output of the oscillator XTALOd. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. Fig 72. Oscillator application for decoder part mbl796 pF pF

32.11 MHz

4.7 mH 15 pF

24.576 MHz

4.7 mH 18 pF n.c. clock

32.11 MHz or

17.1 Reconstruction ﬁlter

Figure71 shows a possible reconstruction ﬁlter for the digital-to-analog converters. Due to its cut-off frequency of∼6 MHz, it is not suitable for HDTV applications.

17.2 Analog output voltages

The analog output voltages are dependent on the total load (typical value 37.5Ω ), the digital gain parameters and the I2C-bus settings of the DAC reference currents (analog settings). a. With 3rd harmonic quartz. Crystal load = 8 pF . b. With fundamental quartz. Crystal load = 20 pF . c. With direct clock. d. With fundamental quartz and restricted drive level. When Pdrive of the internal oscillator is too high, a resistance R s can be placed in series with the oscillator output XTALOe. Note: The decreased crystal amplitude results in a lower drive level but on the other hand the jitter performance will decrease. Fig 73. Oscillator application for encoder part mbl792 pF pF

27.00 MHz

4.7 mH 18 pF n.c. clock

17.3 Suggestions for a board layout

one point directly under the device, by using a 0Ω resistor directly at the supply stage. capacitors close to the supply pins. minimize radiation energy (EMC). analog termination resistors close to the coupling capacitors. Be careful of hidden layout capacitors around the crystal application. The SAA7108AE; SAA7109AE crystal temperature depends on the PCB it is soldered on.

PCB dimensions at least 2000 mm2
PCB at least 4 layers
At least 50 vias (connecting PCB layers) close to the chip
Metal coverage at least 60 % on at least 2 PCB layers near the chip

Table 241. Digital output signals conversion range

18.1 Boundary scan test

Test Action Group (JTAG) chaired by NXP . extension ‘d’ refers to the decoder part.

18.1.1 Initialization of boundary scan circuit

the instruction register into a functional instruction such as IDCODE or BYPASS. Table 242. BST instructions supported by the SAA7108AE; SAA7109AE the latched outputs of the boundary scan register. part number and version number.

18.1.2 Device identiﬁcation codes

A device identiﬁcation register is speciﬁed in“IEEE Std. 1149.1b-1994”. It is a 32-bit register which contains ﬁelds for the speciﬁcation of the IC manufacturer, the IC part number and the IC version number. Its biggest advantage is the possibility to check for the correct ICs mounted after production and to determine the version number of the ICs during ﬁeld service. When the IDCODE instruction is loaded into the BST instruction register, the identiﬁcation register will be connected between TDIe (or TDId) and TDOe (or TDOd) of the IC. The identiﬁcation register will load a component speciﬁc code during the CAPTURE_DATA_REGISTER state of the TAP controller, this code can subsequently be shifted out. At board level this code can be used to verify component manufacturer, type and version number. The device identiﬁcation register contains 32 bits, numbered 31 to 0, where bit 31 is the most signiﬁcant bit (nearest to TDIe or TDId) and bit 0 is the least signiﬁcant bit (nearest to TDOe or TDOd); see Figure74. a. SAA7108AE. b. SAA7109AE. Fig 74. 32 bits of identiﬁcation code 000 0001 01010111 0001 0000 0100 (0111 0001 0001 0100)nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification TDIe (or TDId) TDOe (or TDOd) MSB LSB 28 27 12 11 1 0 mbl786 000 0001 01010111 0001 0000 0101 (0111 0001 0001 0100)nnnn 4-bit version code 16-bit part number 11-bit manufacturer identification TDIe (or TDId) TDOe (or TDOd) MSB LSB 28 27 12 11 1 0 mbl787

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 200 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC 19. Package outline Fig 75. Package outline SOT700-1 (LBGA156) A 1 bA 2UNIT D ye REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE 01-05-11 01-11-06 IEC JEDEC JEITA mm 1.65 0.45 0.35 1.20 0.95 15.2 14.8 15.2 14.8 130.55 0.45 0.12 0.35 DIMENSIONS (mm are the original dimensions) E 0.25 v 0.1 w 0 5 10 mm scale SOT700-1LBGA156: plastic low profile ball grid array package; 156 balls; body 15 x 15 x 1.05 mm A max. A detail X yy1 C X D E C B A A B C D E F H K G J L M N P 2468 1 0 1 2 1 4 13579 1 1 1 3 ball A1 index area ball A1 index area e e b 1/2 e 1/2 e AC C B˘ v M ˘ w M

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 201 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC 20. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application NoteAN10365 “Surface mount reﬂow soldering description”.

20.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for ﬁne pitch SMDs. Reﬂow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

20.2 Wave and reﬂow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reﬂow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature proﬁle. Leaded packages, packages with solder balls, and leadless packages are all reﬂow solderable. Key characteristics in both wave and reﬂow soldering are:
Board speciﬁcations, including the board ﬁnish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering

20.3 Wave soldering

Key characteristics in wave soldering are:

Process issues, such as application of adhesive and ﬂux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath speciﬁcations, including temperature and impurities

20.4 Reﬂow soldering

Lead-free versus SnPb soldering; note that a lead-free reﬂow process usually leads to higher minimum peak temperatures (seeFigure76) than a PbSn process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
Reﬂow temperature proﬁle; this proﬁle includes preheat, reﬂow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classiﬁed in accordance with Table243 and244 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reﬂow soldering, seeFigure76.

Table 243. SnPb eutectic process (from J-STD-020C) Table 244. Lead-free process (from J-STD-020C)

SAA7108AE_SAA7109AE_3 © NXP B.V. 2007. All rights reserved. Product data sheet Rev. 03 — 6 February 2007 203 of 208 NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC For further information on temperature proﬁles, refer to Application NoteAN10365 “Surface mount reﬂow soldering description”. MSL: Moisture Sensitivity Level Fig 76. Temperature proﬁles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = MSL limit, damage level peak temperature

20070206 Product data sheet CPCN200505019 SAA7108AE_

Legal texts have been adapted to the new company name where appropriate
Table4: Updated description for pin E2, pin G2, pin L12 and pin M11
Table240: Digital outputs; LOW-level output voltage for clocks corrected from−0.5 V to 0 V
Package outline changed from SOT472-1 to SOT700-1 SAA7108AE_ SAA7109AE_2

20040629 Product speciﬁcation - SAA7108AE_

20030326 Product speciﬁcation - -

22.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Deﬁnitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

22.2 Deﬁnitions

Draft —The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modiﬁcations or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet —A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the full data sheet shall prevail.

22.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes —NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation speciﬁcations and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use —NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications —Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the speciﬁed use without further testing or modiﬁcation. Limiting values —Stress above one or more limiting values (as deﬁned in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale —NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/proﬁle/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conﬂict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license —Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

22.4 Licenses

22.5 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. I2C-bus — logo is a trademark of NXP B.V. 23. Contact information For additional information, please visit:http://www.nxp.com For sales ofﬁce addresses, send an email to:salesaddresses@nxp.com Document status[1][2] Product status[3] Deﬁnition Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development. Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation. Product [short] data sheet Production This document contains the product speciﬁcation. ICs with Macrovision copyright protection technology This product incorporates copyright protection technology that is protected by method claims of certain U.S. patents and other intellectual property rights owned by Macrovision Corporation and other rights owners. Use of this copyright protection technology must be authorized by Macrovision Corporation and is intended for home and other limited viewing uses only, unless otherwise authorized by Macrovision Corporation. Reverse engineering or disassembly is prohibited.

8 Functional description of digital video

8.5 RGB Y -C

8.10 Oscillator and Discrete Time Oscillator

8.11 Low-pass Clock Generation Circuit

8.12.2 Teletext insertion and encoding (not

8.12.3 Video Programming System (VPS) encoding. 25 8.18 I

8.20 Programming the graphics acquisition scaler

9 Functional description of digital video

9.1.3.3 Brightness Contrast Saturation (BCS)

9.3.1 Acquisition control and task handling

(subaddresses 80h, 90h, 91h, 94h to 9Fh

9.3.2.1 Horizontal prescaler (subaddresses

9.3.2.2 Horizontal ﬁne scaling (variable phase delay

ﬁlter; subaddresses A8h to AFh

9.3.3.1 Line FIFO buffer (subaddresses 91h, B4h

9.3.3.2 Vertical scaler (subaddresses B0h to BFh

9.4 VBI data decoder and capture

9.5 Image port output formatter

9.5.1 Scaler output formatter

9.5.4 Video and text arbitration (subaddress 86h) . 82

9.5.5 Data stream coding and reference signal

generation (subaddresses 84h, 85h and 93h) 82

9.6 Audio clock generation

10 Input/output interfaces and ports of digital

10.3 Clock and real-time synchronization signals. . 89

10.6 Host port for 16-bit extension

10.7 Basic input and output timing diagrams

11.2.1 I

11.2.3 Programming register audio clock generation 154

11.2.5 Programming register interfaces

12 Programming start setup of digital video

NXP Semiconductors SAA7108AE; SAA7109AE HD-CODEC © NXP B.V. 2007. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 6 February 2007 Document identifier: SAA7108AE_SAA7109AE_3 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’.

Selected Specification

NXP Semiconductors SAA7108AE overview.

Overview

SAA7108AE is listed in the IC category. Available datasheets include documents from NXP Semiconductors. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

HD-CODEC Rev. 03-6 February 2007

Description

HD-CODEC Rev. 03-6 February 2007

Source title SAA7108AE Datasheet(PDF) - NXP Semiconductors

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