GTL2107 Datasheet PDF & Specifications

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GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator

Document overview

Manufacturer or author: NXP Semiconductors
PDF pages: 19

Technical content

Table 1. Quick reference data

6.1 Pinning

6.2 Pin description

Table 3. Pin description

7.1 Function tables

Table 3. Pin description …continued Table 4. Power supervisor power good control H = HIGH voltage level; L = LOW voltage level; X = Don’t care. Table 5. Power supervisor power good control H = HIGH voltage level; L = LOW voltage level; X = Don’t care. Table 6. Southbridge SMI_L control H = HIGH voltage level; L = LOW voltage level.

GTL2107_5 © NXP B.V. 2009. All rights reserved. [2] Open-drain input/output terminal is driven to logic LOW state by an external driver. [1] Open-drain input/output terminal is driven to logic LOW state by an external driver. Table 7. CPU SMI_L control H = HIGH voltage level; L = LOW voltage level. Table 8. PROCHOT L control H = HIGH voltage level; L = LOW voltage level. Table 9. Southbridge NMI control H = HIGH voltage level; L = LOW voltage level.

GTL2107_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 23 December 2009 6 of 19 NXP Semiconductors GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator 8. Application design-in information Fig 3. Typical application THRMTRIP L CPU1 IERR_L FORCEPR_L CPU2 SMI_L GTL2107 PROCHOT L FORCEPR_L PROCHOT L THRMTRIP L IERR_L CPU1 SMI_L CPU2 NMI NMI 10BO2 10BO1 4BI 3BI 6BI 5BI EN2 7BO2 7BO1 2BI 1BI1AO 2AO 11A 3AO 4AO 10AI1 10AI2 EN1 GND 9BI 9AO PLATFORM HEALTH MANAGEMENT CPU1 1ERR_L CPU1 THRMTRIP L CPU1 PROCHOT L CPU2 PROCHOT L NMI_L CPU2 1ERR_L CPU2 THRMTRIP L CPU1 SMI_L CPU2 SMI_L SMI_BUFF_L SOUTHBRIDGE NMI SOUTHBRIDGE SMI_L power supervisor POWER GOOD 1.5 kΩ to 1.2 kΩ VCC VTT 56 Ω 1.5 kΩ R VREF 11BI VCC VCC 11BO 002aac747 56 Ω VTT

GTL2107_5 © NXP B.V. 2009. All rights reserved. [1] The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. [2] Current into any output in the LOW state. [3] Current into any output in the HIGH state. temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150 °C.

Recommended operating conditions

Table 10. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V). Table 11. Operating conditions

GTL2107_5 © NXP B.V. 2009. All rights reserved. [1] All typical values are measured at V CC = 3.3 V and Tamb =2 5 °C. [2] The input and output voltage ratings may be exceeded if the input and output current ratings are observed. Table 11. Operating conditions …continued Table 12. Static characteristics Recommended operating conditions; voltages are referenced to GND (ground = 0 V). Tamb = −40 °Ct o + 8 5°C.

GTL2107_5 © NXP B.V. 2009. All rights reserved. [1] All typical values are at V CC = 3.3 V and Tamb =2 5 °C. [2] Includes ~7.6 ns RC rise time of test load pull-up on 11A, 1.5 k Ω pull-up and 21 pF load on 11A has about 23 ns RC rise time. Table 13. Dynamic characteristics …continued

12.1 Waveforms

VM = 1.5 V at VCC ≥ 3.0 V for A ports; VM =V ref for B ports. VM = 1.5 V for A port and Vref for B port A port to B port a. Pulse duration b. Propagation delay times Fig 4. Voltage waveforms 002aaa999 VOH 0 V tp VM VM 002aab000 3.0 V 0 V VTT VOL tPLH tPHL VrefVref 1.5 V 1.5 Vinput output PRR ≤ 10 MHz; Zo =5 0 Ω; tr ≤ 2.5 ns; tf ≤ 2.5 ns Fig 5. Propagation delay, 9BI to 9AO Fig 6. nB I to nA (I/O) or nBI to nAO open-drain outputs Fig 7. 5BI to 7BO1 or 6BI to 7BO2 Fig 8. EN2 to 5A (I/O) or 6A (I/O), or EN1 to nAO, or EN2 to nAO Fig 9. 11BI to 11A Fig 10. 11A to 11BO 002aab001 VTT 1/3VTT VOH VOL tPLH tPHL 1.5 V1.5 V Vref Vrefinput output 002aab002 VTT 1/3VTT VCC tPLZtPZL Vref Vrefinput output VOL + 0.3 V 1.5 V 002aac195 VTT 1/3VTT VTT VOL tPLH tPHL Vref Vrefinput output VrefVref 002aab005 3.0 V 0 V VOH VOL tPLZ tPZL 1.5 V 1.5 Vinput output 1.5 VVOL + 0.3 V 002aac196 VTT 0 V VOH VOL tPLZ tPZL Vref Vrefinput output 1.5 VVOL + 0.3 V 002aac197 3.0 V 0 V VTT VOL tPLH tPHL VrefVref 1.5 V 1.5 Vinput output

GTL2107_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 23 December 2009 12 of 19 NXP Semiconductors GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator 13. Test information RL — Load resistor CL — Load capacitance; includes jig and probe capacitance RT — Termination resistance; should be equal to Zo of pulse generators. Fig 11. Load circuit for A outputs (9AO) Fig 12. Load circuit for B outputs Fig 13. Load circuit for open-drain LVTTL I/O and open-drain outputs PULSE GENERATOR VO CL 50 pF 002aab981 RL 500 ΩRT VI VCC DUT PULSE GENERATOR DUT VO CL 30 pF 50 Ω 002aab264 RT VI VCC VTT PULSE GENERATOR DUT VO CL 21 pF RL 1.5 kΩ 002aab265 RT VI VCC VCC

GTL2107_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 23 December 2009 13 of 19 NXP Semiconductors GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator 14. Package outline Fig 14. Package outline SOT361-1 (TSSOP28) UNIT A 1 A2 A3 bp cD (1) E (2) (1)eH E LL p QZ ywv θ REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC JEITA mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 9.8 9.6 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.8 0.5 o o0.13 0.10.21 DIMENSIONS (mm are the original dimensions) Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 SOT361-1 MO-153 99-12-27 03-02-19 0.25 w M bp Z e 11 4 28 15 pin 1 index θ AA1 Lp Q detail X L (A )3 HE E c v M A XAD y 0 2.5 5 mm scale TSSOP28: plastic thin shrink small outline package; 28 leads; body width 4.4 mm SOT361-1 A max. 1.1

GTL2107_5 © NXP B.V. 2009. All rights reserved. Product data sheet Rev. 05 — 23 December 2009 14 of 19 NXP Semiconductors GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator 15. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description”.

15.1 Introduction to soldering

Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization.

15.2 Wave and reflow soldering

Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following:

Through-hole components
Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are:
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus SnPb soldering

15.3 Wave soldering

Key characteristics in wave soldering are:

Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave
Solder bath specifications, including temperature and impurities

15.4 Reflow soldering

Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 15) than a SnPb process, thus reducing the process window
Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board
Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 14 and 15 Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 15.

Table 14. SnPb eutectic process (from J-STD-020C) Table 15. Lead-free process (from J-STD-020C)

Section 2 “Features”, 7th bullet item: changed from “200 V MM per JESD22-A115” to “150 V MM per JESD22-A115”
Table 1 “Quick reference data”: removed symbol/parameter “Cio, input/output capacitance”
Table 12 “Static characteristics”: – Cio (A port) Typ value changed from “3.0 pF” to “5.0 pF” – Cio (A port) Max value changed from “4.0 pF” to “-” – Cio (B port) Typ value changed from “2.0 pF” to “4.0 pF” – Cio (B port) Max value changed from “3.0 pF” to “-”
Table 13 “Dynamic characteristics”: – (sub-section Vref = 0.73 V; VTT = 1.1 V) deleted tPHZ specification – (sub-section Vref = 0.73 V; VTT = 1.1 V) deleted tPZH specification – (sub-section Vref = 0.76 V; VTT = 1.2 V) deleted tPHZ specification – (sub-section Vref = 0.76 V; VTT = 1.2 V) deleted tPZH specification
Figure 8 title changed from “EN1 to 5A (I/O) or EN2 to 6A (I/O) or EN1 to nAO or EN2 to nAO” to “EN2 to 5A (I/O) or 6A (I/O), or EN1 to nAO, or EN2 to nAO”
Deleted (old) Figure 11 “EN2 to 9AO”
Deleted (old) Figure 15 “Load circuit for 9AO OFF-state to LOW and LOW to OFF-state” GTL2107_4 20070706 Product data sheet - GTL2107_3 GTL2107_3 20070129 Objective data sheet - GTL2008_GTL2107_2 GTL2008_GTL2107_2 20060926 Product data sheet - GTL2008_1 GTL2008_1 20060502 Product data sheet - -

18.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com.

18.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

18.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control — This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Quick reference data — The Quick reference data is an extract of the product data given in the Limiting values and Characteristics sections of this document, and as such is not complete, exhaustive or legally binding.

18.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 19. Contact information For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docu ment contains the product specification.

NXP Semiconductors GTL2107 12-bit GTL−/GTL/GTL+ to LVTTL translator © NXP B.V. 2009. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 23 December 2009 Document identifier: GTL2107_5 Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. 20. Contents

Selected Specification

NXP Semiconductors GTL2107 overview.

Overview

GTL2107 is listed in the IC category. Available datasheets include documents from NXP Semiconductors. DigiCamel provides a local PDF and searchable HTML technical text for online reference.

Summary

12-bit GTL??GTL/GTL+ to LVTTL translator Rev. 05-23 December 2009

Description

12-bit GTL??GTL/GTL+ to LVTTL translator Rev. 05-23 December 2009

Source title GTL2107 Datasheet(PDF) - NXP Semiconductors

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