SAA4700

SAA4700 PHILIPS

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Technical content

Preliminary specification File under Integrated Circuits, IC02 March 1991 INTEGRATED CIRCUITS SAA4700 VPS dataline processor

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700

FEATURES

• Adaptive sync slicer with buffered composite sync output VCS
• Adaptive data slicer
• Data rate clock regenerator
• Field selection and line 16 decoding
• Startcode and biphase check
• Data valid output
• Storage of data line information in a 40 bit register bank
• I2C-bus transmission GENERAL DESCRIPTION The SAA4700 is a bipolar integrated circuit designed for use in dataline receivers and incorporates a dataline slicer and decoder. The slicer extracts the dataline signal from the video signal and regenerates the data clock. It also provides signals for the decoder in order to decode the binary data that is transmitted in line 16 of every first field of the composite video signal (video programming signal and video recording programming by Teletext, VPS and VPT systems). The decoded information out of words 5 and 11 to 14 is accessed via the built-in I 2C-bus interface. This information then can be used for programming a video cassette recorder in order to start and stop a recording of a television program at the correct aligned time, regardless of a delay or extension in the transmission time of the required program. QUICK REFERENCE DATA ORDERING AND PACKAGE INFORMATION Note 1. SOT102-1; 1996 December 4. SYMBOL PARAMETER MIN. TYP. MAX. UNIT V P supply voltage (pins 15 and 16) 4.5 5 5.5 V IP total supply current − 18 23 mA Vi CVBS CVBS input signal sync-to-white (peak-to-peak value) 0.5 1 1.4 V T amb operating ambient temperature 0 −+ 70 °C EXTENDED TYPE NUMBER PACKAGE PINS PIN POSITION MATERIAL CODE SAA4700 18 DIL plastic SOT102 (1)

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 Fig.1 Block diagram and test circuit. handbook, full pagewidth MEH095 8.2 kΩ 0.1 µF external reset VP nF SYNC SEPARATOR FIELD SELECTOR LINE 16 DECODER I2C-BUS CONTROL OUTPUT CONTROLLER INPUT CONTROLLER 40-BIT DATA REGISTER 40-BIT DATA LATCH MULTIPLEXER DATA SLICER CLOCK REGENERATOR PLL WITH

5 MHz VCO AND

n.c. SDA to VP 75 kΩ (2%) 4.7 kΩ CVBS CSO 4.7 nF 1 nF (test line 16) DAV 470 pF 4.7 nF 0.1 µF 5 6 11 12 7 AD = LOW 14 3 4 15 16 10 data VCS line 16 +5 V FUNCTIONAL DESCRIPTION Dataline 16 The information in dataline 16 consists of fifteen 8-bit words; the total information content is shown in Table 1; and the organization of transmitted bytes is shown in Table 2. Out of the fifteen possible 8-bit words the SAA4700 extracts words 5 and 11 to 14. The contents of these words can be read via the built-in I 2C-bus interface. The circuit is fully transparent, thus each bit is transferred without modification with only the sequence of words being changed. Words 11 to 14 are transmitted first followed by word 5. By evaluating the sliced sync signal the circuit can identify the beginning of dataline 16 in the first field. The dataline decoder stage releases the start code detector. When a correct start code is detected (for timing of start code detection see Fig.3) words 5 and 11 to 14 are decoded, checked for biphase errors and stored in a register bank. If no biphase error has occurred, the contents of the register bank are transferred to a second register bank by the data valid control signal. If the system has been addressed, this transfer will be delayed until the next start or stop condition of the I 2C-bus has been received. The last bit of correct information on the dataline remains available until it is read via the I 2C-bus. Once the stored information has been read it is considered to be no longer valid and the internal new data flag is reset. Subsequently, if the circuit is addressed, the only VPS data that will be sent back is ”FFF to F”. The same conditions apply after power-up when no data can be read out. New data is available after reception of another error-free dataline 16.

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 PINNING SYMBOL PIN DESCRIPTION CVBS 1 video signal input (CVBS from TV) SYNC 2 sync amplitude input (CVBS from TV) GND1 3 analog ground (0 V) GND2 4 digital ground (0 V) C black 5 capacitor for black level CSO 6 composite sync output AD 7 address set input SCL 8 I 2C-bus clock line SDA 9 I 2C-bus data line RS 10 reset input active LOW TP 11 test point for line 16 decoder DA V 12 data available output active LOW R osc 13 oscillator resistor for frequency adjustment CP 14 test point clock pulse V P1 15 +5 V supply voltage (digital part) VP2 16 +5 V supply voltage (analog part) C ph 17 capacitor of phase detector n.c. 18 not connected PIN CONFIGURATION Fig.2 Pin configuration handbook, halfpage SAA4700 MBH796 CVBS SYNC GND1 GND2 CSO AD SCL SDA C black n.c. RS TP DAV CP R osc VP1 VP2 C ph External reset The circuit provides an internal power-on reset. When using this facility pin 10 should be connected to V P or, if external reset (RESET = LOW) is to be used pin 10 should be prepared by connecting pin 10 via a 10 kΩ pull-up resistor to V Reset forces the following: 2C-bus not to acknowledge -DAV output to go HIGH (pin 12) -I2C-bus transfer register to “FFF” CVBS input The CVBS signal is applied to the sync separator (pin 2) via a decoupling capacitor and to the data slicer (pin 1) via an RC high-pass filter. To enable proper storage of the sync value in the decoupling capacitor, the sync generator output resistance should not exceed 1 kΩ . Black level The capacitor connected to pin 5 stores the black level value for the adaptive sync slicer. Composite sync output (CSO) A composite sync output signal for customer application is provided (pin 6). DA V output The data available output pin 12 is set LOW after an error free dataline 16 is received. DAV returnes to HIGH after the beginning of the next first field. If no valid data is availableDAV remains HIGH. A short duration pulse of 1µs (Fig.5) is inserted at the beginning of dataline 16; it will ensure that a HIGH-to-LOW transmission occurs which can then be used for triggering.

5 MHz VCO and phase detector

The resistor connected between pin 13 and V P2 determines the current into the voltage controlled oscillator. The RC network connected to pin 17 acts as a low-pass filter for the phase detector. Power supply To prevent crosscoupling the circuit is provided with separate ground and supply pins for analog and digital parts (pins 3, 4, 15 and 16).

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 Table 1 Information per word in dataline 16 Table 2 VTR control information of dataline 16 Note 1. address range; NC = nation code; PC = program source code; X = 0 or 1 (bit) word number content 1 run in 2 start code 3 program source identification (binary coded) 4 program source identification (ASCII sequential) sound and VTR control information 6 program/test picture identification 7 internal information exchange 8 address assignment of signal distribution 9 address assignment of signal distribution 10 messages/commands VTR control/information12 15 reserve VTR CONTROL INFORMATION Word number 51 1 1 2 1 3 1 4 18 0 7 8 1 5 1 6 2 3 2 4 3 1 Bit number X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X X Label binary Day Month Hour Minute NationWord 5: AD (1) Progr. source Bit1 Bit2 Status Special system code0 0 2-channel 0 1 Mono System status code 1 0 Stereo 1 X 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1NC.. .NC PC...PC1 1 2-channel Pause code Bit3 Bit4 Status 1 X 0 0 0 0 0 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1NC.. .NC PC...PC1 0 free 0 1 free Interrupt code .NC

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 Fig.3 Timing diagram of start code detection. handbook, full pagewidth MEH097 0.2 µs 00 10 word 3start code (word 2)run in (word 1) clock signal to time base data to controller start code pulse error biphase error pulse (ignored in word 2) Fig.4 Timing diagram of dataline 16; modulation depth 71.4%. handbook, full pagewidth MEH09848 µs12.5 ±1.5 µs 1 V white level sync level 0.7 V

0.5 V ±5%

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 Fig.5 Timing diagram of the data available output and word latch pulses. handbook, full pagewidth 64 µs 48 µs 12.5 µs 1 µs MEH096 DAV output CVBS input line 16 start code pulse word 5 latch pulse word 11 latch pulse word 14 latch pulse word 1 word 2 word 3 word 4 word 5 word 6 word 7 word 8 word 9 word 10 word 11 word 12 word 13 word 14 word 15

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 LIMITING VALUES In accordance with the Absolute Maximum System (IEC 134). Ground pins 3 and 4 as well as supply pins 15 and 16 tied together. THERMAL RESISTANCE CHARACTERISTICS VP1 = VP2 = 5 V; Tamb = 25°C; CVBS signal according to VPS and VPT standard and measurements taken in Fig.1, unless otherwise specified. SYMBOL PARAMETER MIN. MAX. UNIT VP1 supply voltage (pin 15) −0.5 6.0 V VP2 supply voltage (pin 16) −0.5 6.0 V Tstg storage temperature range −20 125 °C Tamb operating ambient temperature range 0 +70 °C SYMBOL PARAMETER MIN. MAX. UNIT R th j-a from junction to ambient in free air − 78 K/W SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT VP1, VP2 supply voltages (pins 15 and 16) 4.5 5 5.5 V IP total supply current I 15 + I16 − 18 23 mA CVBS and sync inputs(pins 1 and 2) Vi CVBS CVBS input signal (peak-to-peak value) sync-to-white note 1; Fig.4 0.5 1 1.4 V Vi data data input signal (peak-to-peak value, pin 1) line 16; Fig.4 250 500 700 mV Vi sync sync input signal (peak-to-peak value, pin 2) 100 − 600 mV R S source resistance −− 1k Ω Composite sync output(pin 6) VOL output voltage LOW −− 0.4 V VOH output voltage HIGH 2.4 −− V IOL output current LOW −− 200 µA IOH output current HIGH −−− 500 µA td sync separator delay time − 0.3 −µ s DA V output(pin 12) note 2 VOL output voltage LOW −− 0.4 V VOH output voltage HIGH 2.4 −− V IOL output current LOW −− 500 µA IOH output current HIGH − 0.01 1 µA

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 Notes to the characteristics 1. With standard sync and data amplitude of 68% to 75% black-white. 2. If the open collector output DAV is used, a pull-up resistor to VP1 is necessary. SCL and SDA (pins 8 and 9) VIL input voltage LOW −− 1.5 V VIH input voltage HIGH 3 −− V II input current 0.9V P −−± 10 µA C I input capacitance −− 10 pF VO ACK output voltage during acknowledge on pin 9 I OL = 3 mA −− 0.4 V tr rise time −− 1 µs tf fall time −− 0.3 µs tp L pulse duration LOW 4.7 −−µ s tp H pulse duration HIGH 4.0 −−µ s SCL clock frequency −− 100 kHz AD set input(pin 7) note 2 VIL input voltage LOW address 23H 0 − 0.4 V VIH input voltage HIGH address 21H 2.4 − VP V RESET input (pin 10) note 2 VIL input voltage LOW reset active −− 0.4 V VIH input voltage HIGH reset non-active 2.4 −− V IIL input current LOW −−− 10 µA IIH input current HIGH − 0.01 1 µA SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 I2C-BUS FORMAT Remarks to I2C-bus transmission

• the MSB of each word is transmitted first
• there is no restriction on the number of words to be transmitted, but if more than five words are requested, the following content will be “FF” continuously.
• Normally every dataline transmission has to be ended with STOP condition by non-acknowledge of the controller. S SLAVE ADDRESS A DATA A DATA A DATA A DATA A DATA P S = start condition SLAVE ADDRESS = 0010 0001 or 0010 0011 for set input AD = HIGH respectively LOW on pin 7 (the circuit is only a slave transmitter) A = acknowledge, generated by the slave or the master DATA = five data bytes, see words in Table 1 P = stop condition respectively non-acknowledge by the microcontroller Fig.6 Application circuit. handbook, full pagewidth MEH135 4.7 kΩ CVBS 8.2 kΩ 75 kΩ (2%) DAV 0.1 µF1 nF 470 pF +5 VVP 4.7 nF 18 17 16 15 14 13 12 11 10 123456 CSO SCL SDA 789 n.c. SAA4700 4.7 nF nF 0.1 µF

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 PACKAGE OUTLINE REFERENCESOUTLINE VERSION EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SOT102-1 93-10-14 95-01-23 UNIT A max. 12 b1 (1) (1) (1) b2 cD E e M ZHL mm DIMENSIONS (inch dimensions are derived from the original mm dimensions) A min. A max. b max.wM Ee1 1.40 1.14 0.53 0.38 0.32 0.23 21.8 21.4 6.48 6.20 3.9 7.80 9.5 inches 0.055 0.044 0.021 0.015 0.013 0.009 1.40 1.14 0.055 0.044 0.86 0.84 0.26 0.24 0.15 0.31 0.37 M H c (e )1 M E A L seating plane w M e D A 2 Z b E pin 1 index 0 5 10 mm scale Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. DIP18: plastic dual in-line package; 18 leads (300 mil) SOT102-1

Philips Semiconductors Preliminary specification VPS dataline processor SAA4700 SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our “IC Package Databook” (order code 9398 652 90011). Soldering by dipping or by wave The maximum permissible temperature of the solder is 260 °C; solder at this temperature must not be in contact with the joint for more than 5 seconds. The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (T stg max). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Repairing soldered joints Apply a low voltage soldering iron (less than 24 V) to the lead(s) of the package, below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300°C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400°C, contact may be up to 5 seconds. DEFINITIONS LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale. PURCHASE OF PHILIPS I 2C COMPONENTS Data sheet status Objective specification This data sheet contains target or goal specifications for product development. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later. Product specification This data sheet contains final product specifications. Limiting values Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability.

Application information

Where application information is given, it is advisory and does not form part of the specification. Purchase of Philips I 2C components conveys a license under the Philips’ I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.