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MMA65XX

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Dual-Axis SPI Inertial Sensor Rev. 3, 03/2012

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Selected specification: NXP Semiconductors

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MMA65xx, Dual Axis SPI Inertial Sensor

Document overview

Manufacturer or author: NXP Semiconductors
PDF pages: 56

Technical content

Features

± 8 0 g, ±105 g or ±120 g full-scale range, independently specified for each axis
3.3 V or 5 V single supply operation
SPI-compatible serial interface
12-bit digital signed or unsigned SPI data output
Independent programmable arming functions for each axis
Twelve low-pass filter options, ranging from 50 Hz to 1000 Hz
Optional offset cancellation with > 6 s averaging period and < 0.25 LSB/s slew rate
Pb-free, 16-pin QFN, 6 mm x 6 mm x 1.98 mm package Referenced Documents
AEC-Q100, Revision G, dated May 14, 2007 ( http://www.aecouncil.com/

Ordering information

MMA6519KCW ±80 g ±80 g 98ASA00690D Tubes MMA6525KCW ±105 g ±105 g 98ASA00690D Tubes MMA6527KCW ±120 g ±120 g 98ASA00690D Tubes MMA6519KCWR2 ±80 g ±80 g 98ASA00690D Tape & Reel MMA6525KCWR2 ±105 g ±105 g 98ASA00690D Tape & Reel MMA6527KCWR2 ±120 g ±120 g 98ASA00690D Tape & Reel MMA65xx Bottom view Pb-free, 16-pin QFN 6 mm x 6 mm x 1.98 mm package

2 NXP Semiconductors

1 General Description

1.1 Application diagram

Figure 1. Application Diagram Table 1. External Component Recommendations

1.2 Internal block diagram

Figure 2. Internal Block Diagram

1.3 Device orientation and part marking

Figure 3. Device Orientation Diagram Figure 4. Part Marking

8 MHz

1 MHz

1 MHz Regulator

4 NXP Semiconductors

1.4 Pin Connections

Figure 5. Top View, 16-Pin QFN Package Table 2. Pin Descriptions connected between this pin and VSSA. Reference Figure 1. 2V SS Digital GND This pin is the power suppl y return node for the digital circuitry. connected between this pin and VSS. Reference Figure 1. 4V SS Digital GND This pin is the power suppl y return node for the digital circuitry. Section 3.8.11. If unused, this pin must be left unconnected. Section 3.8.11. If unused, this pin must be left unconnected.

7 TEST /

8 MISO SPI Data Out This pin functions as the serial data output for the SPI port. 9V CC Supply This pin supplies power to the device. An external capacitor must be connected between this pin and VSS. 10 SCLK SPI Clock This input pin provides the serial clock to the SPI port. An internal pulldown device is connected to this pin. 11 MOSI SPI Data In This pin functions as the serial data input to the SPI port. An internal pulldown device is connected to this pin. 12 CS Chip Select This input pin provides the chip select for t he SPI port. An internal pullup device is connected to this pin. 13 V SSA Analog GND This pin is the power s upply return node for analog circuitry. 14 N/C No Connect Not internally connected. This pin can be unconnected or connected to VSS in the application. 15 N/C No Connect Not internally connected. This pin can be unconnected or connected to VSS in the application. 16 V SSA Analog GND This pin is the power s upply return node for analog circuitry.

17 PAD Die Attach

Corner Pads The corner pads are internally connected to VSS.

2 Electrical Characteristics

2.1 Maximum Ratings

Maximum ratings are the extreme limits to which the device can be exposed without permanently damaging it.

2.2 Operating Range

The operating ratings are the limits normally expected in the application and define the range of operation. # Rating Symbol Value Unit 1 Supply Voltage VCC -0.3 to +7.0 V( 3 ) 2 VREG, VREGA VREG -0.3 to +3.0 V( 3 ) 3 SCLK, CS, MOSI,VPP/TEST VIN -0.3 to VCC + 0.3 V( 3 ) 4 ARM_X, ARM_Y VIN -0.3 to VCC + 0.3 V( 3 ) 5 MISO (high impedance state) VIN -0.3 to VCC + 0.3 V( 3 ) 6 Powered Shock (six sides, 0.5 ms duration) gpms ±1500 g (5,18) 7 Unpowered Shock (six sides, 0.5 ms duration) gshock ±2000 g (5,18) 8 Drop Shock (to concrete surface) hDROP 1.2 m( 5 ) Electrostatic Discharge Human Body Model (HBM) Charge Device Model (CDM) Machine Model (MM) VESD VESD VESD ±2000 ±750 ±200 V V V (5) (5) (5)

12 Storage Temperature Range Tstg -40 to +125 °C (5)

13 Thermal Resistance - Junction to Case qJC 2.5 °C/W (14) # Characteristic Symbol Min Typ Max Units Supply Voltage Standard Operating Voltage, 3.3 V Standard Operating Voltage, 5.0 V VCC VL +3.135 VTYP +3.3 +5.0 VH +5.25 V V (15) (15) Operating Ambient Temperature Range Verified by 100% Final Test T A TL -40 — TH +105 C (1) 17 Power-on Ramp Rate (VCC)V CC_r 0.000033 — 3300 V/ μs (19)

6 NXP Semiconductors

2.3 Electrical Characteristics - Power Supply and I/O

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified # Characteristic Symbol Min Typ Max Units 18 Supply Current * I DD 4.0 — 8.0 mA (1) Power Supply Monitor Thresholds (See Figure 9) V CC Under Voltage (Falling) VREG Under Voltage (Falling) VREG Over Voltage (Rising) VREGA Under Voltage (Falling) VREGA Over Voltage (Rising) Power Supply Monitor Hysteresis VCC Under Voltage VREG Under Voltage, VREG Over Voltage VREGA Under Voltage, VREGA Over Voltage V CC_UV_f VREG_UV_f VREG_OV_r VREGA_UV_f VREGA_OV_r VHYST VHYST VHYST 2.74 2.10 2.65 2.20 2.65 100 100 100 3.02 2.25 2.85 2.35 2.85 110 210 150 V V V V V mV mV mV (3,6) (3,6) (3,6) (3,6) (3,6) (3) (3) (3) Power Supply RESET Thresholds (See Figure 6, and Figure 9) V REG Under Voltage RESET (Falling) VREG Under Voltage RESET (Rising) VREG RESET Hysteresis VREG_UVR_f VREG_UVR_r VHYST 1.764 1.876 2.024 2.152 140 V V mV (3,6) (3,6) (3) Internally Regulated Voltages VREG VREGA VREG VREGA 2.42 2.42 2.50 2.50 2.58 2.58 V V (1,3) (1,3) External Filter Capacitor (CVREG, CVREGA) Value ESR (including interconnect resistance) CVREG, CVREGA ESR 700 1000 1500 400 nF mΩ (19) (19) Power Supply Coupling 50 kHz ≤ fn ≤ 20 MHz

20 MHz ≤ fn ≤ 100 MHz

0.004 0.004 LSB/mv LSB/mv (3) (19) Output High Voltage (MISO, PCM_X, PCM_Y) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (ILoad = -1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (ILoad = -1 mA) VOH_3 VOH_5 VCC - 0.2 VCC - 0.4 V V (2,3) (2,3) Output Low Voltage (MISO, PCM_X, PCM_Y) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (ILoad = 1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (ILoad = 1 mA) VOL_3 VOL_5 0.2 0.4 V V (2,3) (2,3) Open Drain Output High Voltage (ARM_X, ARM_Y) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (IARM = -1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (IARM = -1 mA) VODH_3 VODH_5 VCC - 0.2 VCC - 0.4 V V (2,3) (2,3) Open Drain Output Pulldown Current (ARM_X, ARM_Y) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (VARM = 1.5 V) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (VARM = 1.5 V) IODPD_3 IODPD_5 100 100 μA μA (2,3) (2,3) Open Drain Output Low Voltage (ARM_X, ARM_Y) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (IARM = 1 mA) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (IARM = 1 mA) VODH_3 VODH_5 0.2 0.4 V V (2,3) (2,3) Open Drain Output Pullup Current (ARM_X, ARM_Y) 3.15 V ≤ (VCC - VSS) ≤ 3.45 V (VARM = 1.5 V) 4.75 V ≤ (VCC - VSS) ≤ 5.25 V (VARM = 1.5 V) IODPU_3 IODPU_5 -100 -100 -50 -50 μA μA (2,3) (2,3) 48 Input High Voltage CS, SCLK, MOSI * V IH 2.0 — — V (3,6) 49 Input Low Voltage CS, SCLK, MOSI * V IL —— 1 . 0 V ( 3 , 6 ) 50 Input Voltage Hysteresis CS, SCLK, MOSI * V I_HYST 0.125 — 0.500 V (19) Input Current High (at VIH) (SCLK, MOSI) Low (at VIL) (CS) IIH IIL -70 -50 -30 μA μA (2,3) (2,3)

2.4 Electrical Characteristics - Sensor and Signal Chain

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified. # Characteristic Symbol Min Typ Max Units Digital Sensitivity (SPI) 80g (12-Bit Output) 105.5g (12-Bit Output) 120g (12-Bit Output) SENS SENS SENS 24.0 18.2 16.0 LSB/g LSB/g LSB/g (1,9) (1,9) (1,9) Sensitivity Error T A = 25 °C -40 °C ≤ TA ≤ 105 °C -40 °C ≤ TA ≤ 105 °C, VCC_UV_f ≤ VCC - VSS ≤ VL ΔSENS ΔSENS ΔSENS (1) (1) (3) 59a 60a 61a 62a Offset at 0g (105.5g 120g Range, No Offset Cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, V CC_UV_f ≤ VCC - VSS ≤ VL 12 bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL OFFSET OFFSET OFFSET OFFSET 1988 -60 1988 -60 2048 2108 +60 1988 -60 LSB LSB LSB LSB (1) (1) (3) (3) 63a 64a 65a 66a Offset at 0g (80g Range, No Offset Cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, V CC_UV_f ≤ VCC - VSS ≤ VL 12 bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL OFFSET OFFSET OFFSET OFFSET 1968 -80 1968 -80 2048 2128 +80 1968 -80 LSB LSB LSB LSB (1) (1) (3) (3) 67b 68b 69b 70b Offset at 0g (With Offset Cancellation) 12 bits, unsigned 12 bits, signed 12 bits, unsigned, V CC_UV_f ≤ VCC - VSS ≤ VL 12 bits, signed, VCC_UV_f ≤ VCC - VSS ≤ VL OFFSET OFFSET OFFSET OFFSET 2047.75 -0.25 2047.75 -0.25 2048 2048.25 +0.25 2048.25 +0.25 LSB LSB LSB LSB (9,7) (9,7) (9) (9) Offset Monitor Thresholds Positive Threshold (12 bits signed) Negative Threshold (12 bits signed) OFFTHR POS OFFTHRNEG 100 -100 LSB LSB (7) (7) Range of Output (SPI, 12 bits, unsigned) Normal Fault Response Code Unused Codes Unused Codes RANGE FAULT UNUSED UNUSED 128 3969 3968 127 4095 LSB LSB LSB LSB (7) (7) (7) (7) Range of Output (SPI, 12 bits, signed) Normal Unused Codes Unused Codes RANGE UNUSED UNUSED -1920 -2047 1921 1920 -1921 2047 LSB LSB LSB (7) (7) (7)

80 Nonlinearity * NL

OUT -1 — 1 % FSR (3) System Output Noise RMS (12 bits, All Ranges, 400 Hz, 3-pole LPF) Peak to Peak (12 bits, All Ranges, 400 Hz, 3-pole LPF) nRMS nP-P LSB LSB (3) (3) Cross-Axis Sensitivity V ZX VYX VZY VXY V ZX VYX VZY VXY (3) (3) (3) (3)

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2.5 Self Test

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified. # Characteristic Symbol Min Typ Max Units Self Test Output Change (Ref Section 3.6) 80g, T A = 25 °C 80g, -40 °C ≤ TA ≤ 105 °C 80g, -40 °C ≤ TA ≤ 105 °C, VCC_UV_f ≤ VCC - VSS ≤ VL 105.5 g, TA = 25 °C 105.5 g, -40 °C ≤ TA ≤ 105 °C 105.5 g, -40 °C ≤ TA ≤ 105 °C, VCC_UV_f ≤ VCC - VSS ≤ VL 120g, TA = 25 °C 120g, -40 °C ≤ TA ≤ 105 °C 120g, -40 °C ≤ TA ≤ 105 °C, VCC_UV_f ≤ VCC - VSS ≤ VL ΔST80_25 ΔST80_ΔT ΔST80_ΔTΔV ΔST105_25 ΔST105_ΔT ΔST105_ΔTΔV ΔST120_25 ΔST120_ΔT ΔST120_ΔTΔV ΔSTMIN 582 545 545 442 414 414 387 363 363 ΔST NOM 727 727 727 553 553 553 484 484 484 ΔST MAX 872 909 909 663 690 690 581 605 605 LSB LSB LSB LSB LSB LSB LSB LSB LSB (1) (1) (3) (1) (1) (3) (1) (1) (3) Self Test Cross-Axis Output Y-Axis Output with X-Axis Self Test X-Axis Output with Y-Axis Self Test ΔSTCrossAxis ΔSTCrossAxis -10 -10 +10 +10 LSB LSB (1) (1) Self Test Output Accuracy Δ from Stored Value, including Sensitivity Error -40 °C ≤ T A ≤ 105 °C (Ref Section 3.6) ΔSTACC -10 — +10 % (3) 100 Sigma Delta Modulator Range X/Y-Axis, Any Range Positive/Negative g ADCl_Clip 375 400 450 g (19) 101 Acceleration (without hitting internal g-cell stops) X/Y-Axis, Any Range Positive/Negative g g-cell_Clip 500 560 600 g (19)

2.6 Dynamic Electrical Char acteristics - Signal Chain

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified. # Characteristic Symbol Min Typ Max Units 102 103 104 DSP Sample Rate (LPF 0,1,2,3,4,5) DSP Sample Rate (LPF 8,9,10,11,12,13) Interpolation Sample Rate tS tS tINTERP 64/fOSC 128/fOSC tS/2 s s s (7) (7) (7) 105 106 Data Path Latency (excluding g-cell and Low-pass Filter) TS = 64/fOSC TS = 128/fOSC tDataPath_8 tDataPath_16 33.0 51.9 34.8 54.6 36.5 57.4 μs μs (7,16) (7,16) 107 108 109 110 111 112 Low-Pass Filter (ts = 8μs) Cutoff frequency 0: 100 Hz, 4-pole Cutoff frequency 1: 300 Hz, 4-pole Cutoff frequency 2: 400 Hz, 4-pole Cutoff frequency 3: 800 Hz, 4-pole Cutoff frequency 4: 1000 Hz, 4-pole Cutoff frequency 5: 400 Hz, 3-pole fC0(LPF) fC1(LPF) fC2(LPF) fC3(LPF) fC4(LPF) fC5(LPF) 285 380 760 950 380 100 300 400 800 1000 400 105 315 420 840 1050 420 Hz Hz Hz Hz Hz Hz (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) 113 114 115 116 117 118 Low-Pass Filter (ts = 16μs) Cutoff frequency 8: 50 Hz, 4-pole Cutoff frequency 9: 150 Hz, 4-pole Cutoff frequency 10: 200 Hz, 4-pole Cutoff frequency 11: 400 Hz, 4-pole Cutoff frequency 12: 500 Hz, 4-pole Cutoff frequency 13: 200 Hz, 3-pole fC8(LPF) fC9(LPF) fC10(LPF) fC11(LPF) fC12(LPF) fC13(LPF) 47.5 142.5 190 380 475 190 150 200 400 500 200 52.5 157.5 210 420 525 210 Hz Hz Hz Hz Hz Hz (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) (3,7,17) 119 120 121 122 123 124 125 Offset Cancellation (Normal Mode, 12-Bit Output) Offset Averaging Period Offset Slew Rate Offset Update Rate Offset Correction Value per Update Positive Offset Correction Value per Update Negative Offset Correction Threshold Positive Offset Correction Threshold Negative OFFAVEPER OFFSLEW OFFRATE OFFCORRP OFFCORRN OFFTHP OFFTHN 6.29146 0.2384 1049 0.25 -0.25 0.125 0.125 s LSB/s ms LSB LSB LSB LSB (3,7) (3,7) (3,7) (3,7) (3,7) (3,7) (3,7) 126 127 128 129 130 131 Self Test Activation Time (CS rising edge to 90% of ST Final Value) Cutoff frequency 0: 100 Hz, 4-pole Cutoff frequency 1: 300 Hz, 4-pole Cutoff frequency 2: 400 Hz, 4-pole Cutoff frequency 3: 800 Hz, 4-pole Cutoff frequency 4: 1000 Hz, 4-pole Cutoff frequency 5: 400 Hz, 3-pole ST_ACT100 ST_ACT300 ST_ACT400 ST_ACT800 ST_ACT1000 ST_ACT400_3 7.00 3.00 2.50 1.70 1.60 2.40 ms ms ms ms ms ms (19) (19) (19) (19) (19) (19)

132 Offset Monitor Bypass Time after Self Test Deactivation tST_OMB — 320 — tS (3,7)

133 Time Between Acceleration Data Requests (Same Axis) tACC_REQ 15 — — μs (3,7,20)

Arming Output Activation Time (ARM_X, ARM_Y, IARM = 200μA) Moving Average and Count Arming Modes (2,3,4,5) Unfiltered Mode Activation Delay (Reference Figure 30) Unfiltered Mode Arm Assertion Time (Reference Figure 30) tARM tARM_UF_DLY tARM_UF_ASSERT 5.00 1.51 1.51 6.579 μs μs μs (3,12) (3,12) (3)

137 Sensing Element Natural Frequency fgcell 10791 13464 15879 Hz (19)

138 Sensing Element Cutoff Frequency (-3 dB ref. to 0 Hz) fgcell 0.851 1.58 2.29 kHz (19) 139 Sensing Element Damping Ratio ζgcell 2.46 4.31 9.36 — (19)

140 Sensing Element Delay (@100 Hz) fgcell_delay 70 101 187 μs (19)

141 Sensing Element Step Response (0% - 90%) tStep_gcell — — 200 μs (19)

10 NXP Semiconductors

2.7 Dynamic Electrical Char acteristics - Supply and SPI

VL ≤ (VCC - VSS) ≤ VH, TL ≤ TA ≤ TH, |ΔTA| < 25 K/min unless otherwise specified 1. Parameters tested 100% at final test. 2. Parameters tested 100% at wafer probe. 3. Parameters verified by characterization 4. (*) Indicates a critical characteristic. 5. Verified by qualification testing. 6. Parameters verified by pass/fail testing in production. 7. Functionality verified 100% via scan. Timing characteristic is directly determined by internal oscillator frequency. 8. N/A. 9. Devices are trimmed at 100 Hz with 1000 Hz low-pass filter option selected. Response is corrected to 0 Hz response. 10. Low-pass filter cutoff frequencies shown are -3 dB referenced to 0 Hz response. 11. Power supply ripple at frequencies greater than 900 kHz should be minimized to the greatest extent possible. 12. Time from falling edge of CS to ARM_X, ARM_Y output valid 13. N/A. 14. Thermal resistance between the die junction and the ex posed pad; cold plate is attached to the exposed pad. 15. Device characterized at all values of V L and VH. Production test is conducted at all typical voltages (VTYP) unless otherwise noted. 16. Data Path Latency is the signal latency from g-cell to SPI output disregarding filter group delays. 17. Filter characteristics are specified independently, and do not include g-cell frequency response. 18. Electrostatic Deflection Test completed during wafer probe. 19. Verified by Simulation. 20. Acceleration Data Request timi ng constraint only applies for proper operation of the Arming Function. # Characteristic Symbol Min Typ Max Units 144 145 146 Power-On Recovery Time (VCC = VCCMIN to first SPI access) Power-On Recovery Time (Internal POR to first SPI access) SPI Reset Activation Time (CS high to Reset) tOP tOP tSPI_RESET 840 300 ms μs ns (3) (3,7) (7) 147 148 Internal Oscillator Frequency Test Frequency - Divided from Internal Oscillator *f OSC fOSCTST 7.6 0.95 8.4 1.05 MHz MHz (7) (1) 149 Serial Interface Timing (See Figure 7, CMISO ≤ 80pF, RMISO ≥ 10kW) Clock (SCLK) period (10% of VCC to 10% of VCC) *t SCLK 120 — — ns (3)

150 Clock (SCLK) high time (90% of VCC to 90% of VCC)* t SCLKH 40 — — ns (3)

151 Clock (SCLK) low time (10% of VCC to 10% of VCC)* t SCLKL 40 — — ns (3)

152 Clock (SCLK) rise time (10% of VCC to 90% of VCC)t SCLKR —1 54 0 n s ( 1 9 )

153 Clock (SCLK) fall time (90% of VCC to 10% of VCC)t SCLKF —1 52 8 n s ( 1 9 )

154 CS asserted to SCLK high (CS = 10% of VCC to SCLK = 10% of VCC)t LEAD 60 — — ns (3)

155 CS asserted to MISO valid (CS = 10% of VCC to MISO = 10/90% of VCC)t ACCESS ——6 0 n s ( 3 )

156 Data setup time (MOSI = 10/90% of VCC to SCLK = 10% of VCC)* t SETUP 20 — — ns (3)

157 MOSI Data hold time (SCLK = 90% of VCC to MOSI = 10/90% of VCC)* t HOLD_IN 10 — — ns (3)

158 MISO Data hold time (SCLK = 90% of VCC to MISO = 10/90% of VCC)* t HOLD_OUT 0— — n s ( 3 )

159 SCLK low to data valid (SCLK = 10% of VCC to MISO = 10/90% of VCC)* t VALID ——3 5 n s ( 3 )

160 SCLK low to CS high (SCLK = 10% of VCC to CS = 90% of VCC)* t LAG 60 — — ns (3)

161 CS high to MISO disable (CS = 90% of VCC to MISO = Hi Z) * t DISABLE ——6 0 n s ( 3 )

162 CS high to CS low (CS = 90% of VCC to CS = 90% of VCC)* t CSN 526 — — ns (3)

163 SCLK low to CS low (SCLK = 10% of VCC to CS = 90% of VCC)* t CLKCS 50 — — ns (3)

164 CS high to SCLK high (CS = 90% of VCC to SCLK = 90% of VCC)t CSCLK 50 — — ns (19)

12 NXP Semiconductors

3 Functional Description

3.1 Customer Accessible Data Array

to prevent unintended changes during normal operation. Portions of the array are reserved for factory-programmed trim values. The customer accessible data is shown in the table below. Table 3. Customer Accessible Data

3.1.1 Device Serial Number Registers

lot size and quantities, all possible lot numbers and serial numbers may not be assigned. performance, and are only used for traceability purposes.

3.1.2 Self Test Deflection Registers (STDEFL_X, STDEFL_Y)

maximum deflection specified in Section 2.4 (ΔSTMAX). specified in Section 2.4 (ΔSTACC). Reference Section 3.6 for more details on calculating the self test limits.

3.1.3 Factory Configuration Registers

configuration information that is programmed by NXP. Table 4. Self Test Deflection Registers Table 5. Factory Configuration Register

14 NXP Semiconductors

3.1.4 Part Number Register (PN)

identify the axis and range information. The contents of this register have no impact on device operation or performance.

3.1.5 Device Control Register (DEVCTL

ignored once the ENDINIT bit is set.

3.1.5.1 Reset Control (RES_1, RES_0)

A series of three consecutive register write operations to the reset control bits in the DEVCTL register will cause a device reset. register write operations must be consecutive SPI commands in the order shown or the device will not be reset. the response to a Register Read or Write will include the last successful written values for these bits. Table 6. Part Number Register Table 7. Device Control Register

3.1.5.2 Offset Cancellation Phase Control Bits (OCPHASE[1:0])

ENDINIT is ‘0’ if the OFFCFG_EN bit is set. ENDINIT is set will return the last successfully written values of OCPHASE[1:0].

3.1.5.3 Offset Cancellation Confi guration Enable Bit (OFFCFG_EN)

When ENDINIT is set, the OFFCFG_EN bit in a write command is ignored, and the offset cancellation phase is set to “Normal”. set will return the last successfully written value of OFFCFG_EN.

3.1.5.4 Reserved Bits (DEVCTL[2:0])

3.1.6 Device Configuration Register (DEVCFG)

check. Refer to Section 3.2.2 for details.

3.1.6.1 Offset Cancelled Data Selection Bits (OC )

The Offset Cancelled Data Selection Bit determines whether the SPI transmitted data is raw data or offset cancelled data.

3.1.6.2 Reserved Bit (Reserved)

0 Don’t Care Don’t Care Ignored Continues from the previously written phase (OCPHASE[1:0]) as

Table 8. Device Configuration Register

0 Offset Cancelled

1 Raw Data

16 NXP Semiconductors

3.1.6.3 End of Initialization Bit (ENDINIT)

(reference Section 3.2.2) is only enabled when the ENDINIT bit is set.

Offset Cancellation is forced to normal mode. OCPHASE[ 1:0], and OFFCFG_EN remain in their previously set states.
X-Axis Self Test is disabled. ST_X remains in its previously set states.
Y-Axis Self Test is disabled. ST_Y remains in its previously set states.

3.1.6.4 SD Bit

g level represented by a nominal value of 0.

3.1.6.5 OFMON Bit

= ‘1’) regardless of the value written to DEVCFG[3].

3.1.6.6 ARM Configuration Bits (A_CFG[2:0])

The ARM Configuration Bits (A_CFG[2:0]) select the mode of operation for the ARM_X/PCM_X, ARM_Y/PCM_Y pins.

1 Unsigned Data Output

0 Signed Data Output

1 Offset Monitor Circuit Enabled

0 Offset Monitor Circuit Disabled

Table 9. Arming Output Configuration

3.1.7 Axis Configuration Registers (DEVCFG_X, DEVCFG_Y)

CRC check. Refer to Section 3.2.2 for details.

3.1.7.1 Self Test Control (ST_X, ST_Y)

cleared following internal reset. that self test is deactivated. ST_Y bits and the response to a Register Read or Write will include the last successful written values for these bits.

3.1.7.2 Reserved Bits (Reserved)

for normal device operation and performance.

3.1.7.3 Low-Pass Filter Selection Bits (LPF_X[3:0], LPF_Y[3:0])

for details regarding filter configurations. Note:Filter characteristics do not include g-cell frequency response. Table 10. Axis Configuration Registers Table 11. Low-pass Filter Selection Bits

0110 R e s e r v e d R e s e r v e d

0111 R e s e r v e d R e s e r v e d

1110 R e s e r v e d R e s e r v e d

1111 R e s e r v e d R e s e r v e d

18 NXP Semiconductors

3.1.8 Arming Configuration Registers (ARMCFGX, ARMCFGY)

only relevant if the arming function is operating in moving average mode, or count mode. registers are included in the writable register CRC check. Refer to Section 3.2.2 for details.

3.1.9 Reserved Bits (Reserved)

for normal device operation and performance.

3.1.9.1 Arming Pulse Stretch (APS_X[1:0], APS_Y[1:0])

3.1.9.2 Arming Window Size (AWS_Xx[1:0], AWS_Yx[1:0])

The AWS_Xx[1:0] & AWS_Yx[1:0] bits have different functions depending on the state of the A_CFG bits in the DEVCFG register. axis. Refer to Section 3.8.10 for more details regarding the arming function. Table 12. Arming Configuration Register Table 13. Arming Pulse Stretch Definitions Table 14. X-Axis Positive Arming Window Size Definitions (Moving Average Mode) Table 15. X-Axis Negative Arming Window Size Definitions (Moving Average Mode)

3.1.10 Arming Threshold Registers ( ARMT_XP, ARMT_XN, ARMT_YP, ARMT_YN)

The arming threshold registers contain the X-axis and Y-axis positive and negative thresholds to be used by the arming function. Refer to Section 3.8.10 for more details regarding the arming function. Table 16. Y-Axis Positive Arming Window Size Definitions (Moving Average Mode) Table 17. Y-Axis Negative Arming Window Size Definitions (Moving Average Mode) Table 18. Arming Count Limit Definitions (Count Mode) Table 19. Arming Count Limit Definitions (Count Mode) Table 20. Arming Threshold Registers

20 NXP Semiconductors

of the value of the A_CFG bits in the DEVCFG register.

3.1.11 Device Status Register (DEVSTAT)

The device status register is a read-only register. A read of this register clears the status flags affected by transient conditions. Reference Section 4.5 for details on the response for each status condition.

3.1.11.1 Unused Bits (UNUSED)

The unused bits have no impact on operation or performance. When read these bits may be ‘1’ or ‘0’.

3.1.11.2 Internal Data Error Flag (IDE)

data stored in the fuse array, the fault will be re-asserted even after a device reset.

3.1.11.3 Device Initialization Flag (DEVINIT)

initialization. DEVINIT is cleared automatically. The device initialization flag is not affected by a read of the DEVSTAT register.

3.1.11.4 SPI MISO Data Mism atch Error Flag (MISOERR)

is cleared by a read of the DEVSTAT register.

3.1.11.5 Offset Monitor Error Flags (OFF_X, OFFSET_Y)

monitor error flags are cleared by a read of the DEVSTAT register.

3.1.11.6 Device Reset Flag (DEVRES)

3.1.12 Count Register (COUNT)

count every 128 μs and the counter rolls over every 32.768 ms. Table 21. Threshold Register Value Examples Table 22. Device Status Register

3.1.13 Offset Correction Value Registers (OFFCORR_X, OFFCORR_Y)

applied to the SPI output data. The values have a resolution of 1 LSB.

3.1.14 Reserved Registers (Reserved)

3.2 Customer Accessible Data Array CRC Verification

3.2.1 OTP Shadow Register Array CRC Verification

= X3 + X + 1, with a seed value = ‘111’. If a CRC error is detected in the OTP array, the IDE bit is set in the DEVSTAT register.

3.2.2 Writable Register CRC Verification

= ‘111’. If a CRC error is detected in the writable register array, the IDE bit is set in the DEVSTAT register. Table 23. Count Register Table 24. Offset Correction Value Register Table 25. Reserved Registers

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3.3 Voltage Regulators

Figure 1. The voltage regulator module includes voltage monitoring circuitry which indicates a device reset until the external is used by the ΣΔ converters. Figure 8. Power Supply Block Diagram Figure 9. Voltage Monitoring

3.3.1 C VREG Failure Detection

The digital supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREG capacitor becomes open, the digital supply voltage will oscillate and cause either an under voltage, or over voltage failure within one internal sample time. This failure will result in one of the following: 1. The DEVRES flag in the DEVSTAT register will be set. The device will respond to SPI acceleration requests as defined in Table 30. 2. The device will be held in RESET and be non-responsive to SPI requests.

3.3.2 C VREGA Failure Detection

The analog supply voltage regulator is designed to be unstable with low capacitance. If the connection to the VREGA capacitor becomes open, the analog supply voltage will oscillate and cause either an under voltage, or over voltage failure within one internal sample time. The DEVRES flag in the DEVSTAT register will be set. The device will respond to SPI acceleration requests as defined in Table 30.

3.3.3 V SS and VSSA Ground Loss Monitor

The device detects the loss of ground connection to either VSS or VSSA. A loss of ground connection to VSS will result in a VREG overvoltage failure. A loss of ground connection to VSSA will result in a VREG undervoltage failure. Both failures result in a device reset.

3.3.4 SPI Initiated Reset

In addition to voltage monitoring, a device reset can be initiated by a specific series of three write operations involving the RES_1

3.4 Internal Oscillator

The device includes a factory trimmed oscillator as specified in Section 2.7.

3.4.1 Oscillator Monitor

The COUNT register in the customer accessible array is a read-only register which provides the current value of a free-running 8-bit counter derived from the primary oscillator. A 10-bit pre-scaler divides the primary oscillator by 1024. Thus, the value in the COUNT register increases by one count every 128 μs, and the register rolls over every 32.768 ms. The SPI master can periodically read the COUNT register, and verify the difference between subsequent register reads against the system time base. 1. The SPI access rates and deviations must be taken into account for this oscillator verification method.

3.4.2 CRC Based Clock Monitor

The device includes unique DSP cores for the X-Axis and Y-Axis. Each DSP core uses multiple frequencies derived from the oscillator, ranging from the base oscillator frequency to the base oscillator frequency divided by 256. In order to guarantee that the clocks for the two DSP cores are synchronized, a clock CRC monitor is employed. The CRC monitor is updated every cycle of the base oscillator.

3.5 Transducer

The transducer is an overdamped mass-spring-damper system described by the following transfer function: where: ζ= Damping Ratio ωn= Natural Frequency = 2∗Π∗fn Reference Section 2.4 for transducer parameters. Hs() ωn s2 2 ξω n s⋅⋅ ⋅ ω n 2++

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3.6 Self Test Interface

test interface is shown in Figure 10. Figure 10. Self Test Interface

3.6.1 Raw Self Test Deflection Verification

The raw self test deflection can be directly verified against raw self test limits listed in Section 2.4.

3.6.2 Delta Self Test Deflection Verification

ΔSTACC The accuracy of the self test deflection relative to the stored deflection as specified in Section 2.4. ΔSTDEFLxCNTS The value stored in the STDEFL_X or STDEFL_Y register. ΔSTMIN The minimum self test deflection at 25C as specified in Section 2.4. ΔSTMAX The maximum self test deflection at 25C as specified in Section 2.4.

stream at a nominal frequency of 1 MHz. Figure 11. ΣΔ Converter Block Diagram

3.8 Digital Signal Processing Block

signal processing flow is shown in Figure 12. Figure 12. Signal Chain Diagram Table 26. Signal Chain Characteristics

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3.8.1 DSP Clock

each edge of the ΣΔ modulator clock to minimize noise during data conversion. Figure 13. Clock Generation

3.8.2 Decimation Sinc Filter

with a decimation factor of 8 or 16, depending on the Low-pass Filter selected. Figure 14. Sinc Filter Response, tS = 8 μs

3.8.3 Low-pass Filter

Data from the Sinc filter is processed by an infinite impulse response (IIR) low-pass filter. illustrated in the figures on the following pages.

8 MHz OSC

6 MHz Digital

Note: Low-pass Filter figures do not include g-cell frequency response. Table 27. Low-pass Filter Coefficients

Description

-3dB Frequency (±5%) Filter Order Sample Time (μs ±5%) Filter Coefficients Group Delay Self Test Step Response (ms) 8 0x08 50 Hz LPF 4 16 n 0 2.08729034056887e-10 d 0 1 26816/ fosc 14.00 n1 8.349134489240434e-10 d 1 -3.976249694824219 n2 1.25237777794924e-09 d 2 5.929003009577855 0 0x00 100 Hz LPF 4 8 n 3 8.349103355433541e-10 d 3 -3.929255528257727 7.00 n4 2.087307211059861e-10 d 4 0.9765022168437554 9 0x09 150 Hz LPF 4 16 n 0 1.639127731323242e-08 d 0 1 9024/ fosc 6.00 n1 6.556510925292969e-08 d 1 -3.928921222686768 n2 9.834768482194806e-08 d 2 5.789028996785419 1 0x01 300 Hz LPF 4 8 n 3 6.556510372902331e-08 d 3 -3.791257019240902 3.00 n4 1.639128257923422e-08 d 4 0.9311495074496179 10 0x0A 200 Hz LPF 4 16 n 0 5.124509334564209e-08 d 0 1 6784/ fosc 5.00 n1 2.049803733825684e-07 d 1 -3.905343055725098 n2 3.074705789151505e-07 d 2 5.72004239520561 2 0x02 400 Hz LPF 4 8 n 3 2.049803958150164e-07 d 3 -3.723967810019985 2.50 n4 5.124510693742625e-08 d 4 0.9092692903507213 13 0x0D 200 Hz LPF 3 16 n 0 2.720393240451813e-06 d 0 1 5632/ fosc 4.80 n1 8.161179721355438e-06 d 1 -2.931681632995605 n2 8.161180123840722e-06 d 2 2.865296718275204 5 0x05 400 Hz LPF 3 8 n 3 2.720393634345496e-06 d 3 -0.9335933215174919 2.40 n4 0d 4 0 11 0x0B 400 Hz LPF 4 16 n 0 7.822513580322266e-07 d 0 1 3392/ fosc 2.50 n1 3.129005432128906e-06 d 1 -3.811614513397217 n2 4.693508163398543e-06 d 2 5.450666051045118 3 0x03 800 Hz LPF 4 8 n 3 3.129005428784364e-06 d 3 -3.465805771100349 1.70 n4 7.822513604678875e-07 d 4 0.8267667478030489 12 0x0C 500 Hz LPF 4 16 n 0 1.865386962890625e-06 d 0 1 2688/ fosc 3.20 n1 7.4615478515625e-06 d 1 -3.765105724334717 n2 1.119232176112846e-05 d 2 5.319861050818872 4 0x04 1000 Hz LPF 4 8 n 3 7.4615478515625e-06 d 3 -3.34309015036024 1.60 n4 1.865386966264658e-06 d 4 0.7883646729233078

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Figure 15. Low-Pass Filter Characteristics: fC = 100 Hz, Poles = 4, tS = 8 μs

Figure 16. Low-Pass Filter Characteristics: fC = 300 Hz, Poles = 4, tS = 8 μs

30 NXP Semiconductors

Figure 17. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 4, tS = 8 μs

Figure 18. Low-Pass Filter Characteristics: fC = 400 Hz, Poles = 3, tS = 8 μs

32 NXP Semiconductors

Figure 19. Low-Pass Filter Characteristics: fC = 800 Hz, Poles = 4, tS = 8 μs

Figure 20. Low-Pass Filter Characteristics: fC = 1000 Hz, Poles = 4, tS = 8 μs

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3.8.4 Offset Cancellation

is shown in Figure 21, and response parameters are specified in Section 2.4 and in Table 28. Figure 21. Offset Cancellation Block Diagram correction value that will be applied to the acceleration data. During start up, three phases of moving average sizes are used to allow for faster convergence of misuse input signals. tST_OMB to allow the acceleration output to return to it’s nominal offset.

3.8.5 Offset Monitor

the offset monitor will also update at this rate. The time to indicate an Offset Over Range Error is dependent upon the input signal. Table 28. Offset Cancellation Timing Specifications

3.8.6 Signal Compensation

is necessary to achieve the specified parameters in Section 2.4.

3.8.7 Output Scaling

device. Figure 22 shows the method used to establish the output acceleration data word from the DSP output. Figure 22. 12-Bit Output Scaling Diagram

3.8.8 Data Interpolation

sample times. This operation is illustrated below. Figure 23. Data Interpolation Timing SPI acceleration request occurring in this window receives true sample.

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Figure 24. Data Interpolation Example

3.8.9 Acceleration Data Timing

Figure 25. Acceleration Data Timing

3.8.10 ARMING FUNCTION

by the state of the A_CFG bits in the DEVCFG register. condition will continue. However, new acceleration reads will not update the arming function regardless of the acceleration value.

3.8.10.1 Arming Function: Moving Average Mode

In moving average mode, the arming function runs a moving average on the offset cancelled output of each acceleration axis. ARMCFGX and ARMCFGY registers. Reference Section 3.1.8 for register details. Where n is the current sample. acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.6. the pulse stretch counter is set as described in Section 3.8.10.4. operation for different SPI conditions. Figure 26. Arming Function Block Diagram - Moving Average Mode moving average mode can be re-enabled.

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3.8.10.2 Arming Function: Count Mode

individually programmed for each axis via the ARMT_Xx and ARMT_Yx registers. Reference Section 3.1.10 for register details. threshold, the sample counter is reset to zero. acceleration data sample rate must meet the minimum time between requests (tACC_REQ_x) specified in Section 2.6. is asserted for the associated axis, and the pulse stretch counter is set as described in Section 3.8.10.4. operation for different SPI conditions. Figure 27. Arming Function Block Diagram - Count Mode Figure 28. X and Y Axis Arming Conditions, Moving Average and Count Mode

3.8.10.3 Arming Function: Unfiltered Mode

includes an acceleration response for that axis. includes an acceleration response for that axis. The pulse stretch function is not applied in Unfiltered mode. operation under the different SPI request conditions. Figure 29. Arming Function Block Diagram - Unfiltered Mode Figure 30. X and Y Axis Arming Conditions, Unfiltered Mode

40 NXP Semiconductors

3.8.10.4 Arming Pulse Stretch Function

A pulse stretch function can be applied to the arming outputs in moving average mode, or count mode. only if an arming condition does not exist for the associated axis after the most recent evaluated sample. stretch timer is zero, the arming output is de-asserted. The pulse stretch counter continuously decrements until it reaches zero. associated axis after the most recent evaluated sample. Reference Figure 28. not reset the pulse stretch counter regardless of the acceleration value.

3.8.10.5 Arming Pin Output Structure

Figure 31. Arming Function - Pin Output Structure

3.8.11 PCM Output Function

The PCM_X and PCM_Y pins are programmed as a digital outputs. Reference Section 2.3 for the pin electrical parameters.
The acceleration value output from the offset cancellation block is saturated to 9-bits and converted to an unsigned value. Note, the 9-bit unsigned acceleration value uses the full range of values (0 - 511).
The 9-bit acceleration value is input into a summer clocked at 8MHz.
The carry from the summer circuit is output to the PCM pin. A block diagram of the PCM output is shown in Figure 32. Exception conditions affect the PCM output as listed in Section 4.5.

Figure 32. PCM Output Function Block Diagram

9 Bit ADDER

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3.9 Serial Peripheral Interface

Section 4 for details regarding the SPI protocol and available commands. operates as a single device. The internal independent blocks are transparent. enables DO for a response during the next SPI message. Figure 33 shows an internal diagram of the SPI. Figure 33. SPI Diagram

3.10 Device Initialization

Figure 34. Initialization Process Notes:1) X-Axis and Y-Axis Self Test can be enabled and evaluated simultaneously to reduce test time. For failure mode coverage of the arming pins and of potential common axis failures, NXP recommends independent self test activation. 2) tSTRISE and tSTFALL are dependent on the selected LPF group delay.

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3.11 Overload Response

3.11.1 Overload Performance

the overload frequency and amplitude. The g-cell is overdamped, providing the optimal design for overload performance.

g-cell damping
N o n - l i n e a r i t y
Clipping limits
Symmetry Figure 35 shows the g-cell, ADC and output clipping of the device over frequency. The relevant parameters are specified in Section 2.1, and Section 2.7.

Figure 35. Output Clipping Vs. Frequency

3.11.2 Sigma Delta Over Range Response

after returning to the normal range of operation due to non-linear effects of the sensor.

4 SPI Communications

intermediate transfers involving other SPI devices may occur between phase one and phase two. Reference Figure 36. Figure 36. SPI Transfer Detail

46 NXP Semiconductors

4.1 SPI Command Format

Table 29. SPI Command Message Summary

0 AX A OC 0 0 0 0 0 0 0 0 1 SD ARM P Command Type Reference

0 X-Axis Acceleration Data

1 Y-Axis Acceleration Data

0 Register Operation

1 Acceleration Data Request

0 Offset Cancelled Data Enabled

1 Raw Acceleration Data Enabled

0 AX A OC 0 0 0 0 0 0 0 0 0 SD ARM P Accel Data

0010000000001001 X-Axis OC, Signed, Disabled/PCM

0010000000001010 X-Axis OC, Signed, ARM Enabled

0010000000001100 X-Axis OC, Unsigned, Disabled/PCM

0010000000001111 X-Axis OC, Unsigned, ARM Enabled

0011000000001000 X-Axis Raw, Signed, Disabled/PCM

0011000000001011 X-Axis Raw, Signed, ARM Enabled

0011000000001101 X-Axis Raw, Unsigned, Disabled/PCM

0011000000001110 X-Axis Raw, Unsigned, ARM Enabled

0110000000001000 Y-Axis OC, Signed, Disabled/PCM

0110000000001011 Y-Axis OC, Signed, ARM Enabled

0110000000001101 Y-Axis OC, Unsigned, Disabled/PCM

0110000000001110 Y-Axis OC, Unsigned, ARM Enabled

0111000000001001 Y-Axis Raw, Signed, Disabled/PCM

0111000000001010 Y-Axis Raw, Signed, ARM Enabled

0111000000001100 Y-Axis Raw, Unsigned, Disabled/PCM

0111000000001111 Y-Axis Raw, Unsigned, ARM Enabled

4.2 SPI Response Format

Table 30. SPI Response Message Summary

0 X-Axis Acceleration Response

1 Y-Axis Acceleration Response

10 S T A c t i v e

48 NXP Semiconductors

4.3 Acceleration Data Transfers

requested, as shown in Table 31. impacts the output data. The requested configuration is compared against the data programmed in the writable register block. Details are shown in Table 32. acceleration data request command must be an odd number.

The DEVINIT bit in the D EVSTAT register is not set
The DEVRES bit in the DEVST AT register is not set
The IDE bit in the DEVSTAT re gister is not set (Reference Section 4.5.5)
No SPI Error is detected (Reference Section 4.5.1)
No MISO Error is detected (Reference Section 4.5.2)
No Acceleration Data Request Mismatch failure is detected (Reference Section 4.5.3.1)
No Self Test Error is present (reference Section 4.5.5.2)
No Offset Monitor Error is present for the requested channel (reference Section 4.5.6) If the above conditions are met, the device responds with a “valid acceleration data request” response as shown in Table 30. Otherwise, the device responds as specified in Section 4.5.

Table 31. Acceleration Data Request Table 32. Acceleration Data Request Configuration Information

4.4 Register Access Operations

Two types of register access operations are supported; register write, and register read. Register access operations are initiated when the acceleration bit (A) of the command message is set to a logic ‘0’. The operation to be performed is indicated by the Access Selection bit (AX) of the command message. Register Access operations include a parity bit (P). Odd parity is employed. The number of logic ‘1’ bits in the Register Access operation must be an odd number.

4.4.1 Register Write Request

During a register write request, bits 12 through 8 contain a five-bit address, and bits 7 through 0 contain the data value to be written. Writable registers are defined in Table 3. The response to a register write operation is shown in Table 30. The response is transmitted on the next SPI message if and only if all of the following conditions are met:

No SPI Error is detected (Reference Section 4.5.1)
No MISO Error is detected (Reference Section 4.5.2)
The ENDINIT bit is cleared (Reference Section 3.1.6.3) – This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified)
No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, the device responds to the register write request as shown in Table 30. Otherwise, the device Responds as specified in Section 4.5. Register write operations do not occur internally until the transfer during which they are requested has been completed. In the event that a SPI Error is detected during a register write transfer, the write operation is not completed.

4.4.2 Register Read Request

During a register read request, bits 12 through 8 contain the five-bit address for the register to be read. Bits 7 through 0 must be logic ‘0’. Readable registers are defined in Table 3. The response to a register read operation is shown in Table 30. The response is transmitted on the next SPI message if and only if all of the following conditions are met:

No SPI Error is detected (Reference Section 4.5.1)
No MISO Error is detected (Reference Section 4.5.2)
No Invalid Register Request is detected (Reference Section 4.5.3.2) If the above conditions are met, the device responds to the register read request as shown in Table 30. Otherwise, the device responds as specified in Section 4.5. Access Selection Bit (AX) Operation

0 Register Read

1 Register Write

50 NXP Semiconductors

4.5 Exception Handling

exceptions exist, the exception response is determined by the priority listed in Table 33.

4.5.1 SPI Error

SCLK is high when CS is asserted
The number of SCLK rising edges detected while CS is asserted is not equal to 16
SCLK is high when CS is negated
Command message parity error (MOSI)
Bit 15 of Acceleration Data Request is not equal to ‘0’
Bits 4 through 11 of an Acceleration Request are not equal to ‘0’
Bits 3 of an Acceleration Request is not equal to ‘1’
Bits 0 through 7 of a Register Read Request are not equal to ‘0’ The device responds to a SPI error with a “SPI Error” response as shown in Table 30. This applies to both acceleration data request SPI errors, and Register Access SPI errors. The arming function will not be updated if a SPI Error is detected. The PCM output is not affected by a SPI Error.

Table 33. SPI Error Response Priority

1 SPI Error Error Response No Update No Effect

2 SPI MISO Error Error Response No Update No Effect

3 Invalid Request Error Response No Update No Effect

4 DEVINIT Bit Set Error Response No Update Disabled

5 DEVRES Error Error Response No Update Disabled

6 CRC Error Error Response No Update No Effect

7 Self Test Error Error Response No Update No Effect

8 Offset Monitor Error Error Response No Update No Effect

4.5.2 SPI Data Output Verification Error

Fault is detected and the MISOERR flag in the DEVSTAT register is set. affected by the MISO mismatch failure. the register read request is for the DEVSTAT register, the DEVSTAT register will not be cleared. DEVSTAT register is completed. Figure 37. SPI Data Output Verification

4.5.3 Invalid Requests

4.5.3.1 Acceleration Data Request Mismatch Failure

is not affected by the “Acceleration Data Request Mismatch” error. Register operations will be executed as specified in Section 4.4.

4.5.3.2 Invalid Register Request

An attempt is made to write to an un-writable register (Writable registers are defined in Section 3.1, Table 3). Attempts to write to registers $09, $18, $19, $1A and $1B will result in an error.
An attempt is made to write to a register while the ENDINIT bit in the DEVCFG register is set – This applies to all registers with the exception of the DEVCTL register (Only Bits 6 and 7 can be modified)
An attempt is made to read an un-readable register (Readable registers are defined in Section 3.1, Table 3). Attempts to read registers $09, $18, $19, $1A and $1B will result in an error. The device responds to an Invalid Register Request” error with an “Invalid Register Request” response as shown in Table 30.

4.5.4 Device Reset Indications

the DEVINIT or DEVRES bit is set in the DEVSTAT register. The PCM output is disabled if the DEVINIT or DEVRES bit is set.

52 NXP Semiconductors

4.5.5 Internal Error

The following errors will result in an internal error, and set the IDE bit in the DEVSTAT register:

OTP CRC Failure
Writable Register CRC Failure
Self Test Error
Invalid internal logic states

4.5.5.1 CRC Error

If the IDE bit is set in the DEVSTAT register due to one or more of the following errors, the device will respond to acceleration data requests with an “Internal Error Present” response until the IDE bit is cleared in the DEVSTAT register.

An OTP Shadow Register CRC failure as described in Section 3.2
A Writable Register CRC failure as described in Section 3.2
A clock monitor CRC failure as described in Section 3.4.2 The arming function will not be updated on Acceleration Data Request commands if a CRC Error is detected. The PCM output is not affected by the CRC error. If the CRC error is in the writable register array, and the ENDINIT bit in the DEVCFG register has been set, the error can only be cleared by a device reset. The IDE bit will not be cleared on a read of the DEVSTAT register. If the CRC error is in the OTP shadow register array, the error cannot be cleared. Register operations will be executed as specified in Section 4.4.

4.5.5.2 Self Test Error

If the IDE bit is set in the DEVSTAT register due to a Self Test activation failure, the device will respond to acceleration data requests with a “Self Test Error” response until the IDE bit is cleared in the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands if a Self Test Error is detected. The PCM output is not affected by the Self Test Error. The IDE bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs, even if the internal failure is removed. If the internal error is still present when the DEVSTAT register is read, the IDE bit will remain set. Register operations will be executed as specified in Section 4.4.

4.5.6 Offset Monitor Error

If an offset monitor error is present as described in Section 3.8.5, the OFFSET_X or OFFSET_Y bit in the DEVSTAT register will be set. The device will respond to an acceleration request for the corresponding axis with an “Internal Error Present” response until the OFFSET_X or OFFSET_Y bit is cleared in the DEVSTAT register. The arming function will not be updated. Once the error condition is removed, the OFFSET_X or OFFSET_Y bit in the DEVSTAT register will remain set until a read of the DEVSTAT register occurs. The PCM output is not affected by the offset monitor over range condition. Register operations will be executed as specified in Section 4.4.

4.6 Initialization SPI Response

The first data transmitted by the device following reset is the SPI Error response shown in Table 30. This ensures that an unexpected reset will always be detectable. The device will respond to all acceleration data requests with the “Invalid Acceleration Data Request” response until the DEVRES bit in the DEVSTAT register is cleared via a read of the DEVSTAT register. The arming function will not be updated on Acceleration Data Request commands until the DEVRES bit in the DEVSTAT register is cleared.

4.7 Acceleration Data Representation

some nominal acceleration values are shown in the following table. Table 34. Nominal Acceleration Data Values

54 NXP Semiconductors

parameters are specified in Section 2.4. Figure 38. Acceleration Data Output Vs. Acceleration Input

5 Package

5.1 Case Outline Drawing

Reference NXP case outline document 98ASA00690D.

5.2 Recommended Footprint

6 Revision History

Table 35. Revision History 9.0 01/2017 • Deleted part numbers MMA6519KGTW, MMA6525KGTW, and MMA6527KGTW. Updated part marking diagram to reflect deletions.

Information in this document is provided solely to enable system and software implementers to use NXP products. There are no expressed or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. NXP reserves the right to make changes without further notice to any products herein. NXP makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does NXP assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation, consequential or incidental damages. "Typical" parameters that may be provided in NXP data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. All operating parameters, including "typicals," must be validated for each customer application by the customer's technical experts. NXP does not convey any license under its patent rights nor the rights of others. NXP sells products pursuant to standard terms and conditions of sale, which can be found at the following address: http://www.nxp.com/terms-of-use.html. How to Reach Us: Home Page: NXP.com Web Support: http://www.nxp.com/support NXP , the NXP logo, Freescale, the Freescale logo, SafeAssure, and the SafeAssure logo, are trademarks of NXP B.V. All other product or service names are the property of their respective owners. All rights reserved. © 2017 NXP B.V. Document Number: MMA65xx Rev. 9.0

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NXP Semiconductors MMA65XX overview.

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Summary

Dual-Axis SPI Inertial Sensor Rev. 3, 03/2012

Description

Dual-Axis SPI Inertial Sensor Rev. 3, 03/2012

Source title MMA65XX Datasheet(PDF) - NXP Semiconductors

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