88W8987-A2-NYEE/AK

88W8987-SDS NXP

Document overview

• Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
• PDF pages: 88

Technical content

Datasheet sections

• 1 Product overview
• 1.1 Applications
• 1.2 Wi-Fi key features
• 1.3 Bluetooth key features
• 1.4 Host interfaces
• 1.5 Operating characteristics
• 1.6 General features
• 1.7 Internal block diagram
• 2 Ordering information
• 3 Wi-Fi subsystem
• 3.2 Wi-Fi MAC
• 3.3 Wi-Fi baseband
• 3.4 Wi-Fi radio
• 3.5 Wi-Fi encryption
• 3.6 Wi-Fi host interfaces
• 4 Bluetooth subsystem
• 4.2 Bluetooth Low Energy (LE)
• 4.3 Bluetooth host interfaces
• 4.4 Coexistence
• 4.5 PCM interface
• 5 Pin information
• 5.1 Signal diagrams
• 5.1.1 Signal diagram for QFN package option
• 5.1.2 Signal diagram for eWLP package option
• 5.2 Pin types
• 5.3 Pin assignment—68-pin QFN
• 5.3.1 Pin list by number
• 5.4 Pad locations—83-bump eWLP
• 5.5 Pin description
• 5.5.1 Pin states
• 5.5.2 General purpose I/O (GPIO)
• 5.5.3 Wi-Fi/Bluetooth radio interface
• 5.5.4 Wi-Fi RF front-end control interface
• 5.5.5 SDIO host interface
• 5.5.6 UART host interface
• 5.5.7 Audio interface
• 5.5.8 Configuration interface
• 5.5.9 Clock interface
• 5.5.10 Power down (PDn) pin
• 5.5.11 Power supply and ground
• 5.6 Configuration pins
• 6 Power information
• 6.1 Power-up sequence
• 6.2 Power-down sequence
• 6.3 Reset
• 6.3.1 Lowest power state
• 7 Absolute maximum ratings
• 8 Recommended operating conditions
• 9 Electrical specifications
• 9.1 GPIO/LED interface specifications
• 9.1.1 VIO DC characteristics
• 9.1.2 LED mode
• 9.2 RF front-end control interface specifications
• 9.2.1 VIO_RF DC characteristics
• 9.3 Wi-Fi radio specifications
• 9.3.1 Wi-Fi radio performance measurement
• 9.3.6 Local oscillator
• 9.4 Bluetooth radio specifications
• 9.4.1 Bluetooth and Bluetooth LE receiver
• 9.4.2 Bluetooth and Bluetooth LE transmitter
• 9.5 Current consumption
• 9.6 SDIO host interface specifications
• 9.6.1 VIO_SD DC characteristics
• 9.6.2 Default speed, high-speed modes
• 9.6.3 SDR12, SDR25, SDR50 modes (up to
• 9.6.6 SDIO internal pull-up/pull-down
• 9.7 High-speed UART specifications
• 9.8 Audio interface specifications
• 9.8.1 PCM interface specifications
• 9.9 Reference clock specifications
• 9.9.1 External crystal oscillator specifications
• 9.9.2 External crystal specifications
• 9.9.3 External sleep clock specifications
• 9.10 Power-down (PDn) pin specifications
• 9.10.1 PDn asserted low—All power supplies good
• 9.10.2 PDn asserted Low—One or more power
• 9.11 Configuration pin specifications
• 9.12 JTAG interface specifications
• 10 Package information
• 10.1 Package thermal conditions
• 10.2 Package mechanical drawing
• 10.3 Package marking
• 11 Acronyms and abbreviations
• 12 Revision history
• 13 Legal information

88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution Rev. 2 — 21 May 2021 Product short data sheet

1 Product overview

The 88W8987 is a highly integrated Wi-Fi (2.4/5 GHz) and Bluetooth single-chip solution, specifically designed to support the speed, reliability, and quality requirements of next generation Very High Throughput (VHT) products. The System-on-Chip (SoC) provides both simultaneous and independent operation of the following:

• IEEE 802.11ac (Wave 2), 1x1 with data rates up to MCS9 (433 Mbit/s)
• Bluetooth 5.2 (includes Bluetooth Low Energy (LE)) The SoC also provides:
• Bluetooth Classic and Bluetooth LE dual (Smart Ready) operation
• Wi-Fi indoor location positioning (802.11mc) For security, the device supports high performance 802.11i security standards through implementation of the Advanced Encryption Standard (AES)/Counter Mode CBC- MAC Protocol (CCMP), AES/Galois/Counter Mode Protocol (GCMP), Wired Equivalent Privacy (WEP) with Temporal Key Integrity Protocol (TKIP), AES/Cipher-Based Message Authentication Code (CMAC), and WLAN Authentication and Privacy Infrastructure (WAPI) security mechanisms. For video, voice, and multimedia applications, 802.11e Quality of Service (QoS) is supported. The device also supports 802.11h Dynamic Frequency Selection (DFS) for detecting radar pulses when operating in the 5 GHz range. Host interfaces include SDIO 3.0 and high-speed UART interfaces for connecting Wi-Fi and Bluetooth technologies to the host processor. The device is designed with two front-end configurations to accommodate Wi-Fi and Bluetooth on either separate or shared paths:
• 2-antenna configuration—1x1 Wi-Fi and Bluetooth on separate paths (QFN)
• 1-antenna configuration—1x1 Wi-Fi and Bluetooth on shared paths (eWLP) The following figures show the application diagrams for each package option.

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.1 Applications

• Wi-Fi and Bluetooth enabled smart phones and tablets
• Personal computing systems including notebooks and ultrabooks
• Wireless home audio and video entertainment systems
• Mobile routers and Internet of Things (IoT) gateways

1.2 Wi-Fi key features

• Support 802.11ac/n/a/g/b
• Dual band: 2.4 GHz and 5 GHz
• Up to MCS9 data rates
• 20/40/80 MHz channel bandwidth
• Security: TKIP, AES, WAPI

1.3 Bluetooth key features

• Bluetooth 5.2 support
• PCM audio interface
• Security: AES

1.4 Host interfaces

Wi-Fi and Bluetooth host interface options Wi-Fi Bluetooth SDIO 3.0 UART SDIO 3.0 SDIO 3.0

1.5 Operating characteristics

• Supply voltage: 2.2V, 1.8V, and 1.1V
• Operating temperature – Extended: -30 to 85°C – Industrial: -40 to 85°C Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

1.6 General features

• Package options – 68-pin 8x8 mm QFN with wettable flanks – 83-bump 4.6x4.2 mm eWLP
• Power management – Low power dissipation – Optional lower power operation with external sleep clock – Sleep and standby modes for low-power operation
• Independent ARM-based Wi-Fi and Bluetooth CPUs
• Supports reference clock signal from external crystal or external crystal oscillator
• Memory – Internal SRAM – Boot ROM – One Time Programmable (OTP) memory to store the MAC address and calibration data
• Peripheral interfaces – GPIO interface (up to 21) Product short data sheet Rev. 2 — 21 May 2021

1.7 Internal block diagram

Figure 3. Internal block diagram—QFN package option Figure 4. Internal block diagram—eWLP package option

2 Ordering information

Figure 5. Part numbering scheme Table 1. Part order codes

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3 Wi-Fi subsystem

3.1 IEEE 802.11 standards

• 802.11 data rates of 1 and 2 Mbit/s
• 802.11b data rates of 5.5 and 11 Mbit/s
• 802.11a/g data rates 6, 9, 12, 18, 24, 36, 48, and 54 Mbit/s for multimedia content transmission
• 802.11g/b performance enhancements
• 802.11ac / 802.11n with maximum data rates up to 86.7 Mbit/s (20 MHz channel), 200 Mbit/s (40 MHz channel), 433 Mbit/s (80 MHz channel)
• 802.11d international roaming
• 802.11e quality of service
• 802.11h transmit power control
• 802.11h DFS radar pulse detection
• 802.11i enhanced security
• 802.11k radio resource measurement
• 802.11mc precise indoor location positioning
• 802.11n block acknowledgment extension
• 802.11r fast hand-off for AP roaming
• 802.11u Hotspot 2.0 (STA mode only)
• 802.11v TIM frame transmission/reception
• 802.11w protected management frames
• Fully supports clients (stations) implementing IEEE Power Save mode Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.2 Wi-Fi MAC

• Simultaneous peer-to-peer and Infrastructure Modes
• RTS/CTS for operation under DCF
• Hardware filtering of 32 multicast addresses and duplicate frame detection for up to 32 unicast addresses
• On-chip Tx and Rx FIFO for maximum throughput
• Open System and Shared Key Authentication services
• A-MPDU Rx (de-aggregation) and Tx (aggregation) (supports 802.11ac single-MPDU A-MPDU)
• 20/40/80 MHz coexistence
• Reduced Inter-Frame Spacing (RIFS) receive
• Management information base counters
• Radio resource measurement counters
• Quality of service queues
• Block acknowledgment extension
• Dynamic frequency selection
• Beamforming – 802.11ac Explicit Beamformee, supports immediate feedback generation using 802.11ac compressed steering matrix feedback – 802.11ac Multi-User Beamformee – 802.11n Explicit Beamformee, supports immediate feedback generation using uncompress and compress steering matrix or delayed feedback of all feedback types
• TIM frame transmission/reception
• Multiple-BSS/Station
• Transmit rate adaptation
• Transmit power control
• Long and short preamble generation on a frame-by-frame basis for 802.11b frames
• Mobile hotspot Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.3 Wi-Fi baseband

• 802.11ac (on-chip RF radio)
• Backward compatibility with legacy 802.11n/a/g/b technology
• Simultaneous Wi-Fi and Bluetooth receive in single-antenna mode (eWLP only)
• PHY data rates up to 433 Mbit/s
• 20 MHz bandwidth/channel, 40 MHz bandwidth/channel, upper/lower 20 MHz packets in 40 MHz channel, 20 MHz duplicate legacy packets in 40 MHz channel mode operation
• 80 MHz bandwidth/channel, 4 positions of 20 MHz packets in 80 MHz channel, upper/ lower 40 MHz packets in 80 MHz channel, 20 MHz quadruplicate legacy packets in

80 MHz channel mode operation

• Modulation and Coding Scheme (MCS) – 802.11ac—MCS 0~9 Nsts = 1 – 802.11n—MCS 0~7 and MCS 32 (duplicate 6 Mbit/s)
• Dynamic frequency selection (radar detection) – Enhanced radar detection for long and short pulse radar – Enhanced AGC scheme for DFS channel – Japan DFS requirements for W53 and W56 frequency bands
• Radio resource measurement
• Optional 802.11ac and 802.11n features: – 20/40/80 MHz coexistence with middle-packet detection (GI detection) for enhanced CCA – 1 spatial stream STBC reception – LDPC transmission and reception for both 802.11n and 802.11ac – 256 QAM (MCS 8, 9) modulation, optional support for 802.11ac MCS 9 in 20 MHz using LDPC – Short guard interval – RIFS on receive path for 802.11n packets – 802.11n greenfield Tx/Rx – Explicit beamformee support – 802.11ac multi-user beamformee – MU-PPDUs (receive)
• Wi-Fi indoor locationing (802.11mc)
• Power save features Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

3.4 Wi-Fi radio

• Integrated direct-conversion radio
• 20, 40, and 80 MHz channel bandwidths
• Shared Wi-Fi/Bluetooth receive input scheme for 2.4 GHz band (eWLP only) Wi-Fi Rx path
• Direct conversion architecture eliminates need for external SAW filter
• On-chip gain selectable LNA with optimized noise figure and power consumption
• High dynamic range AGC function in receive mode Wi-Fi Tx path
• Internal PA with power control
• Optimized Tx gain distribution for linearity and noise performance Wi-Fi local oscillator
• Fractional-N for multiple reference clock support
• Fine channel step

3.5 Wi-Fi encryption

• Temporal Key Integrity Protocol (TKIP) / Wired Equivalent Privacy (WEP)
• Advanced Encryption Standard (AES) / Counter-Mode/CBC-MAC Protocol (CCMP)
• Advanced Encryption Standard (AES) / Cipher-Based Message Authentication Code (CMAC)
• Advanced Encryption Standard (AES) / Galois/Counter Mode Protocol (GCMP)
• WLAN Authentication and Privacy Infrastructure (WAPI)

3.6 Wi-Fi host interfaces

• SDIO 3.0 device interface (4-bit SDIO and 1-bit SDIO) transfer modes at full clock range up to 208 MHz Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

4 Bluetooth subsystem

4.1 2.4 GHz Bluetooth Tx/Rx

• Bluetooth 5.2
• Bluetooth Class 2
• Bluetooth Class 1
• Single-ended, shared Tx/Rx path for Bluetooth (QFN package option)
• Simultaneous Wi-Fi and Bluetooth receive in single-antenna mode (eWLP package option)
• PCM interface for voice applications
• Baseband and radio BDR and EDR packet types—1 Mbit/s (GFSK), 2 Mbit/s ( /4- DQPSK), and 3 Mbit/s (8DPSK)
• Fully functional Bluetooth baseband—AFH, forward error correction, header error control, access code correlation, CRC, encryption bit stream generation, and whitening
• Adaptive Frequency Hopping (AFH) using Packet Error Rate (PER)
• Interlaced scan for faster connection setup
• Simultaneous active ACL connection support
• Automatic ACL packet type selection
• Full master and slave piconet support
• Scatternet support
• Standard SDIO and UART HCI transport layer
• HCI layer to integrate with profile stack
• SCO/eSCO links with hardware accelerated audio signal processing and hardware supported PPEC algorithm for speech quality improvement
• All standard SCO/eSCO voice coding
• All standard pairing, authentication, link key, and encryption operations
• Standard Bluetooth power saving mechanisms (sniff modes, and sniff sub-rating)
• Enhanced Power Control (EPC)
• Channel Quality Driven Data Rate (CQDDR)
• Wideband Speech (WBS) support (1 WBS link)
• Encryption (AES) support

4.2 Bluetooth Low Energy (LE)

• Broadcaster, Observer, Central, and Peripheral roles
• Supports link layer topology to be master and slave (connects up to 16 links)
• Wi-Fi/Bluetooth coexistence protocol support
• Shared RF with BDR/EDR
• Encryption (AES) support
• Intelligent Adaptive Frequency Hopping (AFH)
• Bluetooth LE Privacy 1.2
• Bluetooth LE Secure Connection
• Bluetooth LE Data Length Extension
• Bluetooth LE Advertising Extension
• 2 Mbit/s Bluetooth LE Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

4.3 Bluetooth host interfaces

• SDIO 3.0
• High-speed UART

4.4 Coexistence

• Internal coexistence arbitration for Wi-Fi/Bluetooth

4.5 PCM interface

• Master or slave mode
• PCM bit width size of 8 bits or 16 bits
• Up to 4 slots with configurable bit width and start positions
• PCM short frame and long frame1 synchronization
• Tri-state PCM interface capability 1 In PCM Master mode, PCM long frame synchronization is 1 clock wide. In PCM Slave mode, PCM Master’s long frame synchronization pattern is supported. Product short data sheet Rev. 2 — 21 May 2021

5 Pin information

5.1 Signal diagrams

5.1.1 Signal diagram for QFN package option

Figure 6 shows the signals for the QFN package of the device. Note: Signals may be muxed. See Section 5.5 "Pin description". Figure 6. Signal diagram—QFN

5.1.2 Signal diagram for eWLP package option

Figure 7 shows the signals for eWLP package option. Note: Signals may be muxed. See Section 5.5 "Pin description". Figure 7. Signal diagram—eWLP

5.2 Pin types

Table 2. Pin types

5.3 Pin assignment—68-pin QFN

Figure 8. Pin assignment—68-pin QFN package option[1]

5.3.1 Pin list by number

The following table shows the pin list sorted by pin number.

1 GPIO[8] VIO I/O

2 GPIO[9] VIO I/O

3 GPIO[10] VIO I/O

4 VIO -- Power

5 GPIO[11] VIO I/O

6 VCORE -- Power

7 GPIO[12] VIO I/O

8 GPIO[13] VIO I/O

9 GPIO[14] VIO I/O

10 GPIO[15] VIO I/O

11 GPIO[2] VIO I/O

12 GPIO[3] VIO I/O

13 PDn AVDD18 I

14 AVDD18 -- Power

15 VIO_RF -- Power

16 RF_CNTL0_N VIO_RF O

17 RF_CNTL1_P VIO_RF O

18 RF_CTLN3_P VIO_RF O

19 RF_CTLN2_N VIO_RF O

20 AVDD18 -- Power

21 AVDD18 -- Power

22 AVSS -- Ground

23 AVDD18 -- Power

24 BRF_ANT AVDD18 A, I/O

25 VCORE -- Power

26 AVSS -- Ground

27 AVSS -- Ground

28 RF_TR_2 AVDD18 A, I/O

29 AVDD18 -- Power

30 VPA -- Power

31 VPA -- Power

32 RF_TR_5 AVDD18 A, I/O

33 AVSS -- Ground

34 AVDD18 -- Power

Table 3. Pin list by number

35 AVSS -- Ground

36 AVSS -- Ground

37 AVDD18 -- Power

38 AVDD18 -- Power

39 AVDD18 -- Power

40 XTAL_IN AVDD18 I

41 XTAL_OUT AVDD18 O

42 AVDD18 -- Power

43 AVDD18 -- Power

44 DNC -- --

45 CONFIG_HOST[0] AVDD18 I

46 CONFIG_HOST[1] AVDD18 I

47 CONFIG_AUTO_REF_DET AVDD18 I

48 GPIO[0] VIO I/O

49 GPIO[4] VIO I/O

50 GPIO[5] VIO I/O

51 GPIO[6] VIO I/O

52 GPIO[7] VIO I/O

53 VIO -- Power

54 SLP_CLK_IN VIO I

55 GPIO[1] VIO I/O

56 GPIO[16] VIO I/O

57 GPIO[17] VIO I/O

58 GPIO[18] VIO I/O

59 GPIO[19] VIO I/O

60 GPIO[20] VIO I/O

61 VCORE -- Power

62 VIO_SD -- Power

63 SD_CLK VIO_SD I

64 SD_CMD VIO_SD I/O

65 SD_DAT[0] VIO_SD I/O

66 SD_DAT[1] VIO_SD I/O

67 SD_DAT[2] VIO_SD I/O

68 SD_DAT[3] VIO_SD I/O

Table 3. Pin list by number...continued

5.4 Pad locations—83-bump eWLP

Alphanumeric designations are approximations to the grid. Figure 9. Pad locations—83-bump eWLP (non-bump-side view, bumps down) Table 4 indicates the pad locations in 83-bump eWLP package.

Table 4. Pad locations—83-bump eWLP

Table 4. Pad locations—83-bump eWLP...continued

5.5 Pin description

5.5.1 Pin states

• No Pad Power State indicates the state when there is no power
• PwrDwn State denotes the power-down state in default configuration. Many pads have programmable power-down values, which can be set by firmware.
• Reset State is the state after the power-on-reset state and before the hardware state (HW State)
• HW State (hardware state) is the state after boot code finishes and before firmware download begins (firmware may change the pin state). HW State may differ based on the pin muxing/strap setting. For example, for UART_RTSn and UART_SOUT, the boot code will enable the UART interface when the device is in SDIO-UART mode, making the HW states output high and output low, respectively.
• PwrDwn Prog indicates if the power-down state can be programmed
• Internal PU/PD columns indicates the following: – Type of PU/PD (weak vs nominal) – The polarity (PU vs. PD) The internal pull-up or pull-down applies when the pin is in input mode
• PU denotes whether the pull-up can be programmed or not
• PD denotes whether the pull-down can be programmed or not
• Pull-up and pull-down are only effective when the pad is in input mode
• After firmware is downloaded, the pads (GPIO, RF control, and so on) are programmed in functional mode per the functionality of the pins

5.5.2 General purpose I/O (GPIO)

Pins may be Multi-Functional Pins (MFP). GPIO Mode: GPIO[20] (input/output). This pin is used as a configuration pin: CON[9] (input). See Section 5.6 "Configuration pins". Table 5. General purpose I/O (GPIO)[1] (MFP)

Pins may be Multi-Functional Pins (MFP). GPIO Mode: GPIO[15] (input/output). This pin can also be used as Bluetooth independent reset. This pin can also be used as Wi-Fi independent reset. This pin can also be used for host to 88W8987 Wi-Fi wake-up (out-of-band wake-up signal). This pin is used as a configuration pin: CON[8] (input). See Section 5.6 "Configuration pins". This pin is used as a configuration pin: CONFIG_XOSC_SEL (input). See Section 5.6 "Configuration pins". Table 5. General purpose I/O (GPIO)[1] (MFP)...continued

Pins may be Multi-Functional Pins (MFP).

• Output if master
• Input if slave GPIO[6] VIO tristate input input tristate yes nominal PU yes yes GPIO Mode: GPIO[6] (input/output) PCM Mode: PCM_CLK (input/output)
• Output if master
• Input if slave GPIO[5] VIO tristate input input tristate yes weak PU yes yes GPIO Mode: GPIO[5] (input/output) PCM Mode: PCM_DOUT (output) This pin is used as a configuration pin: CON[7] (input). See Section 5.6 "Configuration pins". GPIO[4] VIO tristate input input tristate yes nominal PU yes yes GPIO Mode: GPIO[4] (input/output) PCM Mode: PCM_DIN (input) GPIO[3] VIO tristate output output high[3] tristate yes weak PU yes yes GPIO Mode: GPIO[3] (input/output) LED Mode: LED_OUT_BT (output) GPIO[2] VIO tristate output output high[3] tristate yes weak PU yes yes GPIO Mode: GPIO[2] (input/output) LED Mode: LED_OUT_WLAN (output) GPIO[1] VIO tristate input input tristate yes weak PU yes yes GPIO Mode: GPIO[1] (input/output). This pin can also be used for 88W8987 Wi-Fi to host wake-up (out-of-band wake-up signal). GPIO[0] VIO tristate output output high output low yes nominal PU yes no GPIO Mode: GPIO[0] (input/output) Oscillator Enable Mode: XOSC_EN (output) (active high). See Section 5.5.9 "Clock interface".

[1] Not all GPIO pins can be used for Host-to-SoC wakeup signals. [2] Maximum input voltage is 0.4V when VIO has no power (or in uncertain situations). [3] The signal may toggle while boot code is executing. [4] When the device is in SDIO-SDIO mode. [5] When the device is in SDIO-UART mode.

5.5.3 Wi-Fi/Bluetooth radio interface

Table 6. Wi-Fi/Bluetooth radio interface - QFN package Table 7. Wi-Fi/Bluetooth radio interface - eWLP package option

5.5.4 Wi-Fi RF front-end control interface

This pin is used as a configuration pin: CON[6] (input). See Section 5.6 "Configuration pins". Table 8. Wi-Fi RF front-end control interface [1] Maximum input voltage is 0.4V when VIO_RF has no power (or in uncertain situations).

5.5.5 SDIO host interface

Table 9. SDIO host interface [1] Maximum input voltage is 0.4V when VIO_SD has no power (or in uncertain situations).

5.5.6 UART host interface

Pins may be Multi-Functional Pins (MFP). Table 10. UART host interface (MFP)

5.5.7 Audio interface

Pins may be Multi-Functional Pins (MFP).

• Output if master
• Input if slave PCM_SYNC I/O VIO PCM frame sync. GPIO[7] input/ouput
• Output if master
• Input if slave

Table 11. Audio interface pins (MFP)

5.5.8 Configuration interface

This pin is used as a configuration pin: CONFIG_HOST[0] (input). See Section 5.6 "Configuration pins". This pin is used as a configuration pin: CONFIG_HOST[1] (input). See Section 5.6 "Configuration pins". This pin is used as a configuration pin: CONFIG_AUTO_REF_DET (input). See Section 5.6 "Configuration pins". Table 12. Configuration interface

5.5.9 Clock interface

Pins may be Multi-Functional Pins (MFP). Reference clock signal frequency must be 26 MHz or 38.4 MHz from an external crystal or external crystal oscillator. external sleep clock is not used. See Section 9.9 "Reference clock specifications". Connect this pin to an external crystal when an external crystal is used. When an external crystal oscillator is used, connect this pin to ground with resistance less than 5 kΩ. Used for lower power operation in sleep mode.

• An external sleep clock of 32.768 kHz can be used for lowest current consumption in sleep mode.
• An external sleep clock is required if automatic reference clock frequency detection is used. See Section 5.6 "Configuration pins".
• If no external sleep clock is used, leave this pin floating (DNC). XOSC_EN VIO -- -- -- -- -- -- -- -- Oscillator Enable (output) (active high) XOSC_EN signal can be used ONLY when an external sleep clock is used. Used to enable an external oscillator. 0 = disable external oscillator 1 = enable external oscillator NOTE: Muxed with GPIO[0].

Table 13. Clock interface (MFP) [1] Maximum input voltage is 0.4V when VIO has no power (or in uncertain situations).

5.5.10 Power down (PDn) pin

• PDn can accept an input of 1.8V to 4.5V
• PDn may be driven by the host
• PDn must be high for normal operation No internal pull-up on this pin.

Table 14. Power down (PDn) pin

5.5.11 Power supply and ground

Do not connect these pins. Leave these pins floating. Table 15. Power supply and ground

5.6 Configuration pins

Table 16 shows the pins used as configuration inputs to set parameters following a reset. The definition of these pins changes immediately after reset to their usual function. external circuitry is required to set a configuration bit to 1. Table 16. Configuration pins

10 SDIO UART 1 (Wi-Fi)

11 SDIO SDIO 2 (Wi-Fi, Bluetooth)

Table 17. Host configuration options

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

6 Power information

Section 5.5.11 "Power supply and ground" shows the required voltage levels for each rail and for PDn input signal.

6.1 Power-up sequence

• VIO/VIO_RF must be good (90%) before or at the same time all other power supplies start ramping up.
• VIO/VIO_RF must be good (90%) before or at the same time PDn starts ramping up.
• VPA must be good (90%) before or at the same time AVDD18 starts ramping up.
• It is recommended to start ramping up AVDD18 ≤1 ms after VPA ramps up.
• AVDD18 must be good (90%) before or at the same time VCORE starts ramping up.
• Ramp-up time of VIO/VIO_RF must be <100 ms.
• Ramp-up time of VPA must be <100 ms.
• Ramp-up time of AVDD18 must be <100 ms.
• Ramp-up time of VCORE must be <5 ms.
• All supplies must be monotonic.
• If using an external crystal oscillator, the reference clock must be stable before PDn ramps up. Figure 10 shows the power-up sequence. Product short data sheet Rev. 2 — 21 May 2021

Figure 10. Power-up sequence

6.2 Power-down sequence

• To ramp down AVDD18 after VPA ramps down
• To discharge all of the power supplies to less than 0.2V to reduce leakage. PDn must be asserted when powering down the device. Figure 11 shows the power-down sequence. VPA (2.2V) AVDD18 (1.8V) Less than 0.2V Less than 0.2V

Figure 11. Power-down sequence

6.3 Reset

• Internal Power-On Reset (POR): POR is triggered when the device receives power and VCORE and AVDD18 supplies are good. See Section 6.1 "Power-up sequence".
• Software/Firmware reset: the software or firmware issues a reset.
• External PDn pin assertion: the device is reset when the PDn input pin is <0.2V and transitions from low to high. See Section 9.10 "Power-down (PDn) pin specifications" for the electrical specifications.

6.3.1 Lowest power state

Wi-Fi and Bluetooth are not in use. To put the device in the lowest power mode, assert PDn low to enter power-down mode. downloaded, the device must be kept in power-down mode to reduce leakage.

7 Absolute maximum ratings

conditions at or beyond these ratings is not guaranteed and can damage the device. Table 18. Absolute maximum ratings Table 19. Limiting values - QFN option [1] According to ANSI/ESDA/JEDEC JS-001. Table 20. Limiting values - eWLP option [1] According to ANSI/ESDA/JEDEC JS-001.

8 Recommended operating conditions

Table 21. Recommended operating conditions

9 Electrical specifications

9.1 GPIO/LED interface specifications

9.1.1 VIO DC characteristics

Table 22. DC electrical characteristics—1.8V operation (VIO) Table 23. DC electrical characteristics—3.3V operation (VIO)

9.1.2 LED mode

Table 24. LED mode data

9.2 RF front-end control interface specifications

9.2.1 VIO_RF DC characteristics

Table 25. DC electrical characteristics—1.8V operation (VIO_RF) Table 26. DC electrical characteristics—3.3V operation (VIO_RF)

9.3 Wi-Fi radio specifications

9.3.1 Wi-Fi radio performance measurement

Figure 12. RF performance measurement points

1 Mbit/s -- -99 -- dBm

2 Mbit/s -- -95 -- dBm

5.5 Mbit/s -- -93 -- dBm

11 Mbit/s -- -90 -- dBm

6 Mbit/s -- -89 -- dBm

9 Mbit/s -- -89 -- dBm

12 Mbit/s -- -88 -- dBm

18 Mbit/s -- -87 -- dBm

24 Mbit/s -- -85 -- dBm

36 Mbit/s -- -81 -- dBm

48 Mbit/s -- -77 -- dBm

54 Mbit/s -- -76[1] -- dBm

Table 27. 2.4 GHz Wi-Fi receiver performance

1 Mbit/s -- 54 -- dB

2 Mbit/s -- 49 -- dB

5.5 Mbit/s -- 47 -- dB

11 Mbit/s -- 45 -- dB

6 Mbit/s -- 37 -- dB

9 Mbit/s -- 35 -- dB

12 Mbit/s -- 39 -- dB

18 Mbit/s -- 36 -- dB

24 Mbit/s -- 33 -- dB

36 Mbit/s -- 27 -- dB

48 Mbit/s -- 27 -- dB

54 Mbit/s -- 24 -- dB

6 Mbit/s -- -92 -- dBm

9 Mbit/s -- -92 -- dBm

12 Mbit/s -- -91 -- dBm

18 Mbit/s -- -89 -- dBm

24 Mbit/s -- -86 -- dBm

36 Mbit/s -- -83 -- dBm

48 Mbit/s -- -78 -- dBm

54 Mbit/s -- -77 -- dBm

Table 28. 5 GHz Wi-Fi receiver performance

Table 28. 5 GHz Wi-Fi receiver performance...continued

6 Mbit/s -- 34 -- dB

9 Mbit/s -- 32 -- dB

12 Mbit/s -- 33 -- dB

18 Mbit/s -- 32 -- dB

24 Mbit/s -- 29 -- dB

36 Mbit/s -- 24 -- dB

48 Mbit/s -- 24 -- dB

54 Mbit/s -- 17 -- dB

20 MHz and bandwidth 40 MHz

Table 29. 2.4 GHz Wi-Fi transmitter performance

Table 30. 5 GHz Wi-Fi transmitter performance

9.3.6 Local oscillator

Table 31. Local oscillator

9.4 Bluetooth radio specifications

The Bluetooth radio interface pin is powered by AVDD18 voltage supply.

9.4.1 Bluetooth and Bluetooth LE receiver performance

Table 32. Bluetooth and Bluetooth LE receiver performance

Table 32. Bluetooth and Bluetooth LE receiver performance...continued

9.4.2 Bluetooth and Bluetooth LE transmitter performance

except at 2x Bluetooth channel frequency. Measured at pin without external filter. Table 33. Bluetooth and Bluetooth LE transmitter

Table 33. Bluetooth and Bluetooth LE transmitter...continued

9.5 Current consumption

frequency and typical value. Data is collected with SDIO-SDIO interface configuration. Table 34. Current consumption

2.4 GHz Wi-Fi receive mode[3]

5 GHz Wi-Fi 5 receive mode[3]

2.4 GHz Wi-Fi transmit mode[3]

5 GHz Wi-Fi transmit mode[3]

Table 34. Current consumption...continued

9.6 SDIO host interface specifications

The SDIO host interface pins are powered by VIO_SD voltage supply. The SDIO electrical specifications are identical for the 4-bit SDIO and 1-bit SDIO modes.

9.6.1 VIO_SD DC characteristics

Table 35. DC electrical characteristics—1.8V operation (VIO_SD)

9.6.2 Default speed, high-speed modes

Figure 13. SDIO protocol timing diagram—Default speed mode Figure 14. SDIO protocol timing diagram—High-speed mode

Table 36. SDIO timing data—Default Speed, High-Speed Modes

Figure 15. SDIO protocol timing diagram—SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)

100 MHz

Table 37. SDIO timing data——SDR12, SDR25, SDR50 Modes (up to 100 MHz) (1.8V)

Figure 16. SDIO protocol timing diagram—SDR104 mode (208 MHz)

208 MHz

Table 38. SDIO timing data—SDR104 mode (208 MHz)

Figure 17. SDIO CMD timing diagram—DDR50 mode (50 MHz) Figure 18. SDIO DAT[3:0] timing diagram—DDR50 mode[1] (50 MHz) [1] In DDR50 mode, DAT[3:0] lines are sampled on both edges of the clock (not applicable for CMD line).

50 MHz (max) between

50 MHz

Table 39. SDIO timing data—DDR50 mode (50 MHz)

Table 39. SDIO timing data—DDR50 mode (50 MHz)...continued

9.6.6 SDIO internal pull-up/pull-down specifications

Table 40. SDIO internal pull-up/pull-down specifications

9.7 High-speed UART specifications

The UART Tx and Rx pins are powered by VIO voltage supply. See Section 9.1.1 "VIO DC characteristics" for DC specifications. Figure 19. UART timing diagram Table 41. UART timing data[1] [1] The acceptable deviation from the UART Rx target baud rate is ±3%.

9.8 Audio interface specifications

9.8.1 PCM interface specifications

characteristics" for specifications.

9.9 Reference clock specifications

9.9.1 External crystal oscillator specifications

The reference clock from the external crystal oscillator requires a CMOS input signal. the 26 MHz reference clock can still be used. Table 44. Clock DC specifications[1] [1] The AC-coupling capacitor is integrated into the SoC. Table 45. 26 MHz clock timing Table 46. 38.4 MHz clock timing

Table 47. Phase Noise—2.4 GHz operation Table 48. Phase Noise—5 GHz operation

9.9.2 External crystal specifications

the 26 MHz reference clock can still be used.

38.4 MHz -- -- 60 ΩSeries resistance (ESR)

26 MHz -- -- 60 Ω

Table 49. External crystal specifications

9.9.3 External sleep clock specifications

• CMOS input clock signal type
• ±250 ppm (initial, aging, temperature) -- 32.768 -- kHz Phase noise requirement (@ 100 kHz) -- -125 -- dBc/Hz Cycle jitter -- 1.5 -- ns (RMS) Slew rate limit (10-90%) -- -- 100 ns Duty cycle tolerance 20 -- 80 %

Table 50. External sleep clock specifications[1] [1] Voltage input levels = 1.8V or 3.3V. See Section 8 "Recommended operating conditions".

9.10 Power-down (PDn) pin specifications

9.10.1 PDn asserted low—All power supplies good

(low) while all power supplies to the device are good. Figure 24. Power-down (PDn) pin timing—The power remains high at PDn assertion Table 51. Power-down (PDn) pin specifications—The power remains high at PDn assertion [1] Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

9.10.2 PDn asserted Low—One or more power supplies ramp down

(low) while 1 or more of the power supplies (including VCORE) ramps down. Figure 25. Power-down (PDn) pin timing—Power ramps down at PDn assertion

Table 52. Power-down (PDn) pin secifications—Power ramps down at PDn assertion [1] Minimum value guaranteed for a valid reset. Smaller values may put the device in an undefined state.

9.11 Configuration pin specifications

For a list of configuration pins, see Section 5.6 "Configuration pins". Table 53. Configuration pin specifications[1] [1] After approximately 1 ms, the configuration pins become functional pins.

9.12 JTAG interface specifications

The test interface pins are powered by VIO voltage supply. See Section 9.1.1 "VIO DC characteristics" for specifications. Figure 26. JTAG timing diagram Table 54. JTAG timing data[1] [1] Does not apply to JTAG enabled by the JTAG_TMS pin.

10.1 Package thermal conditions

Junction to ambient of package. Junction to top-center of package. Junction to case of the package. Junction to board of package. Table 55. Thermal conditions—QFN package

Junction to ambient of package. P = total power dissipation JEDEC 4 in. x 4.5 in. Junction to top-center of package. Table 56. Thermal conditions—eWLP package

10.2 Package mechanical drawing

Figure 27. 68-pin QFN mechanical drawing

Figure 28. 83-bump eWLP mechanical drawing

• Dimensions in mm. Also refer to Section 10.1.2 "83-bump eWLP thermal conditions" and Section 10.3.2 "83-bump eWLP package marking". Product short data sheet Rev. 2 — 21 May 2021

10.3 Package marking

Note: The above drawing is not drawn to scale. The location of markings is approximate. Figure 29. 68-pin QFN package marking and pin 1 location Note: The above drawing is not drawn to scale. The location of markings is approximate. Figure 30. eWLP package marking and pin 1 location

11 Acronyms and abbreviations

Table 57. Acronyms and abbreviations

Table 57. Acronyms and abbreviations...continued

Table 58. Revision history

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution

13 Legal information

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13.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. NXP — wordmark and logo are trademarks of NXP B.V. Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution Tables Tab. 6. Wi-Fi/Bluetooth radio interface - QFN Tab. 7. Wi-Fi/Bluetooth radio interface - eWLP Tab. 22. DC electrical characteristics—1.8V Tab. 23. DC electrical characteristics—3.3V Tab. 25. DC electrical characteristics—1.8V Tab. 26. DC electrical characteristics—3.3V Tab. 32. Bluetooth and Bluetooth LE receiver Tab. 35. DC electrical characteristics—1.8V Tab. 36. SDIO timing data—Default Speed, High- Tab. 37. SDIO timing data——SDR12, SDR25, Tab. 38. SDIO timing data—SDR104 mode (208 Tab. 40. SDIO internal pull-up/pull-down Tab. 42. PCM timing specification data—Master Tab. 43. PCM timing specification data—Slave Tab. 51. Power-down (PDn) pin specifications—The Tab. 52. Power-down (PDn) pin secifications— Figures Fig. 2. Application diagram—eWLP package Fig. 3. Internal block diagram—QFN package Fig. 4. Internal block diagram—eWLP package Fig. 8. Pin assignment—68-pin QFN package Fig. 9. Pad locations—83-bump eWLP (non- Fig. 13. SDIO protocol timing diagram—Default Fig. 14. SDIO protocol timing diagram—High-speed Fig. 15. SDIO protocol timing diagram—SDR12, SDR25, SDR50 Modes (up to 100 MHz) Fig. 16. SDIO protocol timing diagram—SDR104 Fig. 17. SDIO CMD timing diagram—DDR50 mode Fig. 18. SDIO DAT[3:0] timing diagram—DDR50 Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution Fig. 20. PCM timing specification diagram for data Fig. 21. PCM timing specification diagram for Fig. 22. PCM timing specification diagram for data Fig. 23. PCM timing specification diagram for Fig. 24. Power-down (PDn) pin timing—The power Fig. 25. Power-down (PDn) pin timing—Power Fig. 29. 68-pin QFN package marking and pin 1 Product short data sheet Rev. 2 — 21 May 2021

NXP Semiconductors 88W8987_SDS 2.4/5 GHz Dual-band 1x1 Wi-Fi 5 (802.11ac) and Bluetooth 5.2 Solution Please be aware that important notices concerning this document and the product(s) described herein, have been included in section 'Legal information'. © NXP B.V. 2021. All rights reserved. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp.com Date of release: 21 May 2021 Document identifier: 88W8987_SDS