M24512-DF

Datasheet - M24512-W M24512-R M24512-DF - 512-Kbit serial I²C bus EEPROM

Document overview

• Manufacturer or author: STMICROELECTRONICS
• PDF pages: 47

Technical content

Datasheet sections

• 1 Description
• 2 Signal description
• 2.1 Serial Clock (SCL)
• 2.2 Serial Data (SDA)
• 2.3 Chip Enable (E2, E1, E0)
• 2.4 Write Control (WC)
• 2.5 VSS (ground)
• 2.6 Supply voltage (VCC)
• 2.6.1 Operating supply voltage (VCC)
• 2.6.2 Power-up conditions
• 2.6.3 Device reset
• 2.6.4 Power-down conditions
• 3 Memory organization
• 4 Device operation
• 4.1 Start condition
• 4.2 Stop condition
• 4.3 Data input
• 4.4 Acknowledge bit (ACK)
• 4.5 Device addressing
• 5 Instructions
• 5.1 Write operations
• 5.1.1 Byte Write
• 5.1.2 Page Write
• 5.1.3 Write Identification Page (M24128-D only)
• 5.1.4 Lock Identification Page (M24128-D only)
• 5.1.5 ECC (Error Correction Code) and Write cycling
• 5.1.6 Minimizing Write delays by polling on ACK
• 5.2 Read operations
• 5.2.1 Random Address Read
• 5.2.2 Current Address Read

Features

• Compatible with following I 2C bus modes: – 1 MHz – 400 kHz – 100 kHz
• Memory array: – 512 Kbit (64 Kbyte) of EEPROM – Page size: 128 byte – Additional write lockable page (M24512-D order codes)
• Single supply voltage and high speed: – 1 MHz clock from 1.7 V to 5.5 V
• Write time: – Byte write within 5 ms – Page write within 5 ms
• Operating temperature range: – -40 °C up to +85 °C
• Random and sequential read modes
• Write protect of the whole memory array
• Enhanced ESD/latch-Up protection
• More than 4 million write cycles
• More than 200-years data retention
• Packages: – SO8 ECOPACK2 ® – TSSOP8 ECOPACK2 ® – UFDFPN8 ECOPACK2 ® – WLCSP ECOPACK2 ® – Unsawn wafer (each die is tested) Product status link M24512-W M24512-R M24512-DF 512-Kbit serial I²C bus EEPROM M24512-W M24512-R M24512-DF Datasheet DS6520 - Rev 31 - October 2020 For further information contact your local STMicroelectronics sales office.

1 Description

The M24512 is a 512-Kbit I2C-compatible EEPROM (electrically erasable programmable memory) organized as 64 K × 8 bits. The M24512-W can operate with a supply voltage from 2.5 V to 5.5 V, the M24512-R can operate with a supply devices operate with a clock frequency of 1 MHz (or less), over an ambient temperature range of –40 °C / +85 °C. The M24512-D offers an additional page, named the identification page (128 byte). The identification page can be used to store sensitive application parameters which can be (later) permanently locked in read-only mode. Figure 1. Logic diagram Table 1. Signal names Figure 2. 8-pin package connections, top view

Description

Figure 3. WLCSP connections Table 2. Signal vs. bump position

1 SDA - E2 - VSS

3 VCC - WC - E0

2 Signal description

2.1 Serial clock (SCL)

2.2 Serial data (SDA)

connected from serial data (SDA) to VCC (Figure 12 indicates how to calculate the value of the pull-up resistor).

2.3 Chip enable (E2, E1, E0)

b1) of the 7-bit device select code (see Table 3). These inputs must be tied to VCC or VSS, as shown in Figure 4. When not connected (left floating), these inputs are read as low (0). Figure 4. Chip enable inputs connection

2.4 Write control (WC)

enabled when write control (WC) is either driven low or left floating.

2.5 VSS (ground)

VSS is the reference for the VCC supply voltage.

2.6 Supply voltage (VCC)

2.6.1 Operating supply voltage (VCC)

Prior to selecting the memory and issuing instructions to it, a valid and stable VCC voltage within the specified [VCC(min), VCC(max)] range must be applied (see Operating conditions in Section 8 DC and AC parameters). In order to secure a stable DC supply voltage, it is recommended to decouple the VCC line with a suitable capacitor (usually of the order of 10 nF to 100 nF) close to the VCC/VSS package pins. This voltage must remain stable and valid until the end of the transmission of the instruction and, for a write instruction, until the completion of the internal write cycle (tW).

2.6.2 Power-up conditions

The VCC voltage has to rise continuously from 0 V up to the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters).

2.6.3 Device reset

In order to prevent inadvertent write operations during power-up, a power-on-reset (POR) circuit is included. At power-up, the device does not respond to any instruction until VCC has reached the internal reset threshold voltage. This threshold is lower than the minimum VCC operating voltage (see Operating conditions in Section 8 DC and AC parameters). When VCC passes over the POR threshold, the device is reset and enters the standby power mode; however, the device must not be accessed until VCC reaches a valid and stable DC voltage within the specified [VCC(min), VCC(max)] range (see Operating conditions in Section 8 DC and AC parameters). In a similar way, during power-down (continuous decrease in VCC), the device must not be accessed when VCC drops below VCC(min). When VCC drops below the power-on-reset threshold voltage, the device stops responding to any instruction sent to it.

2.6.4 Power-down conditions

During power-down (continuous decrease in VCC), the device must be in the standby power mode (mode reached after decoding a stop condition, assuming that there is no internal write cycle in progress). M24512-W M24512-R M24512-DF Supply voltage (VCC) DS6520 - Rev 31 page 5/47

3 Memory organization

The memory is organized as shown below. Figure 5. Block diagram

4 Device operation

Figure 6. I2C bus protocol

4.1 Start condition

Start is identified by a falling edge of serial data (SDA) while serial clock (SCL) is stable in the high state. A start condition must precede any data transfer instruction. The device continuously monitors (except during a write cycle) serial data (SDA) and serial clock (SCL) for a start condition.

4.2 Stop condition

Stop is identified by a rising edge of serial data (SDA) while serial clock (SCL) is stable and driven high. A stop condition terminates communication between the device and the bus master. A read instruction that is followed by NoAck can be followed by a stop condition to force the device into the standby mode. A stop condition at the end of a write instruction triggers the internal write cycle.

4.3 Data input

During data input, the device samples serial data (SDA) on the rising edge of serial clock (SCL). For correct device operation, serial data (SDA) must be stable during the rising edge of serial clock (SCL), and the serial data (SDA) signal must change only when serial clock (SCL) is driven low.

4.4 Acknowledge bit (ACK)

The acknowledge bit is used to indicate a successful byte transfer. The bus transmitter, whether it be bus master or slave device, releases serial data (SDA) after sending eight bits of data. During the 9th clock pulse period, the receiver pulls serial data (SDA) low to acknowledge the receipt of the eight data bits. M24512-W M24512-R M24512-DF Start condition DS6520 - Rev 31 page 8/47

4.5 Device addressing

condition. Following this, the bus master sends the device select code, shown in Table 3 (most significant bit first). Table 3. Device select code

1. The most significant bit, b7, is sent first.
2. E0, E1 and E2 are compared with the value read on input pins E0, E1 and E2.

value on the chip enable (E2, E1, E0) inputs. The 8th bit is the Read/Write bit (RW). This bit is set to 1 for read and 0 for write operations.

5 Instructions

5.1 Write operations

address byte with an acknowledge bit, and then waits for the data byte. Table 4. Most significant address byte Table 5. Least significant address byte other time slot does not trigger the internal write cycle. counter is automatically incremented to point to the next byte after the last modified byte. bytes are not acknowledged, as shown in Figure 8.

5.1.1 Byte write

terminates the transfer by generating a stop condition, as shown in Figure 7. Figure 7. Write mode sequences with WC = 0 (data write enabled)

5.1.2 Page write

written on the same page, from location 0. address counter is incremented. The transfer is terminated by the bus master generating a stop condition. Figure 8. Write mode sequences with WC = 1 (data write inhibited)

5.1.3 Write identification page (M2512-D only)

The identification page (128 byte) is an additional page which can be written and (later) permanently locked in read-only mode. It is written by issuing the write identification page instruction. This instruction uses the same protocol and format as page write (into memory array), except for the following differences:

• Device type identifier = 1011b
• MSB address bits A15/A7 are don't care except for address bit A10 which must be ‘0’. LSB address bits A6/A0 define the byte address inside the identification page. If the identification page is locked, the data bytes transferred during the write identification page instruction are not acknowledged (NoAck).

5.1.4 Lock identification page (M24512-D only)

The lock identification page instruction (Lock ID) permanently locks the identification page in read-only mode. The lock ID instruction is similar to byte write (into memory array) with the following specific conditions:

• Device type identifier = 1011b
• Address bit A10 must be ‘1’; all other address bits are don't care
• The data byte must be equal to the binary value xxxx xx1x, where x is don't care

5.1.5 ECC (error correction code) and write cycling

The error correction code (ECC) is an internal logic function which is transparent for the I2C communication protocol. The ECC logic is implemented on each group of four EEPROM bytes (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). Inside a group, if a single bit out of the four bytes happens to be erroneous during a read operation, the ECC detects this bit and replaces it with the correct value. The read reliability is therefore much improved. Even if the ECC function is performed on groups of four bytes, a single byte can be written/cycled independently. In this case, the ECC function also writes/cycles the three other bytes located in the same group (A group of four bytes is located at addresses [4*N, 4*N+1, 4*N+2, 4*N+3], where N is an integer). As a consequence, the maximum cycling budget is defined at group level and the cycling can be distributed over the 4 bytes of the group: the sum of the cycles seen by byte0, byte1, byte2 and byte3 of the same group must remain below the maximum value defined Table 12. Cycling performance by groups of four bytes. M24512-W M24512-R M24512-DF Write operations DS6520 - Rev 31 page 13/47

5.1.6 Minimizing write delays by polling on ACK

typical time is shorter. To make use of this, a polling sequence can be used by the bus master.

• Initial condition: a write cycle is in progress.
• Step 1: the bus master issues a Start condition followed by a device select code (the first byte of the new instruction).
• Step 2: if the device is busy with the internal write cycle, no Ack is returned and the bus master goes back to step 1. If the device has terminated the internal write cycle, it responds with an Ack, indicating that the device is ready to receive the second part of the instruction (the first byte of this instruction having been sent during Step 1).

Figure 9. Write cycle polling flowchart using ACK

1. The seven most significant bits of the device select code of a random read (bottom right box in the figure)

5.2 Read operations

Read operations are performed independently of the state of the write control (WC) signal. point to the next byte address. transfer and switches to its standby mode. Figure 10. Read mode sequences

5.2.1 Random address read

A dummy write is first performed to load the address into this address counter (as shown in Figure 10) but without sending a stop condition. Then, the bus master sends another start condition, and repeats the device select code, with the RW bit set to 1. The device acknowledges this, and outputs the contents of the addressed byte. The bus master must not acknowledge the byte, and terminates the transfer with a stop condition.

5.2.2 Current address read

For the current address read operation, following a start condition, the bus master only sends a device select code with the RW bit set to 1. The device acknowledges this, and outputs the byte addressed by the internal address counter. The counter is then incremented. The bus master terminates the transfer with a stop condition, as shown in Figure 10, without acknowledging the byte. Note that the address counter value is defined by instructions accessing either the memory or the identification page. When accessing the Identification page, the address counter value is loaded with the byte location in the identification page, therefore the next current address read in the memory uses this new address counter value. When accessing the memory, it is safer to always use the random address read instruction (this instruction loads the address counter with the byte location to read in the memory, see Section 5.2.1 Random address read) instead of the current address Read instruction.

5.2.3 Sequential read

This operation can be used after a current address read or a random address read. The bus master does acknowledge the data byte output, and sends additional clock pulses so that the device continues to output the next byte in sequence. To terminate the stream of bytes, the bus master must not acknowledge the last byte, and must generate a Stop condition, as shown in Figure 10. The output data comes from consecutive addresses, with the internal address counter automatically incremented after each byte output. After the last memory address, the address counter “rolls-over”, and the device continues to output data from memory address 00h.

5.3 Read identification page (M24512-D only)

The identification page (128 bytes) is an additional page which can be written and (later) permanently locked in Read-only mode. The identification page can be read by issuing an read identification page instruction. This instruction uses the same protocol and format as the random address read (from memory array) with device type identifier defined as 1011b. The MSB address bits A15/A7 are don't care, the LSB address bits A6/A0 define the byte address inside the identification page. The number of bytes to read in the ID page must not exceed the page boundary (e.g.: when reading the identification page from location 100d, the number of bytes should be less than or equal to 28, as the ID page boundary is 128 bytes). M24512-W M24512-R M24512-DF Read identification page (M24512-D only) DS6520 - Rev 31 page 16/47

5.4 Read the lock status (M24512-D only)

The locked/unlocked status of the identification page can be checked by transmitting a specific truncated command [identification page write instruction + one data byte] to the device. The device returns an acknowledge bit if the identification page is unlocked, otherwise a NoAck bit if the identification page is locked. Right after this, it is recommended to transmit to the device a start condition followed by a stop condition, so that:

• Start: the truncated command is not executed because the start condition resets the device internal logic,
• Stop: the device is then set back into standby mode by the stop condition. M24512-W M24512-R M24512-DF Read the lock status (M24512-D only) DS6520 - Rev 31 page 17/47

6 Initial delivery state

The device is delivered with all the memory array bits and Identification page bits set to 1 (each byte contains FFh). M24512-W M24512-R M24512-DF Initial delivery state DS6520 - Rev 31 page 18/47

7 Maximum rating

extended periods may affect device reliability. Table 6. Absolute maximum ratings

1. Compliant with JEDEC Std J-STD-020E (for small body, Sn-Pb or Pb-free assembly), the ST ECOPACK 7191395
2. Positive and negative pulses applied on different combinations of pin connections, according to AEC-Q100-002 (compliant

with ANSI/ESDA/JEDEC JS-001-2012 standard, C1=100 pF, R1=1500 Ω).

8 DC and AC parameters

Table 7. Operating conditions (voltage range W) Table 8. Operating conditions (voltage range R) Table 9. Operating conditions (voltage range F) Table 10. AC measurement conditions

Figure 11. AC measurement I/O waveform Table 11. Input parameters

1. Characterized only, not tested in production.
2. E2, E1, E0 input impedance when the memory is selected (after a start condition).

Table 12. Cycling performance by groups of four bytes

1. The write cycle endurance is defined by characterization and qualification. For devices embedding the ECC functionality ,
2. A Write cycle is executed when either a page write, a byte write, a write identification page or a lock identification page

Table 13. Memory cell data retention

1. The data retention behaviour is checked in production, while the data retention limit defined in this table is extracted from

characterization and qualification results.

Table 14. DC characteristics (M24512-W, device grade 6)

1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the

internal write cycle tW (tW is triggered by the correct decoding of a write instruction).

1. E i inputs should be tied to Vss (see Section 2.3 Chip enable (E2, E1, E0)).
2. Ei inputs should be tied to Vcc (see Section 2.3 Chip enable (E2, E1, E0)).

Table 15. DC characteristics (M24512-R device grade 6)

1. If the application uses the voltage range R device with 2.5 V < V cc < 5.5 V and -40 °C < TA < +85 °C, please refer to

Table 14 instead of this table.

1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the

internal write cycle tW (tW is triggered by the correct decoding of a write instruction).

1. Ei inputs should be tied to V SS (see Section 2.3 Chip enable (E2, E1, E0)).
2. Ei inputs should be tied to V CC (see Section 2.3 Chip enable (E2, E1, E0)

Table 16. DC characteristics (M24512-DF, device grade 6)

1. If the application uses the voltage range F device with 2.5 V < V CC < 5.5 V and -40 °C < TA < +85 °C, please refer to

Table 14 instead of this table.

1. Characterized value, not tested in production.
2. The device is not selected after power-up, after a read instruction (after the stop condition), or after the completion of the

internal write cycle tW (tW is triggered by the correct decoding of a write instruction).

1. Ei inputs should be tied to V SS (see Section 2.3 Chip enable (E2, E1, E0)).
2. Ei inputs should be tied to V CC (see Section 2.3 Chip enable (E2, E1, E0)).

Table 17. 400 kHz AC characteristics

1. Characterized only, not tested in production.
2. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification

that the input signal rise and fall times be more than 20 ns and less than 300 ns when fC < 400 kHz.

1. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of
2. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3VCC or 0.7VCC, assuming

that Rbus × Cbus time constant is within the values specified in Figure 12.

1. WC=0 set up time condition to enable the execution of a WRITE command.
2. WC=0 hold time condition to enable the execution of a WRITE command.

Table 18. 1 MHz AC characteristics

1. There is no min. or max. values for the input signal rise and fall times. It is however recommended by the I²C specification

that the input signal rise and fall times be less than 120 ns when fC < 1 MHz.

1. Characterized only, not tested in production.
2. To avoid spurious Start and Stop conditions, a minimum delay is placed between SCL=1 and the falling or rising edge of
3. t CLQV is the time (from the falling edge of SCL) required by the SDA bus line to reach either 0.3 VCC or 0.7 VCC, assuming

that the Rbus × Cbus time constant is within the values specified in Figure 13.

1. WC=0 set up time condition to enable the execution of a WRITE command.
2. WC=0 hold time condition to enable the execution of a WRITE command.

Figure 14. AC waveforms

9 Package information

In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. For die information concerning the M24512-W delivered in unsawn wafer, please contact your nearest ST Sales Office.

9.1 UFDFPN8 (DFN8) package information

UFDFPN8 is an 8-lead, 2 × 3 mm, 0.5 mm thickness ultra thin profile fine pitch dual flat package Figure 15. UFDFPN8 - Outline

1. Max. package war-page is 0.05 mm.
2. Exposed copper is not systematic and can appear partially or totally according to the cross section.
3. The central pad (the area E2 by D2 in the above illustration) must be either connected to V SS or left floating

(not connected) in the end application.

Package information

DS6520 - Rev 31 page 29/47

Table 19. UFDFPN8 - Mechanical data

1. Values in inches are converted from mm and rounded to 4 decimal digits.
2. Dimension b applies to plated terminal and is measured between 0.15 and 0.30 mm from the terminal tip.
3. Applied for exposed die paddle and terminals. Exclude embedding part of exposed die paddle from measuring.

Figure 16. UFDFPN8 - Recommended footprint

1. Dimensions are expressed in millimeters.

9.2 TSSOP8 package information

TSSOP8 is an 8 lead thin shrink small outline, 3 x 6.4 mm, 0.65 mm pitch, package. Figure 17. TSSOP8 – Outline Table 20. TSSOP8 – Mechanical data

1. Values in inches are converted from mm and rounded to four decimal digits.

Figure 18. TSSOP8 – Recommended footprint

1. Dimensions are expressed in millimeters.

9.3 SO8N package information

SO8N is an 8 lead, 4.9 x 6 mm, plastic small outline, 150 mils body width, package. Figure 19. SO8N – Outline Table 21. SO8N – Mechanical data

1. Values in inches are converted from mm and rounded to four decimal digits.

Figure 20. SO8N - Recommended footprint

1. Dimensions are expressed in millimeters.

9.4 WLCSP8 (CS) package information

Figure 21. WLCSP8 - Outline

1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010.

Table 22. WLCSP8 - Mechanical data

1. Values in inches are converted from mm and rounded to four decimal digits.

Figure 22. WLCSP8 - Recommended footprint

1. Dimensions are expressed in millimeters.

9.5 WLCSP8 (CU) package information

Figure 23. WLCSP8 - Outline

1. Dimension is measured at the maximum bump diameter parallel to primary datum Z.
2. Primary datum Z and seating plane are defined by the spherical crowns of the bump.
3. Bump position designation per JESD 95-1, SPP-010.

Table 23. WLCSP8 - Mechanical data

1. Values in inches are converted from mm and rounded to the 4rd decimal place

Figure 24. WLCSP8 - Recommended footprint

1. Dimensions are expressed in millimeters.

Table 24. Ordering information scheme

1. ECOPACK2 (RoHS compliant and free of brominated, chlorinated and antimony oxide flame retardants).
2. These process letters appear on the device package (marking) and on the shipment box. Contact your nearest ST Sales

Ordering information

DS6520 - Rev 31 page 39/47

Table 25. Ordering information scheme (unsawn wafer) DS6520 - Rev 31 page 40/47

Revision history

Table 26. Document revision history Updated Table 7, Table 13, Table 16 and Table 17. voltage range, temperature grade). – Deleted reference “M24512-DR” and inserted reference “M24512-DF”. – Updated data regarding package UFDFPN8. – Updated Section 1: Description. – Added Figure 4 and updated title of Figure 3. 13 and ICC value in Table 14. characteristics (voltage range F). 17: 1 MHz AC characteristics. 12-Apr-2012 24 Updated Section 1: Description. Updated Section 5.2.2: Current Address Read.

• Note on Figure 3
• Note 2 on Table 3 Updated:
• Note 1 on Table 12 and Table 13
• Table 18
• Figure 11
• Table 20
• Titles on Figure and Table 21
• Table 24
• Note 1 on Table 21 Added:
• Note 2 on Table 12
• Note 4 and 5 on Table 14
• Note 6, 7 and 8 on Table 15
• Note 6, 7 on Table 16
• Note 8 on Table 17
• Figure 20
• Reference to Engineering sample after Ordering information scheme 27-May-2015 28 Added:
• Unsawn wafer reference on cover page and Table 25: Ordering information scheme (unsawn wafer)
• Note 1 on Table 12
• Removed ordering type M24512-DRxxxx from the whole document (device replaced by either M24512-Rxxx or M24512-DFxxx) 22-Mar-2018 29 Added:
• WLCSP8 ultra thin package in cover page
• Section 9.5: WLCSP8 ultra thin package information
• Table 3: Device select code Updated:
• Figure 3: WLCSP connections
• Table 10: AC measurement conditions
• Table 24: Ordering information scheme 21-Sep-2018 30 Updated:
• Figure 19: WLCSP - 8 bumps, 1.271 x 1.937 mm, 0.5 mm pitch wafer level chip scale package outline
• Figure 21: WLCSP - 8 balls, 1.289x1.955 mm, 1 mm pitch, wafer level chip scale package outline 06-Oct-2020 31 Updated:
• Features
• Figure 5. Block diagram Added:
• Figure 16. UFDFPN8 - Recommended footprint
• Figure 18. TSSOP8 – Recommended footprint Removed note in:
• Table 6. Absolute maximum ratings, Table 7. Operating conditions (voltage range W), Table 8. Operating conditions (voltage range R), Table 9. Operating conditions (voltage range F),Table 12. Cycling performance by groups of four bytes, Table 13. Memory cell data retention, Table 14. DC characteristics (M24512-W, device grade 6), Table 15. DC characteristics (M24512-R device grade 6), Table 16. DC characteristics (M24512-DF, device grade 6),

M24512-W M24512-R M24512-DF

Contents

DS6520 - Rev 31 page 44/47