LH7A400

LH7A400 NXP

Document overview

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Technical content

Preliminary data sheet 32-Bit System-on-Chip

FEATURES

• 32-bit ARM9TDMI™ RISC Core – 16 kB Cache: 8 kB Instruction and 8 kB Data – MMU (Windows CE™ Enabled) – Up to 250 MHz; see Table 1 for options  80 kB On-Chip Static RAM  Programmable Interrupt Controller  External Bus Interface – Up to 125 MHz; see Table 1 for options – Asynchronous SRAM/ROM/Flash – Synchronous DRAM/Flash – PCMCIA – CompactFlash  Clock and Power Management – 32.768 kHz and 14. 7456 MHz Oscillators – Programmable PLL  Programmable LCD Controller – Up to 1,024 × 768 Resolution – Supports STN, Color STN, AD-TFT, HR-TFT, TFT – Up to 64 k-Colors and 15 Gray Shades  DMA (10 Channels) –A C 9 7 –M M C –U S B  USB Device Interface (USB 2.0, Full Speed)  Synchronous Serial Port (SSP) – Motorola SPI™ – Texas Instruments SSI – National MICROWIRE™  Three Programmable Timers  Three UARTs – Classic IrDA (115 kbit/s)  Smart Card Interface (ISO7816)  Two DC-to-DC Converters  MultiMediaCard™ Interface  AC97 Codec Interface  Smart Battery Monitor Interface  Real Time Clock (RTC)  Up to 60 General Purpose I/Os  Watchdog Timer  JTAG Debug Interface and Boundary Scan  Operating Voltage – 1.8 V Core – 3.3 V Input/Output  5 V Tolerant Digital Inputs (except oscillator pins) – Oscillator pins P15, P16, R13, and T13 are 1.8 V ± 10 %.  Operating Temperature: −40°C to +85°C  256-ball BGA or 256-ball LFBGA Package

DESCRIPTION

The LH7A400, powered by an ARM922T, is a com- plete System-on-Chip with a high level of integration to satisfy a wide range of requirements and expectations. This high degree of integration lowers overall system costs, reduces development cycle time and accelerates product introduction. Table 1. LH7A400 versions

245 MHz 125 MHz Run = 250 mA; Halt = 50 mA; Standby = 129 µA 0°C to +70°C/

195 MHz 100 MHz Run = 125 mA; Halt: 25 mA; Standby = 42 µA 0°C to +70°C/

Table 2. Ordering information

Figure 1. LH7A400 block diagram

Table 3. Functional Pin List

XTAL32IN leaving XTAL32OUT open. Table 3. Functional Pin List (Cont’d)

edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced. edge triggered and are internally debounced.

other control signals to the appropriate PC Card. other control signals to the appropriate PC Card.

1. Signals beginning with ‘n’ are Active LOW.
2. The SCLK pin can source up to 12 mA and si nk up to 20 mA. See ‘DC Characteristics’.
3. Schmitt trigger input; see ’D C Specifications’, page 31 for triggers points and hysteresis.
4. Input only for JTAG boundary scan mode.
5. Output only for JTAG boundary scan mode.
6. The internal pullup and pull-down resist ance on all digital I/O pins is 50 k
7. When used as SMBCLK, this pin must have a resistor.
8. The RESET STATE is defined as the state during power-on reset.
9. The STANDBY STATE is defined as the state w hen the device is in standby. During this state,

current state is preserved (No Change). In some case, function selection has an overall effect on the standby state. to ground with a 15 kΩ resistor. MEDCHG to specify the boot memory device size. The pins must be pulled HIGH with a 33 kΩ resistor. mode, leave open. For JTAG mode, tie to GND. and JTAG mode, leave open. See Table 4. Table 4. nTest Pin Function

1. The Intensity bit is identical ly generated for all three colors.

Table 5. LCD Data Multiplexing

Table 6. 256-Ball BGA Package

Table 7. 256-Ball LFBGA Package

current power saving mode selected. the only clock in the LH7A400 that runs permanently. is used in the Real Time Clock counter. 48 MHz for the USB peripheral. Figure 4. Application Diagram

operates in all three modes. after which software can then take appropriate actions. high-performance, high clock frequency system modules. buffers and bus holders, and simplifies bus arbitration. Figure 5. Clock and State Controller Block Diagram

14.7456 MHz

wide, high speed gateway to external memory devices. given to the Synchronous Memory Controller interface. the LCD bus is given priority. The LH7A400 system has a 32-bit-wide address bus. these eight banks are designed for PCMCIA systems. AHB and APB. The rest is unused. (nSCS0) is mapped into memory location zero. system for the two boot modes. set the interrupt vector table. the priority must be resolved in software. bits are cleared, therefore masking all interrupts. software after a power-on-reset. Table 8. Boot Modes

sion buffer in Synchronous Memory for large displays. and the embedded SRAM frame buffer. existing access has been completed. See Figure 7. frame data and to be contiguous with external SDRAM. Half-Word and Word accesses are permissible. external (off-chip) memory devices. controller supports only little-endian operation. fast-boot block flash memory. Figure 6. Memory Mapping for Each Boot Mode

1000.0000 ASYNCHRONOUS MEMORY (nCS1)

Figure 7. External Bus Interface Block Diagram

32-Bit System-on-Chip LH7A400 Preliminary data sheet Rev. 01 — 16 July 2007 25 NXP Semiconductors The Asynchronous Memory Controller has six main functions:  Memory bank select  Access sequencing  Wait states generation  Byte lane write control  External bus interface  CompactFlash or PCMCIA interfacing. Synchronous Memory Controller The Synchronous memory controller provides a high speed memory interface to a wide variety of Synchro- nous memory devices, including SDRAM, Synchro- nous Flash and Synchronous ROMs. The key features of the controller are:  LCD DMA port for high bandwidth  Up to four Synchronous Memory banks that can be independently set up  Special configuration bits for Synchronous ROM operation  Ability to program Synchr onous Flash devices using write and erase commands  On booting from Synchronous ROM, (and optionally with Synchronous Flash), a configuration sequence is performed before releasing the processor from reset  Data is transferred between the controller and the SDRAM in quad-word bursts. Longer transfers within the same page are concatenated, forming a seam- less burst  Programmable for 16- or 32-bit data bus size  Two reset domains are provided to enable SDRAM contents to be preserved over a ‘soft’ reset  Power saving Synchronous Memory SCKE and external clock modes provided. MultiMediaCard (MMC) The MMC adapter combines all of the requirements and functions of an MMC host. The adapter supports the full MMC bus protocol, defined by the MMC Defini- tion Group’s specification v.2.11. The controller can also implement the SPI interface to the cards. INTERFACE DESCRIPTION AND MMC OVERVIEW The MMC controller uses the three-wire serial data bus (clock, command, and data) to transfer data to and from the MMC card, and to configure and acquire status information from the card’s registers. MMC bus lines can be divided into three groups:  Power supply: VDD and VSS  Data Transfer: MMCCMD, MMCDATA  Clock: MMCLK. MULTIMEDIACARD ADAPTER The MultiMediaCard Adapter implements MultiMedia- Card specific functions, serves as the bus master for the MultiMediacard Bus and implements the standard inter- face to the MultiMediaCard Cards (card initialization, CRC generation and validation, command/response transactions, etc.). Smart Card Interface (SCI) The SCI (ISO7816) interfaces to an external Smart Card reader. The SCI can autonomously control data transfer to and from the smart card. Transmit and receive data FIFOs are provided to reduce the required interaction between the CPU core and the peripheral. SCI FEATURES  Supports asynchronous T0 and T1 transmission protocols  Supports clock rate conversion factor F = 372, with bit rate adjustment factors D = 1, 2, or 4 supported  Eight-character-deep buffered Tx and Rx paths  Direct interrupts for Tx and Rx FIFO level monitoring  Interrupt status register  Hardware-initiated card deactivation sequence on detection of card removal  Software-initiated card deactivation sequence on transaction complete  Limited support for synchronous Smart Cards via registered input/output. PROGRAMMABLE PARAMETERS  Smart Card clock frequency  Communication baud rate  Protocol convention  Card activation/deactivation time  Check for maximum time for first character of Answer to Reset - ATR reception  Check for maximum duration of ATR character stream  Check for maximum time of receipt of first character of data stream  Check for maximum time allowed between characters  Character guard time  Block guard time  Transmit/receive character retry.

LH7A400 32-Bit System-on-Chip 26 Rev. 01 — 16 July 2007 Preliminary data sheet NXP Semiconductors Direct Memory Access Controller (DMA) The DMA Controller interfaces streams from the fol- lowing three peripherals to the system memory:  USB (1 Tx and 1 Rx DMA Channel)  MMC (1 Tx and 1 Rx DMA Channel)  AC97 (3 Tx and 3 Rx DMA Channels). Each has its own bi-directional peripheral DMA bus capable of transferring data in both directions simulta- neously. All memory transfers take place via the main system AHB bus. DMA Specific features are:  Independent DMA channels for Tx and Rx  Two Buffer Descriptors per channel to avoid poten- tial data under/over-flows due to software introduced latency  No Buffer wrapping  Buffer size may be equal to, greater than, or less than the packet size. Tr ansfers can automatically switch between buffers.  Maskable interrupt generation  Internal arbitration between DMA Channels and external bus arbiter.  For DMA Data transfer sizes, byte, word and quad- word data transfers are supported. A set of control and status registers are available to the system processor for se tting up DMA operations and monitoring their status. A system interrupt is gen- erated when any or all of the DMA channels wish to inform the processor that a new buffer needs to be allo- cated. The DMA controller services three peripherals using ten DMA channels, each with its own peripheral DMA bus capable of transferring data in both directions simultaneously. The MMC and USB peripherals each use two DMA channels, one for transmit and one for receive. The AC97 peripheral uses six DMA channels (three trans- mit and three receive) to allow different sample fre- quency data queues to be handled with low software overheads. The DMA Controller does not support memory to memory transfers. USB Device The features of the USB are:  Fully compliant to USB 1.1 specification  Provides a high level interf ace that shields the firm- ware from USB protocol details  Compatible with both OpenHCI and Intel’s UHCI standards  Supports full-speed (12 Mbps) functions  Supports Suspend and Resume signalling. Color LCD Controller The LH7A400’s LCD Controller is programmable to support up to 1,024 × 768, 16-bit color LCD panels. It interfaces directly to ST N, color STN, TFT, AD-TFT, and HR-TFT panels. Unlike ot her LCD controllers, the LH7A400’s LCD Controller incorporates the timing con- version logic from TFT to HR- and AD-TFT, allowing a direct interface to these panels and minimizing external chip count. The Color LCD Controller features support for:  Up to 1,024 × 768 Resolution  16-bit Video Bus  STN, Color STN, AD-TFT, HR-TFT, TFT panels  Single and Dual Scan STN panels  Up to 15 Gray Shades  Up to 64,000 Colors AC97 Advanced Audio Codec Interface The AC97 Advanced Audi o Codec controller includes a 5-pin serial interface to an external audio codec. The AC97 LINK is a bi-directional, fixed rate, serial Pulse Code Modulation (PCM) digital stream, dividing each audio frame into 12 outgoing and 12 incoming data streams (slots), each with 20-bit sample resolution. The AC97 controller contains logic that controls the AC97 link to the Audio Codec and an interface to the AMBA APB. Its main features include:  Serial-to-parallel conversi on for data received from the external codec  Parallel-to-serial conversion for data transmitted to the external codec  Reception/Transmission of control and status infor- mation via the AMBA APB interface  Supports up to 4 different codec sampling rates at a time with its 4 transmit and 4 receive channels. The transmit and receive paths are buffered with internal FIFO memories, allowing data to be stored indepen- dently in both transmit and receive modes. The out- going data for the FIFOs can be written via either the APB interface or with DMA channels 1 - 3.

32-Bit System-on-Chip LH7A400 Preliminary data sheet Rev. 01 — 16 July 2007 27 NXP Semiconductors Audio Codec Interface (ACI) The ACI provides:  A digital serial interface to an off-chip 8-bit CODEC  All the necessary clocks and timing pulses to per- form serialization or de-serialization of the data stream to or from the CODEC device. The interface supports full duplex operation and the transmit and receive paths are buffered with internal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The ACI includes a programmable frequency divider that generates a common transmit and receive bit clock output from the on-chip ACI clock input (ACICLK). Transmit data values are output synchronous with the rising edge of the bit clock output. Receive data values are sampled on the falling edge of the bit clock output. The start of a data frame is indicated by a synchroniza- tion output signal that is synchronous with the bit clock. Synchronous Serial Port (SSP) The LH7A400 SSP is a master-only interface for synchronous serial communication with device periph- eral devices that has either Motorola SPI, National Semiconductor MICROWIRE or Texas Instruments Synchronous Serial Interfaces. The LH7A400 SSP performs serial-to-parallel con- version on data received from a peripheral device. The transmit and receive paths are buffered with internal FIFO memories allowing up to eight 16-bit values to be stored independently in both transmit and receive modes. Serial data is transmitted on SSPTXD and received on SSPRXD. The LH7A400 SSP includes a programmable bit rate clock divider and prescaler to generate the serial output clock SCLK from the input clock SSPCLK. Bit rates are supported to 2 MHz and beyond, subject to choice of frequency for SSPCLK; the maximum bit rate will usu- ally be determined by peripheral devices. UART/IrDA The LH7A400 contains three UARTs, UART1, UART2, and UART3. The UART performs:  Serial-to-Parallel conversion on data received from the peripheral device  Parallel-to-Serial conversion on data transmitted to the peripheral device. The transmit and receive paths are buffered with inter- nal FIFO memories allowing up to 16 bytes to be stored independently in both transmit and receive modes. The UART can generate:  Four individually maskab le interrupts from the receive, transmit and modem status logic blocks  A single combined interrupt so that the output is asserted if any of the individual interrupts are asserted and unmasked. If a framing, parity, or break error occurs during reception, the appropriate error bit is set, and is stored in the FIFO. If an overrun condition occurs, the overrun register bit is set immediately and the FIFO data is pre- vented from being overwritten. UART1 also supports IrDA 1.0 (15.2 kbit/s). The modem status input signals Clear to Send (CTS), Data Carrier Detect (DCD) and Data Set Ready (DSR) are supported on UART2 and UART3. Timers Two identical timers are integrated in the LH7A400. Each of these timers has an associated 16-bit read/write data register and a control register. Each timer is loaded with the value written to the data register immediately, this value will then be de cremented on the next active clock edge to arrive after the write. When the timer underflows, it will immediately assert its appropriate interrupt. The timers can be read at any time. The clock source and mode is selectable by writing to various bits in the system control register. Clock sources are 508 kHz and 2 kHz. Timer 3 (TC3) has the same basic operation, but is clocked from a single 7.3728 MHz source. It has the same register arrangement as Timer 1 and Timer 2, pro- viding a load, value, control and clear register. Once the timer has been enabled and is written to, unlike the Timer 1 and Timer 2, will decrement the timer on the next rising edge of the 7.3728 MHz clock after the data register has been updated. All the timers can operate in two modes, free running mode or pre-scale mode. FREE-RUNNING MODE In free-running mode, the timer will wrap around to 0xFFFF when it underflows and continue counting down. PRE-SCALE MODE In pre-scale (periodic) mode, the value written to each timer is automatically re-loaded when the timer underflows. This mode can be used to produce a pro- grammable frequency to drive an external buzzer or generate a periodic interrupt.

LH7A400 32-Bit System-on-Chip 28 Rev. 01 — 16 July 2007 Preliminary data sheet NXP Semiconductors Real Time Clock (RTC) The RTC can be used to provide a basic alarm func- tion or long time-base counter. This is achieved by gen- erating an interrupt signal after counting for a programmed number of cycles of a real-time clock input. Counting in one second intervals is achieved by use of a 1 Hz clock input to the RTC. Battery Monitor Interface (BMI) The LH7A400 BMI is a serial communication inter- face specified for two type s of Battery Monitors/Gas Gauges. The first type employs a single wire interface. The second interface employs a two-wire multi-master bus, the Smart Battery System Specification. If both interfaces are enabled at the same time, the Single Wire Interface will have priority. A brief overview of these two interface types are given here. SINGLE WIRE INTERFACE The Single Wire Interface performs:  Serial-to-parallel conversion on data received from the peripheral device  Parallel-to-serial conversion on data transmitted to the peripheral device  Data packet coding/decoding on data transfers (incorporating Start/Data/Stop data packets) The Single Wire interface uses a command-based protocol, in which the host initiates a data transfer by sending a WriteData/Command word to the Battery Monitor. This word will always contain the Command section, which tells the Single Wire Interface device the location for the current transaction. The most signifi- cant bit of the Command determines if the transaction is Read or Write. In the case of a Write transaction, then the word will also contain a WriteData section with the data to be written to the peripheral. SMART BATTERY INTERFACE The SMBus Interface performs:  Serial-to-Parallel conversion on data received from the peripheral device  Parallel-to-Serial conversion of data transmitted to the peripheral device. The Smart Battery Interface uses a two-wire multi- master bus (the SMBus), meaning that more than one device capable of controlling the bus can be connected to it. A master device initiates a bus transfer and provides the clock signals. A slave device can receive data pro- vided by the master or it can provide data to the master. Since more than one device may attempt to take control of the bus as a master, SMBus provides an arbitration mechanism, by relying on the wired-AND connection of all SMBus interfaces to the SMBus. DC-to-DC Converter The features of the DC-DC Converter interface are:  Dual drive PWM outputs, with independent closed loop feedback  Software programmable configuration of one of 8 output frequencies (each being a fixed divide of the input clock).  Software programmable configuration of duty cycle from 0 to 15/16, in intervals of 1/16.  Output polarity (for positive or negative voltage gen- eration) is hardware-configured during power-on reset via the polarity select inputs  Each PWM output can be dynamically switched to one of a pair of preprogrammed frequency/duty cycle combinations via external pins. Watchdog Timer (WDT) The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer that is reset by software at regular intervals. Failure to reset the timer will cause a FIQ inte rrupt. Failure to service the FIQ interrupt will then generate a System Reset. The WDT features are:  Driven by the system clock  16 programmable time-out periods: 2 16 through 231 clock cycles  Generates a system reset (resets LH7A400) or a FIQ Interrupt whenever a time-out period is reached  Software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes  Protection mechanism guards against interrupt-service-failure: – The first WDT time-out triggers FIQ and asserts nWDFIQ status flag – If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a System Reset. General Purpose I/O (GPIO) The LH7A400 GPIO has eight ports, each with a data register and a data direction register. It also has added registers including Keyboard Scan, PINMUX, GPIO Interrupt Enable, INTYPE1/2, GPIOFEOI, and PGHCON. The data direction register determines whether a port is configured as an input or an output while the data register is used to read the value of the GPIO pins. The GPIO Interrupt Enable, INTYPE1/2, and GPI- OFEOI registers are used to control edge-triggered Interrupts on Port F. The PINMUX register controls what signals are output of Port D and Port E when they are set as outputs, while the PGHCON controls the operations of Port G and H.

32-Bit System-on-Chip LH7A400 Preliminary data sheet Rev. 01 — 16 July 2007 29 NXP Semiconductors ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings NOTE: Except for Storage Temperature, these ratings are only for transient conditions. Operation at or beyond absolute maxi- mum rating conditions may affe ct reliability and cause per- manent damage to the device. Recommended Operating Conditions NOTES: 1. Core Voltage should never exceed I/O Voltage after in itial power up. See “Power Supply Sequencing” on page 33 2. USB is not functional below 3.0 V 3. Using 14.7456 MHz Main Oscillator Crysta l and 32.768 kHz RTC Oscillator Crystal 4. VDDC = 1.71 V to 1.89 V (LH7A400N0G000xx) 5. VDDC = 2.1 V ±5 % (LH7A400N0G076xx only) 6. VDD = 3.0 V to 3.6 V (LH7A400N0G000xx) 7. VDD = 3.14V to 3.60 V (LH7A400N0G076xx only) 8. IMPORTANT: Most peripherals will NOT func tion with crystals other than 14.7456 MHz. PARAMETER MINIMUM MAXIMUM DC Core Supply Voltage (VDDC) −0.3 V 2.4 V DC I/O Supply Voltage (VDD) −0.3 V 4.6 V DC Analog Supply Voltage (VDDA) −0.3 V 2.4 V 5 V Tolerant Digital Input Pin Voltage −0.5 V 5.5 V ESD, Human Body Model (Analog pins AN0 - AN9 rated at 500 V) 2 kV ESD, Charged Device Model 1 kV Storage Temperature −55°C 125°C PARAMETER MINIMUM TYPICAL MAXIMUM NOTES DC Core Supply Voltage (VDDC) 1.71 V 1.8 V 1.89 V 1, 4 DC Core Supply Voltage (VDDC) 2.0 V 2.1 V 2.2 V 1, 5 DC I/O Supply Voltage (VDD) 3.0 V 3.3 V 3.6 V 2, 6 DC I/O Supply Voltage (VDD) 3.14 V 3.3 V 3.6 V 2, 7 DC Analog Supply Voltage for PLLs (VDDA) 1.71 V 1.8 V 1.89 V Clock Frequency ( 0°C to +70°C) 10 MHz 200 MHz 3, 4, 6 Clock Frequency (−40°C to +85°C) 10 MHz 195 MHz 3, 4, 6 Bus Clock Frequency (−40°C to +85°C) 100 MHz 3, 4, 6 Clock Frequency (0°C to +70°C) 10 MHz 250 MHz 3, 5, 7 Clock Frequency (−40°C to +85°C) 10 MHz 245 MHz 3, 5, 7 Bus Clock Frequency (−40°C to +85°C) 125 MHz 3, 5, 7 External Clock Input (XTALIN) 14 MHz 14.7456 MHz 20 MHz 8 External Clock Input (XTALIN) Voltage 1.71 V 1.8 V 1.89 V Operating Temperature −40°C 25°C +85°C

1. Table 9 is representative of a typical wafer process. Guaranteed

Figure 8. Temperature/Voltage/Speed Chart Table 9. C lock Frequency vs. Voltages (VDDC) vs. Temperature

1.89 V (+5%)

1.71 V (-5%)

32-Bit System-on-Chip LH7A400 Preliminary data sheet Rev. 01 — 16 July 2007 31 NXP Semiconductors DC/AC SPECIFICATIONS Unless otherwise noted, all data provided in these specifications are based on −40°C to +85°C, VDDC = to 1.89 V. DC Specifications NOTES: 1. Output Drive 5 can sink 20 mA of current, but sources 12 mA of current. 2. Current consumption until oscillators are stabilized. AC Test Conditions SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS NOTES VIH CMOS and Schmitt Trigger Input HIGH Volt- age 2.0 5.5 V VIL CMOS and Schmitt Trigger Input LOW Volt- age −0.2 0.8 V VHST Schmitt Trigger Hysteresis 0.25 V VIL to VIH VOH Output Drive 2 2.6 V IOH = −4 mA Output Drive 3 2.6 V IOH = −8 mA Output Drive 4 and 5 2.6 V IOH = −12 mA 1 VOL Output Drive 2 0.4 V IOL = 4 mA Output Drive 3 0.4 V IOL = 8 mA Output Drive 4 0.4 V IOL = 12 mA Output Drive 5 0.4 V IOL = 20 mA 1 IIN Input Leakage Current −10 10 µA VIN = VDD or GND Input Leakage Current (with pull-up resistors installed) −200 −20 µA VIN = VDD or GND IOZ Output Tri-state Leakage Current −10 10 µA VOUT = VDD or GND ISTARTUP Startup Current 50 µA2 IACTIVE Active Current 125 180 mA IHALT Halt Current 25 41 mA ISTANDBY Standby Current 42 µA CIN Input Capacitance 4 pF COUT Output Capacitance 4 pF PARAMETER RATING UNIT DC I/O Supply Voltage (VDD) 3.0 to 3.6 V DC Core Supply Voltage (VDDC) 1.71 to 1.89 V Input Pulse Levels VSS to 3 V Input Rise and Fall Times 2 ns Input and Output Timing Reference Levels VDD/2 V

 Maximum specified ambient temperature (tAMB).  Nominal case temperature (tAMB). Table 10. Current Consumption by Mode Table 11. Peripheral Current Consumption

Table 12. AC Signal Characteristics

1. Register BCRx:WST1 = 0b000
2. For Output Drive strength spec ifications, refer to Table 3

Table 12. AC Signal Characteristics (Cont’d)

Figure 11. External Asynchronous Memory Write with 4 Wait States (BCRx:WST1 = 0b100)

0 WAIT STATE

Figure 12. External Asynchronous Memory Read with 0 Wait States (BCRx:WST1 = 0b000)

for Activate a Bank and Write. length, depending upon the programmed data size. edge. See Figure 16 and Figure 17. Figure 13. External Asynchronous Memory Read with 4 Wait States (BCRx:WST1 = 0b100)

0 WAIT STATE,

4 WAIT STATES,

Figure 36. STN Horizontal Timing Diagram

1 STN HORIZONTAL LINE

NOTE: Circled numbers are LH7A400 pin numbers.

Figure 37. STN Vert ical Timing Diagram

1. Signal polarties may vary for some displays.
2. LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period.
3. Circled numbers are LH7A400 pin numbers.

Figure 38. TFT Horizontal Timing Diagram

1 TFT HORIZONTAL LINE

NOTE: Circled numbers are LH7A400 pin numbers.

Figure 39. TFT Vertical Timing Diagram

1. Signal polarties may vary for some displays.
2. The use of LCDVDDEN for high-voltage power control is optional on some TFT panels.
3. Circled numbers are LH7A400 pin numbers.

Figure 40. AD-TFT and HR-TFT Horizontal Timing Diagram

1 AD-TFT or HR-TFT HORIZONTAL LINE

1 LCDDCLK

NOTE: Circled numbers are LHA400 pin numbers.

Figure 45. 32.768 kHz External Oscillator Components and Schematic

1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for

a crystal specified at 12.5 pF load capacitance (CL).

1. The values for C1 and C2 are dependent upon
2. R1 must be in the circuit.
3. Ground connections should be short and return

processor's core ground pins.

1. Tolerance for R1, C1, C2 is ≤ 5%.

Figure 46. 14.7456 MHz External Oscillator Components and Schematic

1. Y1 is a parallel-resonant type crystal. (See table)
2. The nominal values for C1 and C2 shown are for

a crystal specified at 18 pF load capacitance (CL).

1. The values for C1 and C2 are dependent upon
2. R1 must be in the circuit.
3. Ground connections should be short and return

processor's core ground pins.

1. Tolerance for R1, C1, C2 is ≤ 5%.

14.7456 MHz Crystal

perature, the faster the CMOS circuits will switch. application executed on the SoC. (i.e., noise immunity of the clock input to the SoC). supply analog power to the PLLs. capacitor near each VDDx, VSSx pair on the chip. quency capacitor should be as short as possible. to its inactive state. 33 KΩ or less is recommended. require external conditioning. larly applies to the address and data buses. and proximity to ground and power planes. ground return paths also increase. Figure 47. VDDA, VSSA Filter Circuit

Figure 48. Package outline SOT1018-1 (BGA256)

Figure 49. Package outline SOT1020-1 (LFBGA256)

32-Bit System-on-Chip LH7A400 Preliminary data sheet Rev. 01 — 16 July 2007 61 NXP Semiconductors

REVISION HISTORY

Table 14. Revision history

• First NXP version based on the LH7A400 data sheet of 20070509

© NXP B.V. 2007. All rights reserved. LH7A400 32-Bit System-on-Chip 1. Legal information

1.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com

1.2 Definitions

Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.

1.3 Disclaimers

General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.

1.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 2. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docum ent contains the product specification.

Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright © (year) by SHARP Corporation. is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document. NXP Semiconductors

ANNEX A: Disclaimers (11) 1. t001dis100.fm: General (DS, AN, UM) General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.

1. t001dis106.fm: No offer to sell or license (DS) No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. 8. t001dis107.fm: Hazardous voltage (DS, AN, UM; if applicable) Hazardous voltage — Although basic supply voltages of the product may be much lower, circuit voltages up to 60 V may appear when operating this product, depending on settings and application. Customers incorporating or otherwise using these products in applications where such high voltages may appear during operation, assembly, test etc. of such application, do so at their own risk. Customers agree to fully indemnify NXP Semiconductors for any damages resulting from or in connection with such high voltages. Furthermore, customers are drawn to safety standards (IEC 950, EN 60 950, CENELEC, ISO, etc.) and other (legal) requirements applying to such high voltages. 9. t001dis108.2.fm: Bare die (DS; if applicable) Bare die (if applicable) — Products indicated as Bare Die are subject to separate specifications and are not tested in accordance with standard testing procedures. Product warranties and guarantees as stated in this document are not applicable to Bare Die Products unless such warranties and guarantees are explicitly stated in a valid separate agreement entered into by NXP Semiconductors and customer. 10. t001dis109.fm: AEC unqualified products (DS, AN, UM; if applicable) AEC unqualified products — This product has not been qualified to the appropriate Automotive Electronics Council (AEC) standard Q100 or Q101 and should not be used in automotive critical applications, including but not limited to applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is for the customer’s own risk. 11. t001dis110.fm: Suitability for use in automotive applications only (DS, AN, UM; if applicable) Suitability for use in automotive applications only — This NXP Semiconductors product has been developed for use in automotive applications only. The product is not designed, authorized or warranted to be suitable for any other use, including medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk.