LH79524 NXP
Document overview
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Technical content
LH79524/LH79525 (A.1) Preliminary data sheet System-on-Chip
FEATURES
- Highly Integrated System-on-Chip High Performance: 76.205 MHz CPU Speed,
50.803 MHz maximum AHB clock (HCLK)
32-bit ARM720T™ RISC Core – LH79524: 32-bit External Data Bus – 208 LFBGA package – LH79525: 16-bit External Data Bus – 176 LQFP package 8 kB Cache with Write Back Buffer MMU (Windows CE™ Enabled) 16 kB On-Chip SRAM Flexible, Programmable Memory Interface – SDRAM Interface – 512 MB External Address Space – 32-bit External Data Bus (LH79524) – 16-bit External Data Bus (LH79525) – SRAM/Flash/ROM Interface – 15-bit External Address Bus – 32-bit External Data Bus (LH79524) – 16-bit External Data Bus (LH79525) Multi-stream DMA Controller – Four 32-bit Burst- Based Data Streams Clock and Power Management – 32.768 kHz Oscillator for Real Time Clock – 10 MHz to 20 MHz Oscillator and On-chip PLL – Active, Standby, Sleep, Stop1, and Stop2 Modes – Externally-supplied Clock Options On-Chip Boot ROM – Allows Booting from 8-, 16-, or 32-bit Devices – NAND Flash Boot Low Power Modes – Active Mode: 85 mA (MAX.) – Standby Mode: 50 mA (MAX.) – Sleep Mode: 3.8 mA (TYP.) – Stop Mode 1: 420 µA (TYP.) – Stop Mode 2: 25 µA (TYP.) USB Device – Compliant with USB 2.0 Specifications (Full Speed) – Four Endpoints Ethernet MAC, with MII and MDIO Interfaces – IEEE 802.3 Compliant – 10 and 100 Mbit/s Operation Analog-to-Digital Converter/Brownout Detector –1 0 - b i t A D C – Pen Sense Interrupt – Integrated Touch Screen Controller (TSC) 2C Module Integrated Codec Interface Support Features (I 2S) Watchdog Timer Vectored Interrupt Controller – 16 Standard and 16 Vectored IRQ Interrupts – Interrupts Individually Configurable as IRQ or FIQ Three UARTs – 16-entry FIFOs for Rx and Tx – IrDA SIR Support on all UARTs Three 16-bit Timers with PWM capability Real Time Clock – 32-bit Up-counter with Programmable Load – Programmable 32-bit Match Compare Register Programmable General Purpose I/O Signals – LH79524: 108 available pins on 14 ports – LH79525: 86 available pins on 12 ports Programmable Color LCD Controller – 16 (LH79524) or 12 (LH79525) Bits-per-Pixel – Up to 800 × 600 resolution – STN, Color STN, HR-TFT, AD-TFT, TFT – TFT: Supports 64 k (LH79524) or 4 k (LH79525) Direct Colors or 256 colors selected from a Palette of 64 k Colors; 15 Shades of Gray – Color STN: Supports 3,375 Direct Colors or 256 Colors Selected from a Palette of 3,375 Colors Synchronous Serial Port – Supports Data Rates Up to 1.8452 Mbit/s – Compatible with Common Interface Schemes JTAG Debug Interface and Boundary Scan 5 V Tolerant Digital Inpu ts (excludes oscillator pins) – XTALIN and XTAL32IN pins are 1.8 V ± 10% On-Chip regulator allows single 3.3 V supply
DESCRIPTION
The LH79524/LH79525, powered by an ARM720T, is a complete System-on-Chip with a high level of inte- gration to satisfy a wide range of requirements and applications. The SoC has a fully static design, power management unit, and low voltage operation (1.8 V Core, 3.3 V I/O). With the on-chip voltage regulator, a single 3.3 V supply can be used as well. Robust periph- erals and a low-power RISC core provide high perfor- mance at a reasonable price.
LH79524/LH79525 System-on-Chip 2R e v . 0 1 — 16 July 2007 Preliminary data sheet NXP Semiconductors
ORDERING INFORMATION
Table 1. Ordering information
Figure 1. LH79524/LH79525 block diagram
4 CHANNEL
10 CHANNEL
Table 2. LH79524 Pin Descriptions
Table 2. LH79524 Pin Descriptions (Cont’d)
ted Serial Data Output, UART0 Serial Transmit Data Out, and External Interrupt 1.
Table 3. LH79524 Numerical Pin List Table 3. LH79524 Numerical Pin List (Cont’d)
- Internal pull-down. The internal pullup and pulldown resistance
on all digital I/O pins is 50KΩ.
- Internal pull-up. The internal pu llup and pulldown resistance on all
- USB Inputs/outputs are tristated.
- Output is for crys tal oscillator only, no drive capability.
- Crystal Oscillator Inputs s hould be driven to a maximum of
- Input with Schmitt Trigger.
- Output Drive Values are M AX. See ‘DC Specifications’.
- All unused analog pins, and XTAL32IN (if unused) should be tied
to ground through a 33KΩ resistor. Table 4. TESTx PIN FUNCTION
Table 5. LH79525 Pin Descriptions
69 A10
67 A11
65 A12
63 A13
62 A14
61 A15
117 SDCLK O SDRAM Clock
116 SDCKE O SDRAM Clock Enable
119 DQM0 O Data Mask Output to SDRAMs118 DQM1
130 USBDN I/O USB Data Negative (Differential Pair output, single ended and Differential input)
131 USBDP I/O USB Data Positive (Differential Pair output, single ended and Differential input)
11 AN0/UL/X+ I ADC Input 0, 4 wire touch screen Upper Left, 5 wire touch screen X+
14 AN1/UR/X– I ADC Input 1, 4 wire touch scr een Upper Right, 5 wire touch screen X–
17 AN2/LL/Y+/PJ3 I ADC Input 2, 4 wire touch screen Lower Left, 5 wire touch screen Y+; multiplexed with
20 AN3/LR/Y–/PJ0 I ADC Input 3, 4 wire touch screen Upper Right, 5 wire touch screen Y–; multiplexed
19 AN4/WIPER/PJ1 I ADC Input 4, 5 wir e touch screen Wiper input; multiplexed with Port J1 (input only)
15 AN5/PJ5/INT5 I ADC Input 5; multiplexed with GPIO Port J5 (input only) and External Interrupt 5
12 AN6/PJ7/INT7 I ADC Input 6; multiplexed with GPIO Port J7 (input only) and External Interrupt 7
13 AN7/PJ6/INT6 I ADC Input 7; multiplexed with GPIO Port J6 (input only) and External Interrupt 6
16 AN8/PJ4 I ADC Input 8; multiplexed with GPIO Port J4 (input only)
18 AN9/PJ2 I ADC Input 9; multiplexed with GPIO Port J2 (input only)
25 CTCLK/INT4/
36 PA0/UARTRX2/
35 PA1/UARTTX2/
34 PA2/CTCAP0A/
32 PA3/CTCAP0B/
31 PA4/CTCAP1A/
30 PA5/CTCAP1B/
29 PA6/CTCAP2A/
28 PA7/CTCAP2B/
44 PB0/nDACK/
43 PB1/DREQ/
42 PB2/SSPFRM/
41 PB3/SSPCLK/
60 PC0/A16 I/O General Purpose I/O Signal — Port C0; multiplexed with Address A16
59 PC1/A17 I/O General Purpose I/O Signal — Port C1; multiplexed with Address A17
58 PC2/A18 I/O General Purpose I/O Signal — Port C2; multiplexed with Address A18
56 PC3/A19 I/O General Purpose I/O Signal — Port C3; multiplexed with Address A19
55 PC4/A20 I/O General Purpose I/O Signal — Port C4; multiplexed with Address A20
54 PC5/A21 I/O General Purpose I/O Signal — Port C5; multiplexed with Address A21
Table 5. LH79525 Pin Descriptions (Cont’d)
53 PC6/A22/nFWE I/O General Purpose I/O Signal — Port C6; multiplexed with Address A22 and NAND
52 PC7/A23/nFRE I/O General Purpose I/O Signal — Port C7; multiplexed with Address A23 and NAND
90 PD0/D8 I/O General Purpose I/O Signal — Port D0; multiplexed with Data D8
89 PD1/D9 I/O General Purpose I/O Signal — Port D1; multiplexed with Data D9
88 PD2/D10 I/O General Purpose I/O Signal — Port D2; multiplexed with Data D10
87 PD3/D11 I/O General Purpose I/O Signal — Port D3; multiplexed with Data D11
85 PD4/D12 I/O General Purpose I/O Signal — Port D4; multiplexed with Data D12
84 PD5/D13 I/O General Purpose I/O Signal — Port D5; multiplexed with Data D13
83 PD6/D14 I/O General Purpose I/O Signal — Port D6; multiplexed with Data D14
82 PD7/D15 I/O General Purpose I/O Signal — Port D7; multiplexed with Data D15
141 PE0/LCDLP/
139 PE1/LCDDCLK I/O General Purpose I/O Signals — Port E1; multiplexed with LCD Data Clock
138 PE2/LCDPS I/O General Purpose I/O Signals — Port E2; multiplexed with LCD Power Save
137 PE3/LCDCLS I/O General Purpose I/O Signals — Port E3; multiplexed with LCD Row Driver Clock
136 PE4/LCDDSPLEN/
134 PE5/LCDVDDEN I/O General Purpose I/O Signals — Port E5; multiplexed with LCD VDD Enable
133 PE6LCDVEEN/
120 PE7/nWAIT/nDEOT I/O General Purpose I/O Signals — Port E7; multiplexed with nWAIT and DMA
153 PF0/LCDVD6 I/O General Purpose I/O Signals — Port F0; multiplexed with LCD Video Data bit 6
151 PF1/LCDVD7 I/O General Purpose I/O Signals — Port F1; multiplexed with LCD Video Data bit 7
149 PF2/LCDVD8 I/O General Purpose I/O Signals — Port F2; multiplexed with LCD Video Data bit 8
147 PF3/LCDVD9 I/O General Purpose I/O Signals — Port F3; multiplexed with LCD Video Data bit 9
146 PF4/LCDVD10 I/O General Purpose I/O Signals — Port F4; multiplexed with LCD Video Data bit 10
145 PF5/LCDVD11 I/O General Purpose I/O Signals — Port F5; multiplexed with LCD Video Data bit 11
143 PF6/LCDEN/
142 PF7/LCDFP/
162 PG0/ETHERTXEN I/O General Purpose I/O Signals — Po rt G0; multiplexed with Ethernet Transmit Enable
161 PG1/ETHERTXCLK I/O General Purpose I/O Signals — Port G1; multiplexed with Ethernet Clock
159 PG2/LCDVD0 I/O General Purpose I/O Signals — Port G2; multiplexed with LCD Video Data bit 0
158 PG3/LCDVD1 I/O General Purpose I/O Signals — Port G3; multiplexed with LCD Video Data bit 1
157 PG4/LCDVD2 I/O General Purpose I/O Signals — Port G4; multiplexed with LCD Video Data bit 2
156 PG5/LCDVD3 I/O General Purpose I/O Signals — Port G5; multiplexed with LCD Video Data bit 3
155 PG6/LCDVD4 I/O General Purpose I/O Signals — Port G6; multiplexed with LCD Video Data bit 4
154 PG7/LCDVD5 I/O General Purpose I/O Signals — Port G7; multiplexed with LCD Video Data bit 5
171 PH0/ETHERRX3 I/O General Purpose I/O Signals — Port H0; multiplexed with Ethernet Receive Channel 3
170 PH1/ETHERRXDV I/O General Purpose I/O Signals — Port H1; multiplexed with Ethernet Data Valid
169 PH2/ETHERRXCLK I/O General Purpose I/O Signals — Port H2; multiplexed with Ethernet Receive Clock
167 PH3/ETHERTXER I/O General Purpose I/O Signals — Po rt H3; multiplexed with Ethernet Transmit Error
166 PH4/ETHERTX0 I/O General Purpose I/O Signals — Port H4; multiplexed with Ethernet Transmit Channel 0
165 PH5/ETHERTX1 I/O General Purpose I/O Signals — Port H5; multiplexed with Ethernet Transmit Channel 1
164 PH6/ETHERTX2 I/O General Purpose I/O Signals — Port H6; multiplexed with Ethernet Transmit Channel 2
163 PH7/ETHERTX3 I/O General Purpose I/O Signals — Port H7; multiplexed with Ethernet Transmit Channel 3
4 PI0/ETHERMDC I/O General Purpose I/O Signals — Port I0; multiplexed with Ethernet Management
1 PI2/ETHERCOL I/O General Purpose I/O Signals — Po rt I2; multiplexed with Ethernet Collision Detect
176 PI3/ETHERCRS I/O General Purpose I/O Signals — Port I3; multiplexed with Ethernet Carrier Sense
175 PI4/ETHERRXER I/O General Purpose I/O Signals — Port I4; multiplexed with Ethernet Receive Error
174 PI5/ETHERRX0 I/O General Purpose I/O Signals — Port I5; multiplexed with Ethernet Receive Channel 0
173 PI6/ETHERRX1 I/O General Purpose I/O Signals — Port I6; multiplexed with Ethernet Receive Channel 1
172 PI7/ETHERRX2 I/O General Purpose I/O Signals — Port I7; multiplexed with Ethernet Receive Channel 2
127 XTALIN I Crystal Input, or external clock input
128 XTALOUT O Crystal Output
50 TMS I JTAG Test Mode Select Input
51 TCK I JTAG Test Clock Input
46 TDI I JTAG Test Serial Data Input
45 TDO O JTAG Test Data Serial Output
47 TEST1 I Tie HIGH for Normal Operation; pull LOW to enable embedded ICE Debugging
48 TEST2 I Tie HIGH for Normal Operation; pull HIGH to enable embedded ICE Debugging
10 VDDA0 Power Analog Power Supply for Analog-to-Digital Converter
122 VDDA1 Power Analog Power Supply for the USB PLL
123 VDDA2 Power Analog Power Supply for System PLL
21 VSSA0 Ground Analog GND for A nalog-to-Digital Converter
121 VSSA1 Ground Analog GN D for the USB PLL
124 VSSA2 Ground Analog GND for System PLL
Table 6. LH79525 Numerical Pin List
1 PI2 ETHERCOL 8 mA 1 2 PI1 ETHERMDIO 8 mA 2
Table 6. LH79525 Numerical Pin List (Cont’d)
4 PI0 ETHERMDC 8 mA 1
5 VSS
7 VSSC
9 LINREGEN
10 VDDA0
11 AN0/UL/X+
12 AN6 PJ7/INT7
13 AN7 PJ6/INT6
14 AN1/UR/X-
15 AN5 PJ5/INT5
16 AN8 PJ4
17 AN2/LL/Y+ PJ3
18 AN9 PJ2
19 AN4/WIPER PJ1
20 AN3/LR/Y- PJ0
21 VSSA0
23 CLKOUT 8 mA
25 CTCLK INT4/BATCNTL 8 mA 2, 3
26 VDD
27 VSS
28 PA7 CTCAP2B/CTCMP2B/
29 PA6 CTCAP2A/CTCMP2A/
30 PA5 CTCAP1B/CTCMP1B 8 mA 1, 3
31 PA4 CTCAP1A/CTCMP1A 8 mA 1, 3
32 PA3 CTCAP0B/CTCMP0B 8 mA 1, 3
33 VDD
34 PA2 CTCAP0A/CTCMP0A 8 mA 1, 3
35 PA1 INT3/UARTTX2/
36 PA0 INT2/UARTRX2/
37 PB7 INT1/UARTTX0/
38 PB6 INT0/UARTRX0/
39 PB5 SSPTX/I2STXD/
40 PB4 SSPRX/I2SRXD/
41 PB3 SSPCLK/I2SCLK 8 mA 1
42 PB2 SSPFRM/I2SWS 8 mA 2
43 PB1 DREQ/nUARTRTS0 8 mA 2
44 PB0 nDACK/nUARTCTS0 8 mA 2
45 TDO 4 mA
46 TDI 2, 3
47 TEST1 2, 3
48 TEST2 2, 3
49 VSS
50 TMS 2, 3
51 TCK 2, 3
52 PC7 A23/nFRE 8 mA 1
53 PC6 A22/nFWE 8 mA 1
54 PC5 A21 8 mA 1
55 PC4 A20 8 mA 1
56 PC3 A19 8 mA 1
57 VDD
58 PC2 A18 8 mA 1
59 PC1 A17 8 mA 1
60 PC0 A16 8 mA 1
61 A15 8 mA
62 A14 8 mA
63 A13 8 mA
64 VSSC
65 A12 8 mA
66 VDDC
67 A11 8 mA
68 VSS
69 A10 8 mA
70 A9 8 mA
71 A8 8 mA
72 A7 8 mA
73 A6 8 mA
74 A5 8 mA
75 VDD
76 A4 8 mA
77 A3 8 mA
78 A2 8 mA
79 A1 8 mA
80 A0 8 mA
81 VSS
82 PD7 D15 8 mA 1
83 PD6 D14 8 mA 1
84 PD5 D13 8 mA 1
85 PD4 D12 8 mA 1
86 VDD
87 PD3 D11 8 mA 1
88 PD2 D10 8 mA 1
89 PD1 D9 8 mA 1
90 PD0 D8 8 mA 1
91 D7 8 mA 1
92 VSS
93 D6 8 mA 1
94 D5 8 mA 1
95 D4 8 mA 1
96 D3 8 mA 1
- Internal pull-down. The internal pullup and pulldown resistance
on all digital I/O pins is 50KΩ.
- Internal pull-up. The internal pu llup and pulldown resistance on all
- Input with Schmitt Trigger.
- USB Inputs/outputs are tristated.
- Crystal Inputs should be driv en to a maximum of 1.8 V ± 10%.
- Output is for crys tal oscillator only, no drive capability.
- Output Drive Values shown ar e MAX. See ‘DC Specifications’.
- All unused analog pins, and XTAL32IN (if unused) should be tied
97 D2 8 mA 1
98 D1 8 mA 1
99 D0 8 mA 1
101 VDD
105 VSSC
107 VDDC
108 VSS
116 SDCKE 8 mA
117 SDCLK 12 mA
118 DQM1 8 mA
119 DQM0 8 mA
120 PE7 nWAIT/nDEOT 8 mA 2, 3
121 VSSA1
122 VDDA1
123 VDDA2
124 VSSA2
125 XTAL32IN 5
126 XTAL32OUT 6
127 XTALIN 5
128 XTALOUT 6
129 VDD
130 USBDN 4
131 USBDP 4
132 VSS
133 PE6 LCDVEEN/
134 PE5 LCDVDDEN 8 mA 1
135 VDD
136 PE4 LCDDSPLEN/LCDREV 8 mA 1
137 PE3 LCDCLS 8 mA 1
138 PE2 LCDPS 8 mA 1
139 PE1 LCDDCLK 8 mA 1
140 VSS
141 PE0 LCDLP/LCDHRLP 8 mA 1
142 PF7 LCDFP/LCDSPS 8 mA 1
143 PF6 LCDEN/LCDSPL 8 mA 1
144 VDD
145 PF5 LCDVD11 8 mA 2
146 PF4 LCDVD10 8 mA 2
147 PF3 LCDVD9 8 mA 2
148 VSSC
149 PF2 LCDVD8 8 mA 2
150 VDDC
151 PF1 LCDVD7 8 mA 1
152 VSS
153 PF0 LCDVD6 8 mA 1
154 PG7 LCDVD5 8 mA 1
155 PG6 LCDVD4 8 mA 1
156 PG5 LCDVD3 8 mA 1
157 PG4 LCDVD2 8 mA 1
158 PG3 LCDVD1 8 mA 1
159 PG2 LCDVD0 8 mA 1
160 VDD
161 PG1 ETHERTXCLK 8 mA 1
162 PG0 ETHERTXEN 8 mA 1
163 PH7 ETHERTX3 8 mA 1
164 PH6 ETHERTX2 8 mA 1
165 PH5 ETHERTX1 8 mA 1
166 PH4 ETHERTX0 8 mA 1
167 PH3 ETHERTXER 8 mA 1
168 VSS
169 PH2 ETHERRXCLK 8 mA 1
170 PH1 ETHERRXDV 8 mA 1
171 PH0 ETHERRX3 8 mA 1
172 PI7 ETHERRX2 8 mA 1
173 PI6 ETHERRX1 8 mA 1
174 PI5 ETHERRX0 8 mA 1
175 PI4 ETHERRXER 8 mA 1
176 PI3 ETHERCRS 8 mA 1
- Recommended hookups for TFT 5:5:5 + Intensity and 5:6:5 are shown.
- The Intensity bit is identical ly generated for all three colors.
- Connect to the LSB of the Red, Green, and Blue inputs of a 6:6:6 panel.
- CLSTN = Color Lower data bit for STN panel.
- CUSTN = Color Upper data bit for STN panel.
- MLSTN = Monochrome Lower data bit for STN panel.
- MUSTN = Monochrome Upper data bit for STN panel.
Table 7. TESTx PIN FUNCTION Table 8. LH79524 LCD Data Multiplexing Table 9. LH79525 LCD Data Multiplexing
145 LCDVD11 MUSTN1 MUSTN1
146 LCDVD10 MUSTN0 MUSTN0
147 LCDVD9
149 LCDVD8
151 LCDVD7 MLSTN3
153 LCDVD6 MLSTN2
154 LCDVD5 MLSTN1
155 LCDVD4 MLSTN0
156 LCDVD3
the user to storing the TT and PT’s.
157 LCDVD2
158 LCDVD1 MUSTN3 MUSTN3
159 LCDVD0 MUSTN2 MUSTN2
Figure 4. LH79524/LH79525 Application Diagram Example
transfers from input to output. timing ASIC in standard TFT and STN panels. ments Synchronous Serial Interface. Available internal loopback test mode. Figure 8. Memory Remap ‘11’
The LH79524/LH79525 incorporates three UARTs. to 512 for low-power mode bit durations. inputs of the ARM7TDMI processor core. embedded control applications. The 32 interrupt channels are shown in Table 10. Table 10. Interrupt Channels
1 Not Used
2 COMRX (used for debug)
3 COMTX (used for debug)
4 Counter/Timer0 Combined
5 Counter/Timer1 Combined
6 Counter/Timer2 Combined
7 External Interrupt 0
8 External Interrupt 1
9 External Interrupt 2
10 External Interrupt 3
11 External Interrupt 4
12 External Interrupt 5
13 External Interrupt 6
14 External Interrupt 7
15 RTC_ALARM
16 ACD TSIRQ Combined
17 ADC Brown Out INTR
to operate the chip in the most power-efficient mode. each clock appear in the User’s Guide. Hardware reset (nRESET IN) and software reset. pare registers are identical.
18 ADC Pen IRQ
19 CLCD Combined Interrupt
20 DMA Stream 0
21 DMA Stream 1
22 DMA Stream 2
23 DMA Stream 3
24 SSP I
25 Ethernet Interrupt
26 USB Interrupt
27 UART 0 Interrupt
28 UART 1 Interrupt
29 UART 2 Interrupt
30 USB DMA Interrupt
Table 10. Interrupt Channels (Cont’d) Table 11. Maximum Clock Speeds Table 12. Clock Activity for Different Power Modes
System-on-Chip LH79524/LH79525 Preliminary data sheet Rev. 01 — 16 July 2007 25 NXP Semiconductors Watchdog Timer The Watchdog Timer provides hardware protection against malfunctions. It is a programmable timer to be reset by software at regular intervals. Failure to reset the timer will cause a FIQ inte rrupt. Failure to service the FIQ interrupt will then generate a System Reset. The features of the Watchdog Timer are: Driven by the bus clock 16 programmable time-out periods: 2 16 through 231 clock cycles Generates a reset or an FIQ Interrupt whenever a time-out period is reached Software enable, lockout, and counter-reset mecha- nisms add security against inadvertent writes Protection mechanism guards against interrupt-ser- vice failure: – The first WDT time-out triggers FIQ and asserts nWDFIQ status flag – If FIQ service routine fails to clear nWDFIQ, then the next WDT time-out triggers a system reset. Timers The LH79524 and LH79525 incorporate three 16-bit independently programmable Timer modules. The tim- ers are clocked by the system clock, but have an inter- nal scaled-down system clock that is used for the Pulse Width Modulator (PWM) and compare functions. All counters are incremented by an internal pre- scaled counter clock or external clock and can gener- ate an overflow interrupt. All three timers have separate internal prescaled counter clocks, with either a com- mon external clock or a pr escaled version of the sys- tem clock. Timer 0 has five Capture Registers and two Com- pare Registers. Timer 1 and Timer 2 have two Capture and two Com- pare Registers each. The Capture Registers have edge-selectable inputs and can generate an interrupt. The Compare Registers can force the compare output pin either HIGH or LOW upon a match. The timers support a PWM Mode that uses the two Timer Compare Registers associated with a timer to create a PWM. Each timer can generate a separate interrupt. The interrupt becomes active if any enabled compare, capture, or overflow interrupt condition occurs. The interrupt remains active until all compare, capture, and overflow interrupts are cleared. General Purpose Input/Output (GPIO) The LH79524 provides up to 108 bits of programma- ble input/output, and the LH79525 provides 86 bits. Many of the GPIO pins are multiplexed with other sig- nals. All GPIO feature: Individually programmable input/output pins All default to Input on power-up. LH79524 – Ports A-I, K, L, and N: Bidirectional I/O (Port N is 4 bits wide) – Port J: Input only – Port M: Output only LH79525 – Ports A-I: Bidirectional I/O – Port J: Input only – Port M: Output only (6 bits wide) Boot Controller The boot controller allows selection of the hardware device to be used for booting. Supports booting from 8-, 16-, or 32-bit devices, selectable via external pins at power-on reset Configures the byte lane boot state for nCS1, selectable via external pins at power-on reset. Supports booting from alternate external devices (e.g., NAND flash) via external pins on power-on reset Glueless interface to external NAND flash. USB Device The USB Device integrated into the LH79524/ LH79525 is compliant with the USB 1.1 and 2.0 speci- fication, and compatible with both the OpenHCI and Intel UHCI standards. The USB Device: Supports Full-Speed (12 Mbit/s) operation, and suspend and resume signaling Four Endpoints Bulk/Interrupt or Isochronous Transfers FIFO for each Endpoint direction (except EP0 which shares a FIFO between IN/OUT). FIFOs exist in 2464 × 8 RAM Supports DMA accesses to FIFO.
LH79524/LH79525 System-on-Chip 26 Rev. 01 — 16 July 2007 Preliminary data sheet NXP Semiconductors Ethernet MAC Controller The on-board Ethernet MAC Controller (EMAC) is compatible with IEEE 802.3, and has passed the Uni- versity of New Hampshire (U NH) testing. It supports both 10- and 100-Mbit/s, and full and half duplex oper- ation. Other features include: Statistics counter re gisters for RMON/MIB MII interface to the physical layer Interrupt generation to signal receive and transmit completion Transmit and receive FIFOs Automatic pad and CRC gen eration on transmitted frames Automatic discard of frames received with errors Address checking logic supports up to four specific (hardware) 48-bit addresses Supports promiscuous mode where all valid received frames are copied to memory Hash matching of unicast and multicast destination addresses Supports physical layer management through MDIO interface Supports serial network interface operation Support for: – Half duplex flow control by forcing collisions on in- coming frames – Full duplex flow control with recognition of incom- ing pause frames and hardware generation of transmitted pause frames – 802.Q VLAN tagging with recognition of incoming VLAN and priority tagged frames Multiple buffers per receive and transmit frame Software configures the MAC address Jumbo frames of up to 10,240 bytes supported. I2C Controller The I 2C Controller includes a two-wire I 2C serial interface capable of operating in either Master or Slave mode. The block conforms to the I 2C 2.1 Bus Specifi- cation for data rates up to 400 kbit/s. The two wires are SCL (serial clock) and SDA (serial data). The I 2C mod- ule provides the following features: Two-wire synchronous serial interface Operates in both the standard mode, for data rates up to 100 kbit/s, and the fast mode, with data rates up to 400 kbit/s Communicates with devices in the fast mode as well as the standard mode if both are attached to the bus. SSP To I2S Converter The SSP to I 2S converter is an interface that con- verts a synchronous serial communication stream in TI DSP-compatible mode into an I 2S compliant synchro- nous serial stream. The I 2S converter operates on serial data in both master and slave mode. The I2S converter provides: Programmable Word Select (WS) delay Left/right channel information: – Current WS value at the pin – WS value associated with next entry written to TX FIFO – WS value associated with next entry read from RX FIFO Ability to invert WS state Ability to invert the bit clock Supports frame size of 16 bits only. Any other frame size will result in a frame size error. Each frame transmits starting with the most-significant bit. Master and slave modes supported As with the SSP, a single combined interrupt is gen- erated as an OR function of the individual interrupt requests. This interrupt replaces the SSP interrupt, which is used solely as an input to the I 2S converter. Additional interrupts: – Transmit FIFO underrun – Transmit frame size error – Receive frame size error A set of Interrupt registers contain all the information in the SSPIMSC, SSPRIS, and SSPMIS registers, plus the transmit underrun error and frame size errors Additional status bits: – Transmit FIFO Full – Receive FIFO Empty Passes SSP data unaltered when module is not enabled Loopback Test Mode support.
System-on-Chip LH79524/LH79525 Preliminary data sheet Rev. 01 — 16 July 2007 27 NXP Semiconductors ADC and Brownout Detector The ADC block consists of an 10-channel, 10-bit Analog-to-Digital Converter with integrated Touch Screen Controller (TSC). The complete touch screen interface is achieved by combining the front-end bias- ing, control circuitry with analog-to-digital conversion, reference generation, and digital control. The ADC has a bias-and-control network that allows correct operation with both 4- and 5-wire touch panels. A 16-entry × 16-bit wide FIFO holds a 10-bit ADC output and a 4-bit tag number. When the screen is touched, it pushes the conduc- tive coating on the coversheet against the coating on the glass, making electr ical contact. The voltages produced are the analog representation of the position touched. The voltage level of the coversheet is converted continuously by the ADC and monitored by the system. Other features include: 10-bit fully differential Successive Approximation Register (SAR) with integrated sample/hold A 10-channel multiplexer that routes user-selected inputs to the ADC in single-ended and differential modes A 16-entry × 16-bit wide FIFO that holds the 10-bit ADC output Front bias-and-control network for touch screen interface and support functions, which are compati- ble with industry-standard 4- and 5-wire touch-sensi- tive panels Touch-pressure sensing circuits Pen-down sensing circuit and interrupt generator Independent voltage reference generator Conversion automation function to minimize interrupt overhead Brownout Detector Battery Control Signal. ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings NOTE: These stress ratings are only for transient conditions. Oper- ation at or beyond absolute maximum rating conditions may affect reliability and cause permanent damage to the device. Recommended Operating Conditions NOTES: 1. Linear Regulator disabled. 2. With PLL enabled. Without PLL, minimum frequency is 0 MHz. Some peripherals may not operate at minimum frequency. 3. Choose 11.2896 MHz to ensure proper operation of the I2S, USB, and UART peripherals. 4. Core Voltage should never exceed I/O Voltage after initial power up. See “Power Supply Sequencing” on page 28. PARAMETER SYMBOL RATING UNIT DC Core Supply Voltage VDDC -0.3 to 2.4 V DC I/O Supply Voltage VDD -0.3 to 4.6 V DC Analog Supply Voltage for ADC VDDA0 -0.3 to 4.6 V VDDA1 -0.3 to 2.4 V VDDA2 -0.3 to 2.4 V Storage Temperature TSTG -55 to +125 °C PARAMETER MINIMUM TYPICAL MAXIMUM NOTES DC Core Supply Voltage (VDDC) 1.7 V 1.8 V 1.9 V 1, 4 DC I/O Supply Voltage (VDD) 3.0 V 3.3 V 3.6 V 4 DC Analog Supply Voltage (VDDA0) 3.0 V 3.3 V 3.6 V DC Analog Supply Voltage (VDDA1) 1.7 V 1.8 V 1.9 V DC Analog Supply Voltage (VDDA2) 1.7 V 1.8 V 1.9 V Clock Frequency 3.27 MHz 76.205 MHz 2 Crystal Frequency 10.0 MHz 11.2896 MHz 20.0 MHz 3 Operating Temperature (Industrial) -40°C 25°C +85°C
LH79524/LH79525 System-on-Chip 28 Rev. 01 — 16 July 2007 Preliminary data sheet NXP Semiconductors Power Supply Sequencing When the linear regulator is not enabled, NXP rec- ommends that the 1.8 V power supply be energized before the 3.3 V supply. If this is not possible, the 1.8 V supply may not lag the 3.3 V supply by more than 100 µs. If longer delay time is needed, it is recommended that the voltage difference between the two power sup- plies be within 1.5 V during power supply ramp up. To avoid a potential latchup condition, voltage should be applied to input pins only after the device is powered- on as described above. DC/AC Specifications Unless noted, all data provided are based on: -40°C to +85°C (Industrial temperature range) VDDC = 1.7 V to 1.9 V DC SPECIFICATIONS NOTES: 1. Table 2 details each pin’s buffer type. 2. Running Typical Applicati on over operating range. 3. Current measured with CP U stopped and all peripherals enabled Linear Regulator DC Characteristics. SYMBOL PARAMETER MIN. TYP. MAX. UNIT CONDITIONS VIH CMOS input HIGH voltage 2.0 5.5 V CEN = 1 VIL CMOS input LOW voltage 0.8 V CEN = 1 VIT+ Positive Input th reshold voltage (Schmitt pins) 2.0 V CSEN = 1 VIT- Negative Input threshold voltage (Schmitt pins) 0.8 V CSEN = 1 VHYST Schmitt trigger hysteresis 0.35 V CSEN = 1 VOH1 Output drive (2 mA type) 2.6 V IOH = -2 mA Output drive (4 mA type) 2.6 V IOH = -4 mA Output drive (8 mA type) 2.6 V IOH = -8 mA Output drive (12 mA type) 2.6 V IOH = -12 mA VOL1 Output drive (2 mA type) 0.4 V IOL = 2 mA Output drive (4 mA type) 0.4 V IOL = 4 mA Output drive (8 mA type) 0.4 V IOL = 7 mA Output drive (12 mA type) 2.6 V IOH = 12 mA RIN Input leakage pull-up/pull-down resistors 40 k Ω VIN = VDD or GND (Calculate input leakage current at desired VDD) IACTIVE Active current 85 mA Note 2 ISTANDBY Standby current 50 mA Notes 2, 3 ISLEEP Sleep current 3.8 mA ISTOP1 Stop1 current 420 µA ISTOP2 Stop2 current 115 µA RTC ON, Linear Regulator ON ISTOP2 Stop2 current 95 µA RTC OFF, Linear Regulator ON ISTOP2 Stop2 current 45 µA RTC ON, Linear Regulator OFF ISTOP2 Stop2 current 25 µA RTC OFF, Linear Regulator OFF SYMBOL PARAMETER MIN. TYP. MAX. UNIT IQUIESCENT Quiescent Current 75 µA ISLEEPLR Current with Linear Regulator disabled 8 µA IOLR Output Current Range 0.0 200 mA VOLR Output Voltage, Linear Regulator 1.84 V
Table 14. AC Signal Characteristics
Table 14. AC Signal Characteristics (Cont’d)
LH79524/LH79525 System-on-Chip 32 Rev. 01 — 16 July 2007 Preliminary data sheet NXP Semiconductors Analog-To-Digital Converter
Electrical Characteristics
Table 15 shows the ADC electrical characteristics. See Figure 10 for the ADC transfer characteristics. NOTES: 1. The analog section of th e ADC takes 16 × A2DCLK cycles per conversion plus 1 × A2DCLK cycles to be made available in the PCLK domain. An additional 3 × PCLK cycles are required before being available on the APB. 2. The internal voltage reference is driven to nominal value VREF = 2.0 V. Using the Reference Multiplexer, alternative low impedance (RS < 500) voltages can be selected as reference voltages. The range of voltages allowed are specified above. However, the on-chip reference cannot drive the ADC unless the reference buffer is switched on. 3. The analog input pins can be driven anyw here between the power supply rails. If the voltage at the input to the ADC exceeds VREF+ or is below VREF-, the A/D result will saturate appropriately at positive or negative full scale. Trying to pull the analog input pins above or below the power supply rails will cause protection diodes to be forward-biased, resulting in large current source/sink and possible damage to the ADC. 4. Bandgap and other low-bandwidth circuitry oper ating. All other ADC blocks shut down. Table 15. ADC Electrical Characteristics
Figure 10. ADC Transfer Characteristics
- The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O conditioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
- The Read Wait States register (SWAITRD x) must be set to a minimum value of 3.
- For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, anot her read wait state (SWAITRDx) must be
added to the minimum requirement.
- nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
- nWAIT delay cycles are added for all nWAI T assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
- Once nWAIT is sampled high, the current memory transaction is queued to complete.
- Since static and dynamic memo ry cannot be accessed at the same time, any pr olonged access (either due to nWAIT or the Extende d Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
- Timing assumes Output Enable Delay r egister (SWAITOENx) is programmed to 0.
Figure 11. nWAIT Read Sequence (SWAITRDx = 3) Table 16. nWAIT Read Sequence Parameter Definitions
- The timing relationship is specified as a cycle-based timing. Variations caused by clock jitter, power rail noise, and I/O conditioning will cause
these timings to vary nominally. It is recommended that designers add a small margin to avoid possible corner-case conditions.
- The Write Wait States register (SWAITWR x) must be set to a minimum value of 3.
- For each rising clock edge (HCLK) that the assertion of nWAIT lags the assertion of nCSx, another write wait state (SWAITRDx) must be
added to the minimum requirement.
- nWAIT delay cycles are not added for all nWAIT assertions sampled prior to WST-3. These nWAIT assertions are ignored.
- nWAIT delay cycles are added for all nWAI T assertions sampled from WST-3 until the de-assertion of nWAIT. nWAIT delay cycles are added
once the wait state countdown has reached WST-1.
- Once nWAIT is sampled high, the current memory transaction is queued to complete.
- Since static and dynamic memo ry cannot be accessed at the same time, any pr olonged access (either due to nWAIT or the Extende d Wait
Register) that causes an SDRAM refresh failure may cause SDRAM data to be lost.
- Timing assumes Write Enable Delay regi ster (SWAITWENx) is programmed to 0.
Figure 14. nWAIT Write Sequence (SWAITWRx = 3) Table 17. nWAIT Write Sequence Parameter Definitions
Figure 17. External Static Memory Read, Zero Wait States
Figure 20. External Static Memory Write with Two Wait States
Figure 22. SDRAM Bank Activate and Write
- SDRAMcmd is the combination of nRAS, nCAS, nSDWE, and nSDCS(X).
- tOVXXX represents tOVRA, tOVCA, tOVSDW, or tOVSC. Refer to the AC timing table.
- tOHXXX represents tOHRA, tOHCA, tOHSDW, or tOHSC.
Figure 27. Write, Memory-to-Peripheral: Burst Size = 4; Destination Width > External Access Width NOTE: * HCLK is an internal signal, provided for reference only.
Figure 28. STN Horizontal Timing
- Signal polarties may vary for some displays.
- See 'STN horizontal timing' diagram.
- LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period.
Figure 29. STN Vertical Timing
- Signal polarties may vary for some displays.
- See 'STN horizontal timing' diagram.
- LCDFP with TIMING1:VSW = 0 is only a single horizontal ine period.
Figure 30. TFT Horizontal Timing
- Signal polarties may vary for some displays.
- The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels.
Figure 31. TFT Vertical Timing
- Signal polarties may vary for some displays.
- The use of LCDDSPLEN for high-voltage power control is optional on some TFT panels.
Figure 32. AD-TFT, HR-TFT Horizontal Timing Figure 33. AD-TFT, HR-TFT Vertical Timing
1 AD-TFT or HR-TFT HORIZONTAL LINE
1 LCDDCLK
NOTE: LCDDCLK can range from 4.5 MHz to 6.8 MHz.
The SSP timing is illustrated in Figure 34. Figure 34. Synchronous Serial Port Waveform
Figure 40. Suggested External Components, 10 MHz to 20 MHz Oscillator
- Y1 is a parallel-resonant type crystal. (See table)
- The nominal values for C1 and C2 shown are for
a crystal specified at 18 pF load capacitance (CL).
- The values for C1 and C2 are dependent upon
- R1 must be in the circuit.
- Ground connections should be short and return
processor's core ground pins.
- Tolerance for R1, C1, C2 is ≤ 5%.
11.2896 MHz Crystal
Figure 41. Package outline SOT1017-1 (LQFP176)
- Plastic or metal protrusions of 0.25 mm maximum per side are not included.
Figure 42. Package outline SOT1019-1 (LFBGA208)
LH79524/LH79525 System-on-Chip 60 Rev. 01 — 16 July 2007 Preliminary data sheet NXP Semiconductors
REVISION HISTORY
Table 19. Revision history
- First NXP version based on the LH79524/LH79525 data sheet of 20060929
© NXP B.V. 2007. All rights reserved. System-on-Chip LH79524/LH79525 9. Legal information
9.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design. [2] The term ‘short data sheet’ is explained in section “Definitions”. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL http://www.nxp.com
9.2 Definitions
Draft — The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet — A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail.
9.3 Disclaimers
General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail. No offer to sell or license — Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights.
9.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 10. Contact information For additional information, please visit: http://www.nxp.com For sales office addresses, send an email to: salesaddresses@nxp.com Document status[1][2] Product status[3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This docum ent contains the product specification.
Dear customer, As from June 1st, 2007 NXP Semiconductors has acquired the LH7xxx ARM Microcontrollers from Sharp Microelectronics. The following changes are applicable to the attached data sheet. In data sheets where the previous Sharp or Sharp Corporation references remain, please use the new links as shown below. For www.sharpsma.com use www.nxp.com/microcontrollers for indicated sales addresses use salesaddresses@nxp.com (email) The copyright notice at the bottom of each page (or elsewhere in the document, depending on the version) - Copyright © (year) by SHARP Corporation. is replaced with: - © NXP B.V. (year). All rights reserved. If you have any questions related to the data sheet, please contact our nearest sales office via e-mail or phone (details via salesaddresses@nxp.com). Thank you for your cooperation and understanding, In addition to that the Annex A (attached hereto) is added to the document. NXP Semiconductors
ANNEX A: Disclaimers (11) 1. t001dis100.fm: General (DS, AN, UM) General — Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. 2. t001dis101.fm: Right to make changes (DS, AN, UM) Right to make changes — NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. 3. t001dis102.fm: Suitability for use (DS, AN, UM) Suitability for use — NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of a NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer’s own risk. 4. t001dis103.fm: Applications (DS, AN, UM) Applications — Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. 5. t001dis104.fm: Limiting values (DS) Limiting values — Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) may cause permanent damage to the device. Limiting values are stress ratings only and operation of the device at these or any other conditions above those given in the Characteristics sections of this document is not implied. Exposure to limiting values for extended periods may affect device reliability. 6. t001dis105.fm: Terms and conditions of sale (DS) Terms and conditions of sale — NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms, including those pertaining to warranty, intellectual property rights infringement and limitation of liability, unless explicitly otherwise agreed to in writing by NXP Semiconductors. In case of any inconsistency or conflict between information in this document and such terms and conditions, the latter will prevail.
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