F00073_15 SSDI
Document overview
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Technical content
SSDIl PRELIMINARY : SFF340-28 SS i SOLID STATE DEVICES, INC
14849 Firestone Boulevard: La Mirada,CA 90638
Phone: (714) 670:S80I (7734) ax: (718) 822-7424 10 AMP Designer’s Data Sheet 400 VOLTS FEATURES: N-CHANNEL POWER MOSFET . Rugged construction with poly silicon gate @ Low DS(on) and high transconductance 28 PIN CLCC = Excellent high temperature stability ® Very fast switching speed = Fast recovery and superior dv/dt performance = Increased reverse energy capability = Low input and transfer capacitance for easy paralleling = Hermetically sealed surface mount package mw TX, TXV and space Level screening available ™ Replaces: IRF340 Types MAXIMUM RATINGS CHARACTERISTIC symeo. | value | uN _ Operating and Storage Temperature -55 to +150 c Total Device Dissipation @ TC=25'°C 36 Total Device Dissipation @ TC=80°C 27 PACKAGE OUTLINE: 28 PIN CLCC 0.030 TYP. DRAIN: 5-11 GATE: 2, 3, 13, 14 _f 0030 NOTE: 0.450 +/--008 Sa. 0.300 rT oa00 All Drain/Source Pins must be connected on the PC Board in order to maximize 4 L current capabilit 0.035 and minimize RBS(on) ahaa 00s AR mt amo TP. (020 x 45 CHAM 1 PLC * Rating based on size of chip. Device rating may vary Gepending on mounting and heatsink conditions. Consult SSDI Marketing department for thermal derating details. NOTE: All ificati b h SSDI prior to release.
PRELIMINARY SSDI| SOLID STATE DEVICES, INC Phone: (714) 670-SSDI (7734) Fax: (714) 522-7424 ELECTRICAL CHARACTERISTICS @ Ts=25 C (Unless Otherwise Specified) [RATING spon] on [rye | max | unr Drain to Source Breakdown Voltage (VGS=0 V, ID=250nA) BVoss Drain to Source on State Resistance (VGS=10 V, ID=60% Rated ID Rosvon) On State Drain Current (VDS >ID(on) X RDS(on) Max, VGS=10 V Gate Threshold Voltage (VDS=VGS, ID=250,1A) VGS(th) Forward Transconductance (VDS = 50V, IDS=60% rated ID) 8.7 Zero Gate Voltage Drain Current (pgm rated voltage, VGS=0 Y) 250 pA VDS=80% rated VDS, VGS=0 V, TA=125°C) 1000 Gate to Source Leakage Forward| At rated VGS 100 Gate to Source Leakage Reverse Icss -100 Total Gate Charge VGS=10 Volts Qg 43 65 Gate to Source Sharge 80% rated VDS Qgs 6 9.3 Gate to Drain Charge = Qgd 22 33 Turn on Delay Time voDsEre ta(on) 4 EA Rise Time . ID=10A tr 50 74 Turn Off Delay Time RG=9.10 td(off) Fall Time AD=200 tt 24 36 Diode Forward Voltage Vsp (IS=rated ID, VGS=0 V, Tu=25°C) T=25°C 170 370 790 Diode Reverse Recovery Time a nsec Reverse Recovery Charge didtctGh Wirsec ra 1.6 3.8 8.2 uc Input Capacitance VGS-=0 Volts Ciss 1300 Output Capacitance VDS=25 Volts Coss 210 Reverse Transfer Capacitance f= 1 MHz Crss 37 SAFE OPERATING AREA (S.0.A.) ‘Te = 25 C, D.C. CONDI NOTES: SSS SSS ae Se ESS * Rating based on sizeof chip, Device > ing may va ing on mou an ES and Reatsink conditions. ‘Consult SSDI sese etimeeen See Marketing department for thermal 3 SS derating details. # os facade ele LL “Due to package resistance; all ase eet nett eeiiit Source/Drain Pins must be connected
80 Ti onthe ‘oard in order to obtain the
oo LA -TT towest RDS(on) possible, 0.1 1 10 100 1000 ‘RAN TO SOURCE VOLTAGE (vs)