STM8S003F3_V01 STMICROELECTRONICS
Document overview
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Technical content
Datasheet sections
- 1 Introduction
- 2 Description
- 3 Block diagram
- 4 Product overview
- 4.1 Central processing unit STM8
- 4.2 Single wire interface module (SWIM) and debug module (DM)
- 4.3 Interrupt controller
- 4.4 Flash program memory and data EEPROM
- 4.5 Clock controller
- 4.6 Power management
- 4.7 Watchdog timers
- 4.8 Auto wakeup counter
- 4.9 Beeper
- 4.10 TIM1 - 16-bit advanced control timer
- 4.11 TIM2 - 16-bit general purpose timer
- 4.12 TIM4 - 8-bit basic timer
- 4.13 Analog-to-digital converter (ADC1)
- 4.14 Communication interfaces
- 4.14.1 UART1
- 4.14.2 SPI
- 4.14.3 I 2C
- 5 Pinouts and pin descriptions
- 5.1 STM8S003K3 LQFP32 pinout and pin description
- 5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin description
- 5.3 Alternate function remapping
- 6 Memory and register map
- 6.1 Memory map
- 6.2 Register map
Datasheet sections
- 11 Ordering information
- 12 STM8 development tools
- 12.1 Emulation and in-circuit debugging tools
- 12.2 Software tools
- 12.2.1 STM8 toolset
- 12.2.2 C and assembly toolchains
- 12.3 Programming tools
- 13 Revision history
Features
- 16 MHz advanced STM8 core with Harvard architecture and 3-stage pipeline
- Extended instruction set Memories
- Program memory: 8 Kbyte Flash memory; data retention 20 years at 55 °C after 100 cycles
- RAM: 1 Kbyte
- Data memory: 128 bytes true data EEPROM; endurance up to 100 k write/erase cycles Clock, reset and supply management
- 2.95 V to 5.5 V operating voltage
- Flexible clock control, 4 master clock sources – Low-power crystal resonator oscillator – External clock input – Internal, user-trimmable 16 MHz RC – Internal low-po wer 128 kHz RC
- Clock security system with clock monitor
- Power management – Low-power modes (wait, active-halt, halt) – Switch-off peripheral clocks individually – Permanently active, low-consumption power-on and power-down reset Interrupt management
- Nested interrupt controller with 32 interrupts
- Up to 27 external interrupts on 6 vectors Timers
- Advanced control timer: 16-bit, 4 CAPCOM channels, 3 complementary outputs, dead-time insertion and flexible synchronization
- 16-bit general purpose timer, with 3 CAPCOM channels (IC, OC or PWM)
- 8-bit basic timer with 8-bit prescaler
- Auto wakeup timer
- Window and independent watchdog timers Communications interfaces
- UART with clock output for synchronous operation, SmartCard, IrDA, LIN master mode
- SPI interface up to 8 Mbit/s
- I2C interface up to 400 Kbit/s Analog to digital converter (ADC)
- 10-bit ADC, ± 1 LSB ADC with up to 5 multiplexed channels, scan mode and analog watchdog I/Os
- Up to 28 I/Os on a 32-pin package including 21 high-sink outputs
- Highly robust I/O design, immune against current injection Development support
- Embedded single-wire interface module (SWIM) for fast on-chip programming and non- intrusive debugging LQFP32 7x7 mm TSSOP20 6.5x6.4 mm UFQFPN20 3x3 mm
STM8S003F3 STM8S003K3 Contents 9.3.9 I
Table 21. Total current consumption wit h code execution in run mode at V
Table 53. TSSOP20 – 20-lead thin shrink sm all outline, 6.5 x 4.4 mm, 0.65 mm pitch, Table 54. UFQFPN20 - 20-lead, 3 x3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
STM8S003F3 STM8S003K3 Introduction
1 Introduction
This datasheet contains the description of the STM8S003F3/K3 value line features, pinout, electrical characteristics, mechanical data and ordering information.
- For complete information on the STM8S microcontroller memory, registers and peripherals, please refer to the STM8S and STM8A microcontroller families reference manual (RM0016).
- For information on programming, erasing and protection of the internal Flash memory please refer to the PM0051 (How to program STM8S and STM8A Flash program memory and data EEPROM).
- For information on the debug and SWIM (single wire interface module) refer to the STM8 SWIM communication protocol and debug module user manual (UM0470).
- For information on the STM8 core, please refer to the STM8 CPU programming manual (PM0044).
2 Description
the STM8S microcontroller family reference manual (RM0016). robustness and reduced system cost. clock source, and a clock security system. oscillators, watchdog, and brown-out reset. Full documentation is offered as well as a wide choice of development tools. Table 1. STM8S003F3/K3 value line features
- Without read-while-write capability.
3 Block diagram
Figure 1. STM8S003F3/K3 value line block diagram
400 Kbit/s
8 Kbyte
1 Kbyte RAM
4 CAPCOM
3 CAPCOM
Product overview STM8S003F3 STM8S003K3 12/103 DS7147 Rev 10
4 Product overview
The following section intends to give an overview of the basic features of the STM8S003F3/K3 value line functional modules and peripherals. For more detailed information please refer to the corresponding family reference manual (RM0016).
4.1 Central proc essing unit STM8
The 8-bit STM8 core is designed for code efficiency and performance. It contains six internal registers which are directly addressable in each execution context, 20 addressing modes including indexed indirect and relative addressing and 80 instructions. Architecture and registers
- Harvard architecture
- 3-stage pipeline
- 32-bit wide program memory bus - single cycle fetching for most instructions
- X and Y 16-bit index registers - enabling indexed addressing modes with or without offset and read-modify-write type data manipulations
- 8-bit accumulator
- 24-bit program counter - 16-Mbyte linear memory space
- 16-bit stack pointer - access to a 64 K-level stack
- 8-bit condition code register - 7 condition flags for the result of the last instruction Addressing
- 20 addressing modes
- Indexed indirect addressing mode for look-up tables located anywhere in the address space
- Stack pointer relative addressing mode for local variables and parameter passing Instruction set
- 80 instructions with 2-byte average instruction size
- Standard data movement and logic/arithmetic functions
- 8-bit by 8-bit multiplication
- 16-bit by 8-bit and 16-bit by 16-bit division
- Bit manipulation
- Data transfer between stack and accumulator (push/pop) with direct stack access
- Data transfer using the X and Y registers or direct memory-to-memory transfers
STM8S003F3 STM8S003K3 Product overview
4.2 Single wire interface module (SWIM) and debug module (DM)
The single wire interface module and debug module permits non-intrusive, real-time in- circuit debugging and fast memory programming. SWIM Single wire interface module for direct access to the debug module and memory programming. The interface can be activated in all device operation modes. The maximum data transmission speed is 145 byte/ms. Debug module The non-intrusive debugging module features a performance close to a full-featured emulator. Beside memory and peripherals, also CPU operation can be monitored in real- time by means of shadow registers.
- R/W to RAM and peripheral registers in real-time
- R/W access to all resources by stalling the CPU
- Breakpoints on all program-memory instructions (software breakpoints)
- Two advanced breakpoints, 23 predefined configurations
4.3 Interrupt controller
- Nested interrupts with three software priority levels
- 32 interrupt vectors with hardware priority
- Up to 27 external interrupts on six vectors including TLI
- Trap and reset interrupts
4.4 Flash program me mory and data EEPROM
- 8 Kbyte of Flash program single voltage Flash memory
- 128 byte true data EEPROM
- User option byte area Write protection (WP) Write protection of Flash program memory and data EEPROM is provided to avoid unintentional overwriting of memory that could result from a user software malfunction. There are two levels of write protection. The first level is known as MASS (memory access security system). MASS is always enabled and protects the main Flash program memory, data EEPROM and option bytes. To perform in-application programming (IAP), this write protection can be removed by writing a MASS key sequence in a control register. This allows the application to modify the content of main program memory and data EEPROM, or to reprogram the device option bytes. A second level of write protection, can be enabled to further protect a specific area of memory known as UBC (user boot code). Refer to Figure 2.
of 1 page (64-byte block) by programming the UBC option byte in ICP mode.
- Main program memory: 8 Kbyte minus UBC
- User-specific boot code (UBC): Configurable up to 8 Kbyte The UBC area remains write-protected during in-application programming. This means that the MASS keys do not unlock the UBC area. It protects the memory used to store the boot program, specific code libraries, reset and interrupt vectors, the reset routine and usually the IAP and communication routines.
Figure 2. Flash memory organization activated, any attempt to toggle its status triggers a global erase of the program memory. high level of protection for a general purpose microcontroller.
8 Kbytes
STM8S003F3 STM8S003K3 Product overview
4.5 Clock controller
The clock controller distributes the system clock (fMASTER) coming from different oscillators to the core and the peripherals. It also manages clock gating for low power modes and ensures clock robustness.
- Clock prescaler: To get the best compromise between speed and current consumption the clock frequency to the CPU and peripherals can be adjusted by a programmable prescaler.
- Safe clock switching: Clock sources can be changed safely on the fly in run mode through a configuration register. The clock signal is not switched until the new clock source is ready. The design guarantees glitch-free switching.
- Clock management: To reduce power consumption, the clock controller can stop the clock to the core, individual peripherals or memory.
- Master clock sources: Four different clock sources can be used to drive the master clock: – 1-16 MHz high-speed external crystal (HSE) – Up to 16 MHz high-speed user-external clock (HSE user-ext) – 16 MHz high-speed internal RC oscillator (HSI) – 128 kHz low-speed internal RC (LSI)
- Startup clock: After reset, the microcontroller restarts by default with an internal 2 MHz clock (HSI/8). The prescaler ratio and clock source can be changed by the application program as soon as the code execution starts.
- Clock security system (CSS): This feature can be enabled by software. If an HSE clock failure occurs, the internal RC (16 MHz/8) is automatically selected by the CSS and an interrupt can optionally be generated.
- Configurable main clock output (CCO): This outputs an external clock for use by the application.
Table 2. Peripheral clock gating bit assignments in CLK_PCKENR1/2 registers
Product overview STM8S003F3 STM8S003K3 16/103 DS7147 Rev 10
4.6 Power management
For efficient power management, the application can be put in one of four different low- power modes. You can configure each mode to obtain the best compromise between the lowest power consumption, the fastest start-up time and available wakeup sources.
- Wait mode: In this mode, the CPU is stopped, but peripherals are kept running. The wakeup is performed by an internal or external interrupt or reset.
- Active halt mode with regulator on: In this mode, the CPU and peripheral clocks are stopped. An internal wakeup is generated at programmable intervals by the auto wake up unit (AWU). The main voltage regulator is kept powered on, so current consumption is higher than in active halt mode with regulator off, but the wakeup time is faster. Wakeup is triggered by the internal AWU interrupt, external interrupt or reset.
- Active halt mode with regulator off: This mode is the same as active halt with regulator on, except that the main voltage regulator is powered off, so the wake up time is slower.
- Halt mode: In this mode the microcontroller uses the least power. The CPU and peripheral clocks are stopped, the main voltage regulator is powered off. Wakeup is triggered by external event or reset.
4.7 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to the applications. Activation of the watchdog timers is controlled by option bytes or by software. Once activated, the watchdogs cannot be disabled by the user program without performing a reset. Window watchdog timer The window watchdog is used to detect the occurrence of a software fault, usually generated by external interferences or by unexpected logical conditions, which cause the application program to abandon its normal sequence. The window function can be used to trim the watchdog behavior to match the application perfectly. The application software must refresh the counter before time-out and during a limited time window. A reset is generated in two situations: 1. Timeout: at 16 MHz CPU clock the time-out period can be adjusted between 75 µs up to 64 ms. 2. Refresh out of window: the down-counter is refreshed before its value is lower than the one stored in the window register.
STM8S003F3 STM8S003K3 Product overview Independent watchdog timer The independent watchdog peripheral can be used to resolve processor malfunctions due to hardware or software failures. It is clocked by the 128 kHz LSI internal RC clock source, and thus stays active even in case of a CPU clock failure The IWDG time base spans from 60 µs to 1 s.
4.8 Auto wakeup counter
- Used for auto wakeup from active halt mode
- Clock source: internal 128 kHz internal low frequency RC oscillator or external clock
- LSI clock can be internally connected to TIM1 input capture channel 1 for calibration
4.9 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in the range of 1, 2 or 4 kHz. The beeper output port is only available through the alternate function remap option bit AFR7.
4.10 TIM1 - 16-bit advanced control timer
This is a high-end timer designed for a wide range of control applications. With its complementary outputs, dead-time control and center-aligned PWM capability, the field of applications is extended to motor control, lighting and half-bridge driver.
- 16-bit up, down and up/down autoreload counter with 16-bit prescaler
- Four independent capture/compare channels (CAPCOM) configurable as input capture, output compare, PWM generation (edge and center aligned mode) and single pulse mode output
- Synchronization module to control the timer with external signals
- Break input to force the timer outputs into a defined state
- Three complementary outputs with adjustable dead time
- Encoder mode
- Interrupt sources: 3 x input capture/output compare, 1 x overflow/update, 1 x break
4.11 TIM2 - 16-bit ge neral purpose timer
- 16-bit autoreload (AR) up-counter
- 15-bit prescaler adjustable to fixed power of 2 ratios 1…32768
- 3 individually configurable capture/compare channels
- PWM mode
- Interrupt sources: 3 x input capture/output compare, 1 x overflow/update
4.12 TIM4 - 8-bit basic timer
- 8-bit autoreload, adjustable prescaler ratio to any power of 2 from 1 to 128
- Clock source: CPU clock
- Interrupt source: 1 x overflow/update
4.13 Analog-to-digital converter (ADC1)
- Input voltage range: 0 to VDDA
- Conversion time: 14 clock cycles
- Single and continuous, buffered continuous conversion modes
- Buffer size (10 x 10 bits)
- Scan mode for single and continuous conversion of a sequence of channels
- Analog watchdog capability with programmable upper and lower thresholds
- Analog watchdog interrupt
- External trigger input
- Trigger from TIM1 TRGO
- End of conversion (EOC) interrupt Note: Additional AIN12 analog inpu t is not selectable in ADC scan mode or with analog watchdog. Values converted from AIN12 are stored only into the ADC_DRH/ADC_DRL registers.
4.14 Communication interfaces
- UART1: full feature UART, synchronous mode, SPI master mode, SmartCard mode, IrDA mode, LIN2.1 master capability
- SPI: full and half-duplex, 8 Mbit/s
- I²C: up to 400 Kbit/s
Table 3. TIM timer features
STM8S003F3 STM8S003K3 Product overview
4.14.1 UART1
- 1 Mbit/s full duplex SCI
- SPI emulation
- High precision baud rate generator
- Smartcard emulation
- IrDA SIR encoder decoder
- LIN master mode
- Single wire half duplex mode Asynchronous communication (UART mode)
- Full duplex communication - NRZ standard format (mark/space)
- Programmable transmit and receive baud rates up to 1 Mbit/s (fCPU/16) and capable of following any standard baud rate regardless of the input frequency
- Separate enable bits for transmitter and receiver
- Two receiver wakeup modes: – Address bit (MSB) – Idle line (interrupt)
- Transmission error detection with interrupt generation
- Parity control Synchronous communication
- Full duplex synchronous transfers
- SPI master operation
- 8-bit data communication
- Maximum speed: 1 Mbit/s at 16 MHz (fCPU/16) LIN master mode
- Emission: generates 13-bit synch. break frame
- Reception: detects 11-bit break frame
4.14.2 SPI
- Maximum speed: 8 Mbit/s (fMASTER/2) both for master and slave
- Full duplex synchronous transfers
- Simplex synchronous transfers on two lines with a possible bidirectional data line
- Master or slave operation - selectable by hardware or software
- CRC calculation
- 1 byte Tx and Rx buffer
- Slave/master selection input pin
Product overview STM8S003F3 STM8S003K3 20/103 DS7147 Rev 10
4.14.3 I 2C
- I2C master features – Clock generation – Start and stop generation
- I 2C slave features – Programmable I 2C address detection – Stop bit detection
- Generation and detection of 7-bit/10-bit addressing and general call
- Supports different communication speeds – Standard speed (up to 100 kHz) – Fast speed (up to 400 kHz)
5 Pinouts and pin descriptions
Table 4. Legend/abbreviations for STM8S003F3/K3 pin description tables and after the internal reset release.
5.1 STM8S003K3 LQFP32 pino ut and pin description
Figure 3. STM8S003K3 LQFP32 pinout Table 5. STM8S003K3 descriptions
1 NRST I/O - X - - - - - Reset -
2 PA1/OSCIN (2) I/O X XX- O 1 X X Port A1 Resonator/
3 PA2/OSCOUT I/O X XX- O 1 X X Port A2 Resonator/
7 PA3/TIM2_CH3
9 PB7 I/O X X-- O 1 X X Port B7 --
10 PB6 I/O X X-- O 1 X X Port B6 --
11 PB5/I 2C_SDA I/O X -X- O 1 T (3) - Port B5 I2C data -
12 PB4/I 2C_SCL I/O X -X- O 1 T (3) - Port B4 I2C clock -
13 PB3/AIN3
14 PB2/AIN2
15 PB1/AIN1
16 PB0/AIN0
17 PE5/SPI_NSS I/O X
18 PC1/TIM1_CH1/
19 PC2/TIM1_CH2 I/O X XX H S O 3 X X Port C2 Timer 1-
20 PC3/TIM1_CH3 I/O X XX H S O 3 X X Port C3 Timer 1 -
Table 5. STM8S003K3 descriptions (continued)
21 PC4/TIM1_CH4/C
22 PC5/SPI_SCK I/O X
23 PC6/SPI_MOSI I/O X XX H S O 3 X X Port C6 SPI master
24 PC7/SPI_MISO I/O X XX H S O 3 X X Port C7 SPI master in/
25 PD0/[TIM1_BKIN
26 PD1/SWIM
27 PD2
28 PD3/TIM2_CH2
29 PD4/BEEP/
30 PD5/ UART1_TX I/O X XX H S O 3 X X Port D5 UART1 data
31 PD6/ UART1_RX I/O X XX H S O 3 X X Port D6 UART1 data
32 PD7/TLI
- I/O pins used simultaneously for hi gh-current source/sink must be uniformly spaced around the package. In
- When the MCU is in Halt/Active-halt mode, PA1 is automatically configured in input weak pull-up and
recommended to use PA1 only in input mode if Halt/Active-halt is used in the application.
- In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection
diode to VDD are not implemented).
- The PD1 pin is in input pull-up during the re set phase and after the internal reset release.
STM8S003F3 STM8S003K3 Pinouts and pin descriptions
5.2 STM8S003F3 TSSOP20/UFQFPN20 pinout and pin
description
Figure 4. STM8S003F3 TSSOP20 pinout
- (T) True open drain (P-buffer and prot ection diode to VDD not implemented).
- [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
Figure 5. STM8S003F3 UFQFPN20 pinout
- (T) True open drain (P-buffer and prot ection diode to VDD not implemented).
- [ ] alternate function remapping option (If the same alternate function is shown twice, it indicates an
exclusive choice not a duplication of the function).
Table 6. STM8S003F3 pin description
- I/O pins used simultaneously for high cu rrent source/sink must be uniformly spaced around the package. In addition, the
total driven current must respect the absolute maximum ratings.
- When the MCU is in halt/active-halt mode, PA1 is automatic ally configured in input weak pull-up and cannot be used for
if halt/active-halt is used in the application.
- In the open-drain output column, "T" defines a true open-drain I/O (P-buffer, weak pull-up, and protection diode to VDD are
- The PD1 pin is in input pull-up during the reset phase and after internal reset release.
Table 6. STM8S003F3 pin description (continued)
STM8S003F3 STM8S003K3 Pinouts and pin descriptions
5.3 Alternate func tion remapping
As shown in the rightmost column of the pin description table, some alternate functions can be remapped at different I/O ports by programming one of eight AFR (alternate function remap) option bits. Refer to Section 8: Option bytes. When the remapping option is active, the default alternate function is no longer available. To use an alternate function, the corresponding peripheral must be enabled in the peripheral registers. Alternate function remapping does not effect GPIO capabilities of the I/O ports (see the GPIO section of the family reference manual, RM0016).
6 Memory and register map
6.1 Memory map
Figure 6. Memory map
RAM end address in each case.
6.2 Register map
6.2.1 I/O port hardware register map
Table 7. Flash, Data EEPROM and RAM boundary addresses Table 8. I/O port hardware register map
6.2.2 General hardwa re register map
- Depends on the external circuitry.
Table 8. I/O port hardware register map (continued)
Table 9. General hardware register map
Table 9. General hardware register map (continued)
- Depends on the previous reset source.
6.2.3 CPU/SWIM/debug module/in terrupt controller registers
Table 10. CPU/SWIM/debug module/interrupt controller registers
- Accessible by debug module only
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
7 Interrupt vector mapping
Table 11. Interrupt mapping
0 TLI External top level interrupt - - 0x00 8008
1 AWU Auto wake up from halt - Yes 0x00 800C
2 CLK Clock controller - - 0x00 8010
3 EXTI0 Port A external interrupts Yes
4 EXTI1 Port B external interrupts Yes Yes 0x00 8018
5 EXTI2 Port C external interrupts Yes Yes 0x00 801C
6 EXTI3 Port D external interrupts Yes Yes 0x00 8020
7 EXTI4 Port E external interrupts Yes Yes 0x00 8024
10 SPI End of transfer Yes Yes 0x00 8030
11 TIM1 TIM1 update/overflow/underflow/
12 TIM1 TIM1 capture/compare - - 0x00 8038
13 TIM2 TIM2 update /overflow - - 0x00 803C
14 TIM2 TIM2 capture/compare - - 0x00 8040
17 UART1 Tx complete - - 0x00 804C
18 UART1 Receive register DATA FULL - - 0x00 8050
22 ADC1 ADC1 end of conversion/analog
23 TIM4 TIM4 update/overflow - - 0x00 8064
24 Flash EOP/WR_PG_DIS - - 0x00 8068
8 Option bytes
(OPTx) and a complemented one (NOPTx) for redundancy. Table 12. Option bytes Table 13. Option byte description Flash/EEPROM memory readout protection for details.
Page 0 and page 1 contain the interrupt vectors. Other values: Pages 0 to 127 defined as UBC, memory-write protected. Flash/EEPROM write protection for more details. of bits [7:2] and [1:0] respectively. This configures the stabilization time. Table 13. Option byte description (continued)
8.1 Alternate functi on remapping bits
Table 14. STM8S003K3 alternate function remapping bits for 32-pin devices
- Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
1: Port D7 alternate function = TIM1_CH4. 1: Port D0 alternate function = CLK_CCO.
- Refer to the pinout description.
Table 15. STM8S003F3 alternate function remapping bits for 20-pin devices 0: AFR4 remapping option inactive: default alternate function(1). 1: Port C3 alternate function = TLI. TIM1_CH1; port C7 alternate function = TIM1_CH2.
- Refer to the pinout description.
- Do not use more than one remapping option in the same port. It is forbidden to enable both AFR1 and
9 Electrical characteristics
9.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
9.1.1 Minimum and maximum values
the selected temperature range).
9.1.2 Typical values
only as design guidelines and are not tested. error less than or equal to the value indicated (mean ± 2 Σ).
9.1.3 Typical curves
9.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 7. Figure 7. Pin loading conditions
9.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 8.
Figure 8. Pin input voltage
9.2 Absolute maximum ratings
extended periods may affect the device’s reliability. Qualification Standard, extended mission profiles are available on demand. Table 16. Voltage characteristics
- All power (V DD) and ground (VSS) pins must always be connected to the external power supply
- I INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
Table 17. Current characteristics
- Data based on characterization results.
- All power (V DD) and ground (VSS) pins must always be connected to the external supply.
- I INJ(PIN) must never be exceeded. This is implicitly insured if VIN maximum is respected. If VIN maximum
- ADC accuracy vs. negative injection current: Inje cting negative current on any of the analog input pins
ΣIINJ(PIN) in the I/O port pin characteristics section does not affect the ADC accuracy.
- When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
with ΣIINJ(PIN) maximum current injection on four I/O port pins of the device. Table 18. Thermal characteristics
9.3 Operating conditions
addition, full account must be taken of all physical capacitor characteristics and tolerances. Figure 9. fCPUmax versus VDD Table 19. General operating conditions
- Care should be taken when selecting the capacitor, due to its tolerance, as well as the parameter
values must be respected for the full application range.
- This frequency of 1 MHz as a condition for V CAP parameters is given by the design of the internal regulator.
- To calculate P Dmax(TA), use the formula PDmax = (TJmax - TA)/ΘJA (see Section 10.4: Thermal
Table 55: Thermal characteristics.
Table 20. Operating conditions at power-up/power-down
- Reset is always generated after a t TEMP delay. The application must ensure that VDD is still above the
minimum operating voltage (VDD min) when the tTEMP delay has elapsed.
9.3.1 VCAP external capacitor
Figure 10. External capacitor CEXT
- Legend: ESR is the equivalent series resist ance and ESL is the equivalent inductance.
9.3.2 Supply current characteristics
The current consumption is measured as described in Section 9.1.5: Pin input voltage.
- All I/O pins in input mode with a static value at VDD or VSS (no load)
- All peripherals are disabled (clock stopped by Peripheral Clock Gating registers) except if explicitly mentioned. Subject to general operating conditions for VDD and TA. MSv36488V1 ESR RLeak ESLC
Table 21. Total current consumption with code execution in run mode at VDD = 5 V
- Data based on characterization results.
- Default clock configuration m easured with all peripherals off.
Table 22. Total current consumption with code execution in run mode at VDD = 3.3 V
- Data based on characterization results.
- Default clock configuration, measured with all peripherals off.
Table 23. Total current consumption in wait mode at VDD = 5 V
- Data based on characterization results.
- Default clock configuration m easured with all peripherals off.
Table 24. Total current consumption in wait mode at VDD = 3.3 V
- Data based on characterization results.
- Default clock configuration m easured with all peripherals off.
Table 25. Total current consumption in active halt mode at VDD = 5 V
- Data based on characterization results.
- Configured by the REGAH bit in the CLK_ICKR register.
- Configured by the AHALT bit in the FLASH_CR1 register.
Table 26. Total current consumption in active halt mode at VDD = 3.3 V
- Data based on characterization results.
- Configured by the REGAH bit in the CLK_ICKR register.
- Configured by the AHALT bit in the FLASH_CR1 register.
Table 27. Total current consumption in halt mode at VDD = 5 V
- Data based on characterization results.
Table 28. Total current consumption in halt mode at VDD = 3.3 V
- Data based on characterization results.
Table 29. Wakeup times
- Data guaranteed by design.
- t WU(WFI) = 2 x 1/fmaster + 7 x 1/fCPU
- Measured from interrupt event to interrupt vector fetch.
- Configured by the REGAH bit in the CLK_ICKR register.
- Configured by the AHALT bit in the FLASH_CR1 register.
- Plus 1 LSI clock depending on synchronization.
Subject to general operating conditions for VDD and TA. HSI internal RC/fCPU = fMASTER = 16 MHz, VDD = 5 V. Table 30. Total current consumption and timing in forced reset state
- Data guaranteed by design.
- Characterized with all I/Os tied to V SS.
Table 31. Peripheral current consumption
- Data based on a differential I DD measurement between reset configuration and timer counter running at
16 MHz. No IC/OC programmed (no I/O pads toggling). Not tested in production.
9.3.3 External clock sources and timing characteristics
Subject to general operating conditions for VDD and TA. Figure 17. HSE external clock source (frequency, package, accuracy...). Table 32. HSE user external clock characteristics
- Data based on characterization results.
Figure 18. HSE oscillator circuit diagram Table 33. HSE oscillator characteristics
- C is approximately equivalent to 2 x crystal Cload.
- The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
- Data based on characterization results.
reached. This value is measured for a standard crystal resonator and it can vary significantly with the crystal manufacturer.
9.3.4 Internal clock source s and timing characteristics
Subject to general operating conditions for VDD and TA. Table 34. HSI oscillator characteristics
- See the application note.
- Data based on characterization results.
9.3.5 Memory characteristics
General conditions: TA = -40 to 85 °C. Table 36. RAM and hardware registers
- Minimum supply voltage without losing data stored in RAM (in halt mode or under reset) or in hardware
registers (only in halt mode). Guaranteed by design.
- Refer to Table 20 on page 50 for the value of VIT-max.
Table 37. Flash program memory and data EEPROM
- Data based on characterization results.
- The physical granularity of the memory is 4 byte s, so cycling is performed on 4 bytes even when a
write/erase operation addresses a single byte.
9.3.6 I/O port pin characteristics
an external pull-up or pull-down resistor. Table 38. I/O static characteristics
- Hysteresis voltage between Schmitt trigger sw itching levels. Based on characterization results.
- Data guaranteed by design.
- Data based on characterization results.
Figure 23. Typical pull-up current vs VDD @ 4 temperatures
- The pull-up is a pure resistor (slope goes through 0).
Table 39. Output driving current (standard ports)
- Data based on characterization results.
Table 40. Output driving current (true open drain ports)
- Data based on characterization results.
Figure 33. Typ. VDD - VOH @ VDD = 3.3 V (high sink ports)
9.3.7 Reset pin characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. Figure 34. Typical NRST VIL and VIH vs VDD @ 4 temperatures Table 42. NRST pin characteristics
- Data based on characterization results.
- The R PU pull-up equivalent resistor is based on a resistive transistor.
- Data guaranteed by design.
Figure 37. Recommended reset pin protection
9.3.8 SPI serial peripheral interface
conditions. tMASTER = 1/fMASTER. characteristics (NSS, SCK, MOSI, MISO). Table 43. SPI characteristics
- Values based on design simulation and/or charac terization results, and not tested in production.
- Min time is for the minimum time to drive the output and t he max time is for the maximum time to validate the data.
Figure 40. SPI timing diagram - master mode(1)
- Measurement points are done at CMOS levels: 0.3 V DD and 0.7 VDD.
9.3.9 I 2C interface characteristics
Table 44. I2C characteristics
- f MASTER, must be at least 8 MHz to achieve max fast I2C speed (400kHz)
- Data based on standard I2C protocol requirement, not tested in production
- The maximum hold time of the start condition has only to be met if the interface does not stretch the low
- The device must internally provide a hold time of at least 300 ns for the SDA signal in order to bridge the
Figure 41. Typical application with I2C bus and timing diagram
- Measurement points are made at CMOS levels: 0.3 x VDD and 0.7 x VDD
Table 45. ADC characteristics
- During the sample time the input capacitance C AIN (3 pF max) can be charged/discharged by the external
the conversion result. Values for the sample clock tS depend on programming. Table 46. ADC accuracy with RAIN < 10 kΩ , VDD = 5 V
- Data based on characterization results.
- ADC accuracy vs. negative injection current: Inject ing negative current on any of the analog input pins
ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy. Table 47. ADC accuracy with RAIN < 10 kΩ RAIN, VDD = 3.3 V
- Data based on characterization results.
- ADC accuracy vs. negative injection current: Inject ing negative current on any of the analog input pins
ΣIINJ(PIN) in Section 9.3.6 does not affect the ADC accuracy.
9.3.11 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization. stressed by two electromagnetic events until a failure occurs (indicated by the LEDs).
- ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device until a functional disturbance occurs. This test conforms with the IEC 61000-4-2 standard.
- FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS through a 100 pF capacitor, until a functional disturbance occurs. This test conforms with the IEC 61000-4-4 standard. A device reset allows normal operations to be resumed. The test results are given in the table below based on the EMS levels and classes defined in application note AN1709. Designing hardened software to avoid noise problems EMC characterization and optimization are performed at component level with a typical application environment and simplified MCU software. It should be noted that good EMC performance is highly dependent on the user application and the software in particular. Therefore it is recommended that the user applies EMC software optimization and prequalification tests in relation with the EMC level requested for his application. Software recommendations The software flowchart must include the management of runaway conditions such as:
- Corrupted program counter
- Unexpected reset
- Critical data corruption (control registers...) Prequalification trials Most of the common failures (unexpected reset and program counter corruption) can be recovered by applying a low state on the NRST pin or the oscillator pins for 1 second. To complete these trials, ESD stress can be applied directly on the device, over the range of specification values. When unexpected behavior is detected, the software can be hardened to prevent unrecoverable errors occurring (see application note AN1015).
Table 48. EMS data
- Data obtained with HSI clock configuration, afte r applying HW recommendations described in AN2860 -
EMC guidelines for STM8Smicrocontrollers.
61967-2 standard for test software, board layout and pin loading. the product is stressed in order to determine its performance in terms of electrical sensitivity. For more details, refer to the application note AN1181. A114A/A115A standard. For more details, refer to the application note AN1181. Table 49. EMI data
- Data based on characterization results.
16 MHz/
8 MHz
16 MHz
0.1 MHz to 30 MHz 5 5
130 MHz to 1 GHz 5 5
Table 50. ESD absolute maximum ratings
- Data based on characterization results.
- A supply overvoltage (applied to each power supply pin)
- A current injection (applied to each input, output and configurable I/O pin) is performed on each sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details, refer to the application note AN1181.
Table 51. Electrical sensitivities
- Class description: A Class is an STMicr oelectronics internal specification. All its limits are higher than the
class strictly covers all the JEDEC criteria (international standard).
specifications, grade definitions and product status are available at www.st.com. ECOPACK® is an ST trademark.
10.1 LQFP32 package information
Figure 44. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package outline
Figure 45. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat recommended footprint
- Dimensions are expr essed in millimeters.
Table 52. LQFP32 - 32-pin, 7 x 7 mm low-profile quad flat package mechanical data
- Values in inches are converted from mm and rounded to 4 decimal digits.
chain operations, are not indicated below. Figure 46. LQFP32 marking example (package top view)
- Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
Samples to run qualification activity.
10.2 TSSOP20 package information
Figure 47. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch, Table 53. TSSOP20 – 20-lead thin shrink small outline, 6.5 x 4.4 mm, 0.65 mm pitch,
- Values in inches are converted fr om mm and rounded to four decimal digits.
- Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusions or gate burrs
shall not exceed 0.15mm per side.
- Dimension "E1" does not include interlead Flash or protrusions. Interlead Flash or protrusions shall not
10.3 UFQFPN20 package information
Figure 50. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
Figure 51. UFQFPN20 - 20-lead, 3 x 3 mm, 0.5 mm pitch, ultra thin fine pitch quad flat
- Dimensions are expr essed in millimeters.
- Values in inches are converted from mm and rounded to 4 decimal digits.
chain operations, are not indicated below. Figure 52. UFQFPN20 marking example (package top view)
- Parts marked as "ES", "E" or accompanied by an Engineering Sample notification letter, are not yet
Samples to run qualification activity.
10.4 Thermal characteristics
Table 19: General operating conditions.
- TAmax is the maximum ambient temperature in ° C
- Θ JA is the package junction-to-ambient thermal resistance in ° C/W
- PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
- PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip internal power.
- PI/Omax represents the maximum power dissipation on output pins, where: PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*IOH), and taking account of the actual VOL/IOL and VOH/IOH of the I/Os at low and high level in the application.
10.4.1 Reference document
convection (still air). Available from www.jedec.org. Table 55. Thermal characteristics(1)
- Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
10.4.2 Selecting the product temperature range
When ordering the microcontroller, the temperature range is specified in the order code (see Figure 53: STM8S003F3/K3 value line ordering information scheme(1)). The following example shows how to calculate the temperature range needed for a given application. Assuming the following application conditions:
- Maximum ambient temperature TAmax= 75 °C (measured according to JESD51-2)
- IDDmax = 8 mA, VDD = 5.0 V
- Maximum 20 I/Os used at the same time in output at low level with IOL = 8 mA, VOL= 0.4 V PINTmax = 8 mA x 5.0 V = 400 mW PDmax = 400 mW + 64 mW Thus: PDmax = 464 mW Using the values obtained in Section Table 55.: Thermal characteristics TJmax is calculated as follows for LQFP32 7 x 7 mm = 60 °C/W: TJmax = 75 °C + (60 °C/W x 464 mW) = 75 °C + 27.8 °C = 102.8 °C This is within the range of the suffix 6 version parts (-40 < TJ < 105 °C). In this case, parts must be ordered at least with the temperature range suffix 6.
Figure 53. STM8S003F3/K3 value line ordering information scheme(1)
- For a list of available options (e.g. memory size, package) and orderable part numbers or for further
- Refer to Table 1: STM8S003F3/K3 value line features for detailed description.
- TSSOP and UFQFPN packages.
STM8S003F3 STM8S003K3 ST M8 development tools 100
12 STM8 development tools
Development tools for the STM8 microcontrollers include the full-featured STice emulation system supported by a complete software tool package including C compiler, assembler and integrated development environment with high-level language debugger. In addition, the STM8 is to be supported by a complete range of tools including starter kits, evaluation boards and a low-cost in-circuit debugger/programmer.
12.1 Emulation and in-c ircuit debugging tools
The STice emulation system offers a complete range of emulation and in-circuit debugging features on a platform that is designed for versatility and cost-effectiveness. In addition, STM8 application development is supported by a low-cost in-circuit debugger/programmer. The STice is the fourth generation of full featured emulators from STMicroelectronics. It offers new advanced debugging capabilities including profiling and coverage to help detect and eliminate bottlenecks in application execution and dead code when fine tuning an application. In addition, STice offers in-circuit debugging and programming of STM8 microcontrollers via the STM8 single wire interface module (SWIM), which allows non-intrusive debugging of an application while it runs on the target microcontroller. For improved cost effectiveness, STice is based on a modular design that allows users to order exactly what they need to meet their development requirements and to adapt their emulation system to support existing and future ST microcontrollers. STice key features
- Occurrence and time profiling and code coverage (new features)
- Advanced breakpoints with up to 4 levels of conditions
- Data breakpoints
- Program and data trace recording up to 128 KB records
- Read/write on the fly of memory during emulation
- In-circuit debugging/programming via SWIM protocol
- 8-bit probe analyzer
- 1 input and 2 output triggers
- Power supply follower managing application voltages between 1.62 to 5.5 V
- Modularity that allows users to specify the components users need to meet their development requirements and adapt to future requirements
- Supported by free software tools that include integrated development environment (IDE), programming software interface and assembler for STM8.
STM8 development tools STM8S003F3 STM8S003K3 100/103 DS7147 Rev 10
12.2 Software tools
STM8 development tools are supported by a complete, free software package from STMicroelectronics that includes ST Visual Develop (STVD) IDE and the ST Visual Programmer (STVP) software interface. STVD provides seamless integration of the Cosmic and Raisonance C compilers for STM8. A free version that outputs up to 16 Kbytes of code is available.
12.2.1 STM8 toolset
STM8 toolset with STVD integrated development environment and STVP programming software is available for free download at www.st.com. This package includes: ST Visual Develop – Full-featured integrated development environment from ST, featuring
- Seamless integration of C and ASM toolsets
- Full-featured debugger
- Project management
- Syntax highlighting editor
- Integrated programming interface
- Support of advanced emulation features for STice such as code profiling and coverage ST Visual Programmer (STVP) – Easy-to-use, unlimited graphical interface allowing read, write and verify the user STM8 microcontroller Flash program memory, data EEPROM and option bytes. STVP also offers project mode for saving programming configurations and automating programming sequences.
12.2.2 C and assembly toolchains
Control of C and assembly toolchains is seamlessly integrated into the STVD integrated development environment, making it possible to configure and control the building of user application directly from an easy-to-use graphical interface. Available toolchains include:
- Cosmic C compiler for STM8 – One free version that outputs up to 16 Kbytes of code is available. For more information, see www.cosmic-software.com.
- Raisonance C compiler for STM8 – One free version that outputs up to 16 Kbytes of code. For more information, see www.raisonance.com.
- STM8 assembler linker – Free assembly toolchain included in the STVD toolset, which allows users to assemble and link the user application source code.
12.3 Programming tools
During the development cycle, STice provides in-circuit programming of the STM8 Flash microcontroller on user application board via the SWIM protocol. Additional tools are to include a low-cost in-circuit programmer as well as ST socket boards, which provide dedicated programming platforms with sockets for programming the user STM8. For production environments, programmers will include a complete range of gang and automated programming solutions from third-party tool developers already supplying programmers for the STM8 family.
Table 56. Document revision history 12-Jul-2011 1 Initial release. Flash program memory and data EEPROM. and Table: I/O static characteristics. ACCHSI in Table: HSI oscillator characteristics. 6.5 x 4.4 mm, 0.65 mm pitch, package mechanical data. Section : Electromagnetic interference (EMI). STM8S003F3/K3 value line block diagram.
Table 56. Document revision history (continued)