ZXFV4089_05 ZETEX | Alldatasheet

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Technical content

The ZXFV4089 is a DC restored video amplifier (black-level clamp) in an 8pin SOIC package. It integrates a high performance video amplifier with a nulling sample and hold amplifier specially designed to provide brightness level stability. The input video signal is AC coupled to the main amplifier and this AC coupling capacitor also acts as the holding capacitor for the sample and hold amplifier. This configuration reduces both pin count and external components over traditional solutions. Typically, during the back-porch interval of an analog video waveform the sample and hold amplifier forces the input of the video amplifier to the reference voltage. The video waveform is now referenced to the new reference voltage for the remainder of the line-scan interval. The video amplifier has been optimised for video applications and as such drives back-terminated 75 /H9024loads with good differential gain and phase errors. The current feedback architecture allows the bandwidth to remain fixed over a wide range of gains, and is set by two external resistors. The ZXFV4089 is specified for operation at ±5V and over the -40°C to +85°C temperature range and is pin compatible with the industry standard EL4089. FEATURES AND BENEFITS

  • Complete analog video dc level restoration system
  • Supports various TV systems
  • PAL, NTSC, SECAM
  • Excellent video performance
  • 0.08% differential gain
  • 0.1° differential phase
  • 30 MHz 0.1 dB bandwidth
  • 210 MHz -3 dB bandwidth
  • 400V//H9262s slewrate
  • TTL/CMOS logic compatible HOLD input
  • Pin and function compatible with industry standard EL4089

APPLICATIONS

  • Black Level Clamp, providing stable intensity in video systems such as:
  • cameras
  • image capture
  • video mixing
  • displays
  • DC restoration of other high frequency signals ZXFV4089 ISSUE 2 - SEPTEMBER 2005 VIDEO AMPLIFIER WITH DC RESTORATION

ORDERING INFORMATION

Part Number Container Increment Part mark ZXFV4089N8TA Reel 7" 500 ZXFV4089 ZXFV4089N8TC Reel 13" 2500 ZXFV4089 CONNECTION DIAGRAM

ABSOLUTE MAXIMUM RATINGS- Over operating free-air temperature (unless otherwise stated)1 Positive supply voltage VCC to GND -0.5V to +5.5V Negative supply Voltage VEE to GND -5.5V to +0.5V Input voltage, pins 1,2,3 to GND V EE -0.5V to VCC +0.5V Differential Input Voltage2, pin 1 to pin 2 ±3 V Output current, pin 7 (continuous, TJ < 110°C) ±60 mA Internal power dissipation See note 3 Input current, IN- pin 1 ±5 mA Current into IN+ and HOLD, pins 2 and 4 ±5 mA Operating ambient temperature range -40°C to 85°C Storage temperature range -65°C to 150°C Operating junction temperature T JMAX 150°C Notes: 1. Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2. At high closed loop gains and low gain setting resistors care must be taken if large input signals are applied to the device which cause the output stage to saturate for extended periods of time. 3. The power dissipation of the device when loaded must be designed to keep the device junction temperature below T JMAX, de-rated according to the Theta-ja for the SO8 package, which is typically 168°C/W, i.e. 0.74W at 25°C. * During power-up and power-down, these voltage ratings require that signals be applied only when the power supply is connected. ESD: This device is sensitive to static discharge and proper handling precautions are required. ZXFV4089 SEMICONDUCTORS ISSUE 2 - SEPTEMBER 2005

PARAMETER CONDITIONS MIN TYP MAX UNIT ICCH Positive supply current, holding HOLD = HIGH 5 8 10 mA ICCS Positive supply current, sampling HOLD = LOW 5 8.5 11 mA IEEH Negative supply current, holding HOLD = HIGH 5 8 10 mA IEES Negative supply current, sampling HOLD = LOW 5 8.5 11 mA Amplifier section, Hold Input = High unless otherwise stated VOS Input offset voltage VIN+ =0 V 11 0 m V IB+ + input bias current 15 µA IB- – input bias current 11 0 µA ROL Trans-impedance V IN+ = ±3V 1800 k /H9024 RIN+ + input resistance 1 2 M /H9024 VO Output voltage swing V IN+ =± 3 V , IOUT = /H1100740mA ±2.95 ±3.0 V IO Output drive current 40 mA +PSRR Positive power supply rejection ratio V CC =5 V ± 5 % ,VEE = -5V 49 57 dB -PSRR Negative power supply rejection ratio V CC =5 V ,V EE =- 5 V± 5 % 5 1 5 8 d B VCMR Common mode input voltage range (1) ±3 V CMRR Common mode rejection ratio V IN = ±3V 48 57 dB Restore section, HOLD = Low unless otherwise stated VOSCOMP Composite input offset voltage, from V REF to amplifier output VREF =0 V 0.3 7 mV IREF VREF input bias current V REF =0 V 3 1 2 µ A IOUT Input restore current available, pin 2 180 300 600 µA V REF input voltage range ±2 V CMRR Common mode rejection ratio V REF = ±2V 54 90 dB +PSRR Positive power supply rejection ratio V CC =5 V ± 5 % ,VEE = -5V 50 60 dB -PSRR Negative power supply rejection ratio V CC =5 V ,V EE =- 5 V± 5 % 5 0 6 0 d B VHmin HOLD pin high logic level 2 V VLmax HOLD pin low logic level 0.8 V IIL Logic low input current HOLD = LOW 40 100 µA IIH Logic high input current HOLD = HIGH 12 µA

ELECTRICAL CHARACTERISTICS

VCC = 5V, VEE = -5V, G =1, RF = 1k/H9024, RLOAD=1k/H9024, Tamb = 25°C unless otherwise stated. NOTES: 1. The voltage at the input to pin 2 should be limited to +2.7V for the best DC restoration accuracy. See later explanation under "Common-mode input range."

PARAMETER CONDITIONS MIN TYP MAX UNIT Amplifier section HOLD = high unless otherwise stated SR Slew Rate V OUT =2 V PP 400 V/µs BW-3 Bandwidth, -3dB V OUT =0 . 2 VPP, G = 2 210 MHz BW-3 Bandwidth, -3dB V OUT =0 . 2 VPP,G=1 ,R f = 820 /H9024 210 MHz BW0.1 Bandwidth, ±0.1dB V OUT =0 . 2 VPP 30 MHz dG Differential gain, NTSC f = 3.58 MHz, V IN = 280mV pk-pk, DC = -714 to +714 mV 0.08 % dP Differential phase, NTSC 0.1 deg Restore section HOLD = low unless otherwise stated SR Slew rate V OUT =2 V PP,C HOLD = 0.01µF* 25 V/µs tENH Time to enable hold 25 ns tDISH Time to disable hold 40 ns * Slew rate is dependent on the ac coupling hold capacitor connected to pin 2. AC ELECTRICAL CHARACTERISTICS VCC =5 V ,VEE =- 5 V ,RF = 470/H9024,G=2 ,R LOAD = 150/H9024,C LOAD =1 0p F ,TAMB = 25°C unless otherwise stated.

TYPICAL CHARACTERISTICS (CONT.)

DC Level Acquisition change In the restore mode the available charging current, together with the capacitor value, determines the maximum DC voltage correction which can be applied at each sample. For a charging current limit of 300 µA applied for 1.2 µs, the charge injected is: Qmax = 300 µA x 1.2 µs = 360 pC Then the maximum voltage shift correction is: Vmax = Qmax/C = 360 pC / 0.01 µF = 36 mV DC Level Droop In the hold state, a small voltage drift is caused by leakage from the Sample-hold circuit and bias current from the main amplifier charging or discharging the coupling capacitor. The drift rate is equal to the bias/leakage current of up to about 1 µA divided by the coupling capacitor value. For a coupling capacitor of 0.01 µF the drift rate is then up to ±100 µV/µs. For a typical video line scan the switch remains open for the rest of the scan duration, or about 62 µs. The drift at the end of the line scan has therefore accumulated to about 6.2 mV. This is acceptable for most applications, but if desired it can be reduced by increasing the value of the coupling capacitor. This will result in a proportionately smaller value of the maximum available correction voltage at each scan as described above. Normally, once settled, the video system requires only a very small correction at each scan, so this will not present any problem. Supply filtering & printed circuit layout In the applied circuit, the power filtering and printed layout design needs special attention as is appropriate for a high-speed analog circuit. For each supply lead, use a leadless ceramic chip capacitor placed very close to the device power pin. A value of 0.1µF is recommended. In addition, a larger value capacitor, which should be ceramic or solid tantalum construction, with a value of 1 to 10 µF, is also recommended for connection to each supply fairly close to the device. The layout naturally requires some short interconnections on the component side (top copper layer) and a continuous ground plane should be provided on another layer with plated via holes providing low inductance ground connections for the device and other components. The amplifier frequency response is affected to some extent by stray capacitance at the inverting input at pin 1. This effect can be minimised by providing a small cut-out area in the ground plane and other layers around pin 1, though this may not always be necessary for the application. Further Applications Information The ZXFV4089 is a high speed device requiring the appropriate care in the layout of the application printed circuit board. A continuous ground plane construction is preferred. Suitable power supply decoupling suggested includes a 100nF leadless ceramic capacitor close to the power supply connections at pin 8 and pin 6. As stated earlier the main video amplifier of the ZXFV4089 is a current feedback amplifier. Compared to a voltage-feedback amplifier, current feedback provides better bandwidths at higher gains and also much faster slew rates. To optimise performance from a current feedback amplifier choice of feedback resistor is very important. In this case, typically the device will be used with a voltage gain of two, using two resistors of 1k/H9024as in Figure 1. Stray capacitance at the inverting input node of this circuit can affect frequency and pulse response, so the printed circuit layout should take account of this. Place the feedback resistors as close as possible to the inverting input pin and minimise the printed metal connected to this pin. Common-mode input range The signal input voltage range is determined partly by the common-mode input range of the main amplifier. The amplifier configuration is non-inverting, and so the inverting input will follow the signal input voltage. It is also necessary to observe the maximum limit on the value of V REF (±2V) which is less than the amplifier input voltage range. Therefore the input range of the system is limited to this value. In addition the restore amplifier voltage input range is restricted to a similar value. Attention is drawn to the footnote of the DC Electrical Characteristics Table, regarding input signal amplitude. The video signal is ac coupled into the main amplifier and clamped to V REF. As a result of this the actual voltage seen by the device input at pin 2 is the sum of V REF plus the video input signal voltage excursion above VREF (when clamping the back porch, this excursion is normally the luminance waveform of up to about 0.72V white level). At a particular positive value at pin 2 close to 2.7V, the leakage current of the Sample-hold switch increases causing an increase in the droop rate. Therefore, for example, a reference voltage of 2V with a peak white video signal of 0.7V could result in increased restoration error arising from the increased DC offset. If pin 2 is driven above +2.7V peak voltage the DC restoration accuracy could be affected and care should be taken in this respect. When using 0.7V luminance, this is consistent with the maximum recommended reference voltage of +2V. Evaluation Circuit An evaluation circuit is available to allow demonstration of the video black-level clamping function. The circuit uses the Zetex ZXFV4583 Sync Separator circuit to provide the HOLD function timing signal. This circuit is described in the data sheet for ZXFV4583. To order the evaluation board, ask for ZXFV4583EV. ZXFV4089 SEMICONDUCTORS ISSUE 2 - SEPTEMBER 2005

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