ZAMC4100 | DigiCamel IC Datasheet

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Document overview

Manufacturer or author: Provided By www.digicamel.com(FREE DATASHEET DOWNLOAD SITE)
PDF pages: 156

Technical content

Datasheet sections

1 IC Characteristics
2 System Blocks Description
3 ZAMC4100 SBC Functional Description

Features

Two main operation modes § NORMAL Mode with all functional ity available § SLEEP Mode with very low current consumption (less than 80µA)
10-bit ADC for measuring various parameters
4 general purpose ADC inputs con figurable for absolute or ratiometric mode
4 low RDS (ON) half-bridge drivers and 4 low RDS (ON) high-side switches
Analog EC mirror output controlled via 6-bit DAC
All outputs short circuit protected
Hardware 8 -bit PWM control for half -bridge and high-side drivers
Over-temperature protection with automatic driver shut-down
Over-voltage and under-voltage detection with automatic driver shut -down
Overload and open/short diagnostic for all outputs
Embedded LIN 2.2/SAE J2602-2 transceiver
Embedded ARM® Cortex™-M0 microcontroller
8 user-configurable GPIO pins Benefits
Multi-chip-module concept with high functional integrity
Low number of external components
Small footprint plastic QFN package with exposed pad allowing better thermal management
AEC-Q100 qualified product, o ptimized for automotive environment
Smart power managemen t concept for achieving low sleep current consumption (< 80µA) Available Support
Data sheet and application notes
Evaluation and Application Kits
Software Development Kit (SDK) Physical Characteristics
Ambient operation temperature: - 40°C to +85°C
Wide power supply voltage range: 6V to 18V
Plastic QFN64 9x9mm package ; exposed die pad ZAMC4100 PQFN64 TOP VIEW EXPOSED PAD (pin 65) VDDE1 n.c. VSS4 HB3 EC_RES EC_M VSS5 HS4 CAP_CP LIN VSS_LIN VSS_IO STO VSSD2 TEST TRSTNVDDE VSSD1 CAP_5V0 S_P AIN1 AIN2 S_N AIN4/TEMP2 VSSA AIN3/TEMP1 n.c. HB4 VSS1 n.c. n.c. VDDE8 TCK TMS TDO TDI GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 n.c. CAP_3V3 CAP_1V8 HB2a VSS3 HB1b VDDE2 VDDE3 HS1a VDDE4 VDDE5 HS2 HS1b VDDE6 VDDE7 HB1a HS3 VSS2 HB2b CAP_MCU * Note: The ARM® and Cortex™ trademarks are owned by ARM, Ltd.

Actuator and Motor Controller ZAMC4100 Datasheet © 2016 Integrated Device Technology, Inc. 2 January 26, 2016 Automotive Mirror Control HB1 HB2 HB3 HB4 HS4 M M M HS3 Turn signal Puddle lamp HS2 BSD lamp HS1 Heater EC_RES EC_M S_P S_N AIN1 AIN2 EC Mirror VDDE CAP_5V0 VSS1-5VSSD1-2VSSA AIN3/TEMP1 GPIO0 GPIO7 LIN GND Vbat CAP_CP VDDE1-8 VSS_LIN ext. temp CAP_3V3 CAP_1V8 CAP_MCU ZAMC4100 VSS_IO C1C3 C9 D2 AIN4/TEMP2 Typical Applications

Automotive exterior rear view mirror controllers
Intelligent DC motor drivers
Stand alone or slave actuator controllers
Power management for low voltage electrical systems
Single chip solution for optimized white goods’ controllers Note: Refer to the ZAMC4100 Data Sheet for the values and functions of the external components in the application circuit. Multi-Chip-Module Assembly: Microcontroller Unit (MCU) and System Basis Chip (SBC) SBC MCU Off-chip bonding wiresExternal pin bonding wires Exposed pad

© 2016 Integrated Device Technology, Inc. 3 January 26, 2016 System Basis Chip TXD RXD AFE Ctrl. & Data Path S_P S_N AIN1 AIN2 VSS1..5 VSSD2 CAP_1V8 TXD RXD TEST CONTROL CSN SPI_CLK MOSI MISO HB1a HB1b HB2a HB2b HB3 HB4 HS2 HS3 HS1b EC_M MCU_CLK 1V8_MCU 3V3_MCU CAP_CP VSSA CAP_5V0 VDDE LIN SBC Analog SBC Dig. Core LIN PHY VDD1V8 VDD3V3 VDD5V0 BG & Ref VDD2V5 Charge Pump OSCL 125kHz POR PORB OVRV UNDV OVRT OSCH 20MHz DAC Motor driverLamp & Defogger Driver Analog Back-End EC_RES MCU chip TEST TRSTN TESTTEST TCKTCK TMSTMS TRSTN STOTDI TDO TRSTN TCK TMS STO TDO TDI TEST FLASH PROGRAMMING CONTROL SPI Slave & Control Logic LIN wake-up Diagnostic & Control Clk & Reset Ctrl Analog Back-End Control Reg File WDT IRQ Ctrl Diagnostic Driver CTRL DAC Ctrl IRQN UART Clk & Rst ctrl MCU_RSTN SPI Master/Slave IRQ Ctrl RAM 2KB FLASH 32KB GPIO GPIO2 GPIO3 GPIO4 GPIO1 GPIO0 SAR ADC Vref Analog Front-EndMUX TIMER modules HS1a HS4 CAP_3V3 ARM Cortex M0 VDDE1..8 GPIO5 GPIO6 GPIO7 VSSD1 VSS_LIN 256B emulated EEPROM (optional) PWM CAP_MCU DBGEN VSS_IO AIN3/TEMP1 AIN4/TEMP2 ZAMC4100 Block Diagram SENSORS INTERFACE PINS DESCRIPTION S_P Positive supply for sensors (5V) S_N Negative supply for sensors (0V) AIN1 General purpose ADC input AIN2 General purpose ADC input AIN3/TEMP1 General purpose ADC input/temperature sensor input AIN4/TEMP2 General purpose ADC input/temperature sensor input

© 2016 Integrated Device Technology, Inc. 4 January 26, 2016 ACTUATORS INTERFACE PINS DESCRIPTION COMMUNICATION INTERFACE PINS DESCRIPTION HB1a Output of half-bridge driver 1 LIN LIN bus HB1b GPIO0 to GPIO7 General purpose I/O pins HB2a Output of half-bridge driver 2 TEST INTERFACE PINS DESCRIPTION HB2b HB3 Output of half-bridge driver 3 TEST Global test enable pin HB4 Output of half-bridge driver 4 TRSTN JTAG Low-active Reset HS1a Output of high-side switch 1 TCK JTAG clock HS1b TMS JTAG Mode Select HS2 Output of high-side switch 2 TDO JTAG data out pin HS3 Output of high-side switch 3 TDI JTAG data in pin HS4 Output of high-side switch 4 STO SBC test data out EC_M Output for EC mirror control SUPPLY PINS DESCRIPTION EC_RES Connection to external resistor for EC VDDE Supply for the system SERVICE PINS DESCRIPTION VDDE1 to VDDE8 High current supply for the drivers CAP_5V0 Connection to external capacitor for 5V (SBC analog core supply) VSS1 to VSS5 High current ground for drivers CAP_3V3 Connection to external capacitor for 3.3V (MCU peripheral supply) VSS_LIN Ground for LIN transceiver CAP_1V8 Connection to external capacitor for 1.8V (SBC digital core supply) VSSA Ground for analog blocks (low noise) CAP_MCU Connection to external capacitor for 1.8V (MCU core supply) VSSD1 Ground for digital blocks of SBC CAP_CP Connection to external capacitor for CP VSSD2 Ground for MCU EXPOSED PAD Connected to digital ground VSS_IO Ground for SBC digital IOs

Ordering Information

Product Sales Code Description Package ZAMC4100GA2R ZAMC4100GA PQFN64 – Temperature range: -40°C to +85°C 13” Tape and Reel ZAMC4100GA2V ZAMC4100GA PQFN64 – Temperature range: -40°C to +85°C Tray ZAMC4100 Evaluation Kit V2.0 including the ZAMC4100 Evaluation Board; software available at www.IDT.com/ZAMC4100

© 2016 Integrated Device Technology, Inc. 16 January 26, 2016 Charge Pump Charge pump output voltage (with respect to VDDE1; drivers disabled) VCP 4.5 5.0 5.5 V Charge pump output current (through CAP_CP pin) ICAP_CP - - 10 µA External Capacitor Pins Voltage REG5V0 capacitor pin CAP_5V0 VCAP_5V0 4.5 5.0 5.5 V REG3V3 capacitor pin CAP_3V3 VCAP_3V3 2.97 3.3 3.63 V REG1V8 capacitor pin CAP_1V8 (on SBC side) VCAP_1V8 1.62 1.8 1.98 V REG1V8 capacitor pin CAP_MCU (on MCU side) VCAP_MCU 1.62 1.8 1.98 V Charge pump capacitor pin CAP_CP (with respect to VDDE 1 pin) VCAP_CP 4.3 - 5.5 V Table 1.5 System Resets and Supply Monitoring Parameter Symbol Min. Typ. Max. Unit Power-On Reset Threshold 1) PORTH 4.2 4.5 4.8 V Hysteresis PORHYST 0.2 0.3 0.4 V Under-Voltage Detection Threshold 1) UVDTH 5.7 6.0 6.3 V Hysteresis UVDHYST 0.05 0.2 0.3 V Over-Voltage Detection Threshold 1) OVDTH 17.7 18.6 19.5 V Hysteresis OVDHYST 0.3 0.5 0.7 V Over-Temperature Drivers Shut -Down Threshold 2) OVTTH - 125 - °C Hysteresis 2) OVTHYST - 5 - °C 1) These parameters are defined with respect to the potential at the VDDE pin. 2) Junction temperature of the SBC chip. Parameter guaranteed by process monitoring but not tested during production.

© 2016 Integrated Device Technology, Inc. 18 January 26, 2016 Parameter Symbol LIN Spec 2.2 Reference Min Typ. Max Unit Difference between battery shift and ground shift 2) VSHIFT_Difference Parameter 24 0 - 8 % LIN pull-up resistor RSLAVE Parameter 26 20 40 60 kΩ Duty cycle 1 D1 Parameter 27 0.396 - - - Duty cycle 2 D2 Parameter 28 - - 0.581 - Duty cycle 3 D3 Parameter 29 0.417 - - - Duty cycle 4 D4 Parameter 30 - - 0.590 - Receiver propagation delay tRX_pdr Parameter 31 - - 6 µs Receiver propagation delay symmetry between rising and falling edge tRX_sym Parameter 32 -2 - 2 µs Capacitance of slave node 2) CSLAVE Parameter 23 - - 250 pF LIN pin capacitance 1) CLIN - - - 30 pF Over-current shutdown threshold IOC_LIN - 45 - 175 mA LIN wake-up filter time tLINWU - 100 125 150 µs TxD dominant time out time tDOM - 11 - - ms LIN fast mode data rate (Cbus = 1nF, Rbus = 1kΩ ) 1) LBFAST - - - 115 kbps 1) Parameter guaranteed by process monitoring but not tested during production. 2) Standard LIN network parameter which specifies operating condition for the IC. 1.2.4. Output Drivers Table 1.8 Drivers Static Parameters Parameter Symbol Min. Typ. Max. Unit HS1 (High-Side Switch) Switch-on resistance (at 27°C; VSUP=13.5V; IHS1=1A) RDSON_HS1 110 170 230 mΩ Over-current shut down IOC_HS1 5.5 6.1 6.7 A Leakage current ILEAKAGE_HS1 - <0.5 15 μA Current sense ratio CSR_HS1 650000 695000 740000 -

© 2016 Integrated Device Technology, Inc. 23 January 26, 2016 n SMPADC tSRt __ 2 −= , where n = [0:7] and n is the decimal equivalent of the value configured in bit field ADCSR[2:0] in the ADCCONF register (see Table 3.37). 6) For external temperature measurement, the ADC sample time is fixed. Changing ADCSR[2:0] changes the ADC idle time. 7) The parameter tADC_IDLE is calculated using the formula: ( ) CNVADCTMSMPADCMAX n IDLEADC ttSRt ____ 2 −−= , where n = [3:7] and n is the decimal equivalent of the value configured in bits ADCSR[2:0]. Important: For n = [0:2], tADC_IDLE = 0. Figure 1.1 ADC Timing Parameters Definition tADC_STL tADC_CNV tADC_SMP tCCNV tSCNV tADC_STL tADC_CNVtADC_SMP_TM All other ADC conversions Ext. temperature ADC conversion tADC_IDLE tCCNV_TM tSCNV_TM

© 2016 Integrated Device Technology, Inc. 25 January 26, 2016 porb PORHYST Vfall Vrise rstn VDDE TYP tPWRT t t t tHDPOR tHDPOR Analog Circuitry SETTLING STABLE STABLESETTLINGUNSUP tPWRT tCharge Pump SUPLIED SETTLING STABLEUNSUP t SUPPLIED SETTLING STABLE tCP_STL PORTH tCP_STL

© 2016 Integrated Device Technology, Inc. 30 January 26, 2016 SBC: LIN PHY, Wake-up, Diagnostics MCU: LIN Controller MCU: Firmware (LIN Protocol Engine) ZAMC4100 SIP PHYSICALMedia, Signal & Binary Transmission DATA LINKPhysical Addressing NETWORKPath Determination & Logical Addressing BITS FRAMES PACKETS Media Layers OSI Model RX TXpd RXD TXDLIN LIN PHY TXD TXD RXD RXD LIN Wake-up Diag & Ctrl Dominant Time-Out LIN Short (debounced) LIN Wake-up LIN Pwr Crtl LIN Controller BREAK/SYNC Detection Inactivity Timer (4 sec) SBC Chip MCU Chip UARTsh sh = short pd = power down

© 2016 Integrated Device Technology, Inc. 33 January 26, 2016 Power supply Sys. Reset Yes No No No Yes 1) Enable MCU clock 2) Release MCU reset Enable SBC NORMAL Mode TPWRT? MCU SW initialization MCU application routine execution POR generated MCU SUPPLY ON SBC MCU MCU supply valid? No Yes SLEEP Mode entry Yes TMSC? SW diagnostic check: 1) SBC-to-MCU connectivity check 2) ADC check 3) Output drivers check

© 2016 Integrated Device Technology, Inc. 36 January 26, 2016 Figure 3.3 ZAMC4100 Reset Sources POR WDT sys_rst SLEEP mcu_rst STBY PWRT tPWRT SBC clock OVT DRIVERS RSTN SBC RSTN MCU RSTN WDTMCUF PORF OVTIF WDTSYSF

© 2016 Integrated Device Technology, Inc. 38 January 26, 2016 Osc 125kHz Divider Postscaler MCU reset 10ms Postscaler System reset mcu_rst sys_rst WDT time-base WDTEN MWDPOS[2:0] SWDPOS[1:0]WDTCLR 3 2 en clr WDTPMEN SLEEP STBY WDTIFWDTIESTBY SLEEP wake-up STBY wake-up SLEEP STBY

© 2016 Integrated Device Technology, Inc. 39 January 26, 2016 MWDPOS "000" (MCU reset time-out tMCU_TO = 10ms) SWDPOS "10" (System reset time-out tSYS_TO = 4x10ms) tMCU_TO tMCU_TO tMCU_TO MCU_RSTN (internal pin) SYS_RSTN (internal signal) tMCU_RST tSYS_RSTtSYS_TO

© 2016 Integrated Device Technology, Inc. 40 January 26, 2016 Bit name WDTCLR SWDPOS[1] SWDPOS[0] MWDPOS[2] MWDPOS[1] MWDPOS[0] WDTLCK WDTEN Reset 0 0 0 1 0 0 0 1 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x04 R/W = Read/Write

© 2016 Integrated Device Technology, Inc. 41 January 26, 2016 Table 3.4 WDTCONF Register Bits Description Bit Description 4:2 1 WDTLCK: WDT configuration lock bit. 1 = The writing to the WDTCONF register is not possible and writing can be enabled only after a power-on reset. 0 = The write access of WDTCONF is enabled. 0 WDTEN: WDT enable bit. 1 = The WDT is enabled, and if a time-out occurs, it will generate an MCU reset. 0 = The WDT is disabled. No reset is generated by WDT.

© 2016 Integrated Device Technology, Inc. 45 January 26, 2016 Figure 3.7 ZAMC4100 SLEEP and STANDBY Mode Behavior SBC MCU SPI SMDCTRL writeSLEEP = 1 NoLIN wake-up? Yes Analog blocks power-down Clock switch4MHz à 125kHz Analog blocks power-up Clock switch125kHz à 4MHz No Yes MCU SW initialization MCU SUPPLY ON MCU supply valid? Yes SLEEP MCU SUPPLY OFF 1) Enable MCU clock2) Release MCU reset NORMAL Mode MCU application routine execution SW Diagnostic Check:1) SBC-to-MCU connectivity check2) ADC check3) Output drivers check SBC MCU NORMAL Mode SPI SMDCTRL writeSTBY = 1 YesLIN wake-up? No LIN wake-up enable IRQN = 0 STBY MCU clock gate MCU suspended Yes Other IRQ event? No MCU applicationroutine execution ZAMC4100 SLEEP Mode ZAMC4100 STANDBY Mode TMSC? No MCU clock enable Yes NoIRQN = 0?

© 2016 Integrated Device Technology, Inc. 47 January 26, 2016 Bit name CPVEIFAC SEIFAC WDTPMEN OVDP UVDP STBY SLEEP Reset U 0 0 0 1 1 0 0 Access U R/W R/W R/W R/W R/W W W Address 0x03 R/W = Read/Write bit; W = Write-only bit, read as 0; U = Unimplemented, read as ‘0’

© 2016 Integrated Device Technology, Inc. 49 January 26, 2016 IRQN IRQSTAT &WDTIF WDTIE &OVTIF OVTIE SEIF SEIE ADCIF ADCIE HBOCIF HBOCIE HSOCIF HSOCIE &ECMOCIF ECMOCIE LINIF LINIE SBC MCU ZAMC4100 MCU Interrupt Controller IRQCTRL ADCRDYIFADCCMPIF HB1OCIF HB2OCIF HB3OCIF HB4OCIF HS1OCIF HS2OCIF HS3OCIF HS4OCIF LINWUIF LINDTOIF LINSHIF ADCSTAT HBDSTAT HSDSTAT LINSTAT SBC Global Interrupts SBC Peripheral Interrupts OVIF UVIF RSTSTAT CPVEIF OSCLEIF &CMPEN

© 2016 Integrated Device Technology, Inc. 51 January 26, 2016 Table 3.9. The details for each peripheral interrupt are given in the sections where the corresponding periphery is described. Table 3.7 IRQCTRL Register Bits Mapping Name IRQCTRL Bit No 7 6 5 4 3 2 1 0 Bit name WDTIE OVTIE SEIE ADCIE HBOCIE HSOCIE ECMOCIE LINIE Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x02 R/W = Read/Write

© 2016 Integrated Device Technology, Inc. 52 January 26, 2016 Table 3.8 IRQCTRL Register Bits Description Bit Description 7 WDTIE: Watchdog timer interrupt enable bit during STANDBY Mode. 1 = WDT interrupt is enabled. 0 = WDT interrupt is disabled. Note: This interrupt is generated only when the system is in STANDBY Mode.

© 2016 Integrated Device Technology, Inc. 53 January 26, 2016 Table 3.9 IRQSTAT Register Bits Mapping Name IRQSTAT 1) Bit No 7 6 5 4 3 2 1 0 Bit name WDTIF OVTIF SEIF ADCIF HBOCIF HSOCIF ECMOCIF LINIF Reset 0 0 0 0 0 0 0 0 Access R R R R R R R R Address 0x01 R = Read-only bit 1) The ECMOCIF is physically implemented in register ECMDIAG (Table 3.30) and mapped to IRQSTAT. Table 3.10 IRQSTAT Register Bits Description Bit Description

© 2016 Integrated Device Technology, Inc. 56 January 26, 2016 Figure 3.10 SPI Frames CMD MISO A) Data WRITE Frame B) Data READ Frame C) Command Byte Structure Legend: MOSI WR DATA SSB PTR DATA CMD MISO MOSI SSB 7 12 B Address[4:0] R/W D) Slave Status Byte Structure 7 6 5 4 3 2 1 0 CSN CSN RD DATA RD DATA Reserved bits (keep at 0) R/W = Read / not Write B= Burst read enable ACCSIG LINIFSEIFECMCLIFHSOCIFHBOCIFADCCMPIFADCRDYIF

© 2016 Integrated Device Technology, Inc. 57 January 26, 2016 MISO MOSI SSB 07 CSN RD DATA(Addr) 07 RD DATA (Addr) 07 B) Burst SPI READ 1 0Address[4:0] MISO MOSI SSB 07 CSN RD DATA(Addr) 07 RD DATA (Addr+1) 07 1 1Address[4:0]

© 2016 Integrated Device Technology, Inc. 59 January 26, 2016 VSS Driver H Charge Pump Driver L HBxHEN HBx pin VSS VSS HBxCSHEN HBxCSLEN HBxLEN OCH Detect HBxOCIF Limit OCL Detect 20µs Counter Integrator CPVEIF Limit HBxOSF CSH CSL Open/Short Detect OVT Reset OVT Reset OVIF UVIF HBx PWMEN From PWM Block OVTIF

© 2016 Integrated Device Technology, Inc. 60 January 26, 2016 Bit name HB4HEN HB4LEN HB3HEN HB3LEN HB2HEN HB2LEN HB1HEN HB1LEN Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x06 R/W = Read/Write Table 3.14 HBDCTRL Bits Description Bit Description 7,5,3,1 HBxHEN: 1), 2), 3), 4) High-side MOSFET enable bit for half-bridge driver x, (x=4 to 1) 1 = High-side MOSFET enabled 0 = High-side MOSFET disabled

© 2016 Integrated Device Technology, Inc. 61 January 26, 2016 Table 3.15 HBDSTAT Register Bits Mapping Name HBDSTAT Bit No 7 6 5 4 3 2 1 0 Bit name HB4OSF HB3OSF HB2OSF HB1OSF HB4OCIF HB3OCIF HB2OCIF HB1OCIF Reset 0 0 0 0 0 0 0 0 Access R R R R R/Wc R/Wc R/Wc R/Wc Address 0x0A R/Wc = Read/Write 1 to clear, R = Read-only Table 3.16 HBDSTAT Register Bit Descriptions Bit Description

© 2016 Integrated Device Technology, Inc. 62 January 26, 2016 0 10 20 30 40 50 60 70 90 110 t [µs] HS or LS Over- Current Event 0 10 20 30 40 50 60 70 80 90 100 110 t [µs] OC Counter (integrator) 0 10 20 30 40 50 60 70 80 90 100 110 t [µs] HBxOCIF HBxOCIF clear 20µs 10080 Case A Case B Case C Note: One counter step = 250ns 10µs10µs 5µs 15µs 10µs 20µs

© 2016 Integrated Device Technology, Inc. 63 January 26, 2016 Bit name HB4CSHEN HB4CSLEN HB3CSHEN HB3CSLEN HB2CSHEN HB2CSLEN HB1CSHEN HB1CSLEN Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x07 R/W = Read/Write bit Table 3.18 HBDDIAG Register Bits Description Bit Description 7,5,3,1 HBxCSHEN: 1), 2) High-side current source enable bit for driver x, (x = 4 to 1, for HB4 to HB1 respectively). 1 = The high-side current source of driver x is enabled. 0 = The high-side current source of driver x is disabled.

© 2016 Integrated Device Technology, Inc. 65 January 26, 2016 VDDE Driver H Charge Pump HSxEN HSx pin VSS HSxCSEN OCH Detect HSxOCIF Limit 20µs Counter Integrator Open/Short DetectHSxOSF CS RLOAD VSS OVT Reset HSx PWMEN From PWM Block CPVEIF OVIF UVIF OVTIF

© 2016 Integrated Device Technology, Inc. 66 January 26, 2016 3.9.1. High-Side Control and Status Register Table 3.20 HSDCTRL Register Bits Mapping Name HSDCTRL Bit No 7 6 5 4 3 2 1 0 Bit name HS4CSEN HS3CSEN HS2CSEN HS1CSEN HS4EN HS3EN HS2EN HS1EN Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x08 R/W = Read/Write Table 3.21 HSDCTRL Register Bits Description Bit Description 7:4 HSxCSEN: 1), 2) Current source enable bit for high-side driver x, (x = 4 to 1). 1 = The current source of high-side driver x is enabled. 0 = The current source of high-side driver x is disabled.

© 2016 Integrated Device Technology, Inc. 67 January 26, 2016 Important note: When the diagnostic circuitry is enabled (one of the HSxCSEN bits is set), then the corresponding over-current protection circuitry is not active. Therefore enabling the driver when the diagnostic circuitry is enabled is not recommended! Table 3.22 HSDSTAT Register Bits Mapping Name HSDSTAT Bit No 7 6 5 4 3 2 1 0 Bit name HS4OSF HS3OSF HS2OSF HS1OSF HS4OCIF HS3OCIF HS2OCIF HS1OCIF 3:0 HSxOCIF: Over-current interrupt flag of the high-side driver x (x = 4 to 1). 1 = There is an over-current in the output of driver x. The driver x is disabled as long as this bit is set. 0 = There is no over-current in the output of driver x. Table 3.24 High-Side Diagnostic Bits Description HSxCSHEN HSxOSF Description 1) 0 0 Normal load or short to VSS 2) 1 0 0 0 Open load 1 1 0 1 Short to VDDE 1 1 0 1 Not possible in normal application 1 0 1) Important: The diagnostic result is correct only if the corresponding driver is switched off. 2) In the event of a short, an over-current will occur.

8 HB1PWMEN

© 2016 Integrated Device Technology, Inc. 69 January 26, 2016 PWMDCFG PWMFCFG PWM signal PWMDCFG PWMFCFG The PWM frequency is configured via register PWMFCFG and is calculated using the formula: [ ]255:0][,]1[256 )80/( ∈→+×= PWMFCFGHzPWMFCFG

© 2016 Integrated Device Technology, Inc. 73 January 26, 2016 Figure 3.19 ECM Driver Structure VDDE VSS ECMEN EC_M EC_RES EN ECMOSF ECMDAC[5:0] ECMCSHEN RECMpCECM VSS DAC OVT Reset OVIF UVIF CSH CSL RECMs ECMCSLEN Open/Short Detect Error Amplifier HS Ctrl OC Detect LS ctrl ECM Control ECMOCIF DSCEN

© 2016 Integrated Device Technology, Inc. 75 January 26, 2016 Bit name ECMEN DSCEN ECMDAC[5] ECMDAC[4] ECMDAC[3] ECMDAC[2] ECMDAC[1] ECMDAC[0] Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x09 R/W = Read/Write bit Table 3.28 ECMCTRL Register Bits Description Bit Description 7 ECMEN: 1) 2) 3) Electrochromatic mirror driver enable bit. 1 = ECM driver is enabled. 0 = ECM driver is disabled. 6 DSCEN: 1) 2) Electrochromatic mirror discharge enable bit. 1 = ECM driver low-side MOSFET is ON; EC mirror discharge enabled. 0 = ECM driver low-side MOSFET is OFF; EC mirror discharge disabled.

© 2016 Integrated Device Technology, Inc. 76 January 26, 2016 Bit name ECMCSHEN ECMCSLEN ECMOSF ECMOCIF Reset U U U U 0 0 0 0 Access U U U U R/W R/W R R/Wc Address 0x0C R/W = Read/Write; R = Read-only bit; U = Unimplemented, read as ‘0’; R/Wc = Read/Write 1 to clear 1) The ECMOCIF is physically implemented in register ECMDIAG and mapped to IRQSTAT (Table 3.10). Table 3.30 ECMDIAG Register Bits Description Bit Description 7:4 Unimplemented bits. Read as 0. 3 ECMCSHEN(1): ECM high-side current source enable bit. 1 = High-side current source is enabled. 0 = High-side current source is disabled.

© 2016 Integrated Device Technology, Inc. 78 January 26, 2016 Figure 3.20 illustrates the block diagram of the ADC module with the result comparator at the bottom of the diagram. Figure 3.20 ADC Functional Diagram Input MUX VSSA AIN1 Analog Inputs AIN2 AIN3 AIN4 ADCRESH ADCRESL ADCRES[9:0] FORMATTING Int.Ref VREF RESFMT CMP Counter CMP RCMPCNT ADCCMPIF ADCRDYIF ADC Rate ADCSR[2:0] SysClk ADC CCNV SCNVINPSEL[4:0] ADCCMPLADCCMPH 2 8 AINCONF NMOS Current Inputs HB1 H/L* HB2 H/L HB3 H/L HB4 H/L HS1 H HS2 H HS3 H HS4 H Internal Temp Internal Diag *H/L H = HIGH SIDE NMOS, L = LOW SIDE NMOS NMOS Current Inputs CMPTH CMPMD CNTDEC ECM VDDE This module is highly versatile due to a comprehensive register structure as summarized below: • ADC External Port Configuration Register AINICONF • ADC Multiplexer and Control Register ADCCTRL • ADC Configuration Register ADCCONF • ADC Status Register with Interrupts Flags ADCSTAT • ADC Compare and Counter Registers RESCMPH, RESSCMPL, RCMPCNT • ADC Digitized and Formatted Results ADCRESH and ADCRESL

© 2016 Integrated Device Technology, Inc. 79 January 26, 2016 S_P AINx S_N ADC SPSWEN Input MUX VREFP VREFN VSSA VDD5V0 SNSWEN Sensor Signal Source AINx Input MUX VSSA Int.RefVREF ADC VREFP VREFN A) External Sensor Supply C) Absolute Measurement S_P AINx S_N Input MUX VSSA VDD5V0 Sensor -VE +VE Ratiometric Inputs Configuration B) Internal Sensor Supply

© 2016 Integrated Device Technology, Inc. 80 January 26, 2016 CS ratio 1:10 Temp. Sensor AIN3/4 Input MUX VSSA Int.Ref VREF ADC VREFP VREFN ZAMC4100 AINxTMEN VDD5V0 For more information about the temperature measurement including the LM135 and thermistors, refer to the ZAMC4100 Application Note – ADC. Table 3.32 AINCONF Register Bits Mapping Name AINCONF Bit No 7 6 5 4 3 2 1 0 Bit name SPSWEN SNSWEN AIN4TMEN AIN3TMEN AIN4MD AIN3MD AIN2MD AIN1MD Reset 0 0 0 0 0 0 0 0 Access R/W R/W R/W R/W R/W R/W R/W R/W Address 0x10 R/W = Read/Write bit Note: When the ADC conversion is running, the AINCONF register is accessed as read-only.

© 2016 Integrated Device Technology, Inc. 81 January 26, 2016 Table 3.33 AINCONF Register Bits Description Bit Description 5:4 AINxTMEN: Enable external temperature measurement at pins AIN3, AIN4. 1 = Pin AINx (x=3, 4) is configured for temperature measurement. 0 = Pin AINx (x=3, 4) is used as a general-purpose pin. Note: When AINxTMEN = 1, the bits AINxMD are “don’t care.”

© 2016 Integrated Device Technology, Inc. 82 January 26, 2016 Table 3.34 ADCCTRL Register Bits Mapping Name ADCCTRL Bit No 7 6 5 4 3 2 1 0 Bit name CCNV SCNV INPSEL[4] INPSEL[3] INPSEL[2] INPSEL[1] INPSEL[0] 6 CCNV: Continuous Conversion Mode. 1 = ADC performs Continuous Conversion Mode. 0 = ADC idle.

© 2016 Integrated Device Technology, Inc. 83 January 26, 2016 Table 3.36 Input MUX Control Bits Description INPSEL[4:0] value Channel Number [DEC] Selected Channel Name Notes Application mode ADC channels 00000 0 AIN1 The type of measurement depends on the value of the AICONF register. 00001 1 AIN2 00010 2 AIN3 00011 3 AIN4 00100 4 HB1H Current measurement mode. Measures the current through the high-side/low-side transistor of the half-bridge drivers 1-4.

© 2016 Integrated Device Technology, Inc. 84 January 26, 2016 RATIORESCODE 100 2][ 10 VV VAINxRESCODE REF ∗= For VDDE measurements, the equation is: [V]V VDDE[V]RESCODE REF∗ ∗= 8 210 Absolute current measurement This measurement is for internal channels associated with half-bridge and high-side drivers. The equation below represents a current measurement in RESCODE (unsigned) after internal translation using two constants: CSR_X = Current Sense Ratio Coefficient (specified for each high-side and half bridge driver in Table 1.8) IREF = Calibrated internal reference current as specified in Table 1.12 (typically 10µA) 2][ AICSR AIRESCODE REFX IN ∗µ= Where IIN = Input current up to full-scale range equal to (CSR_X Û IREF)

© 2016 Integrated Device Technology, Inc. 85 January 26, 2016 External temperature measurement For a basic understanding of external temperature measurement for the diode-based sensor, the equation below provides a temperature measurement result (unsigned) within RESCODE (other additional factors apply in final applications; contact IDT for more details using the contact information on page 155): [V]V T[K]RESCODE [V]Vq )(kT[K]RESCODE REF REF ∗∗∗∗= 1538.0 210ln32 Where: q = elementary charge (1.60217646 x 10-19) k = Boltzmann constant (1.3806503 x 10-23) Internal temperature measurement The formula for temperature calculation in correspondence with the conversion unsigned result is ( ) 27105123072 10 3 +⎟⎟ ∗−⎟⎟ ⎛ +°∗ ∗=° C][mV/S [V]VRESCODEC][mV/S [V]VC]T[ VT t VT

© 2016 Integrated Device Technology, Inc. 86 January 26, 2016 Table 3.37 ADCCONF Register Bits Mapping Name ADCCONF Bit No 7 6 5 4 3 2 1 0 Bit name RESJSTF RESSIGN CCNVMD ADCSR[2] ADCSR[1] ADCSR[0] 4 RESSIGN: Result register in signed or unsigned format. 1 = Signed value (RESCODE = -512 to +511 full-scale range). 0 = Unsigned value (RESCODE = 0 to 1023 full-scale range).

© 2016 Integrated Device Technology, Inc. 89 January 26, 2016 CMD = ADCCTRL write MCU MCU SCNV = 1, INPSEL = HS1 SSB à CNVRDYIF ADCRESH = I(HS1) CMD = ADCCTRL write SCNV = 1, INPSEL = HS2 SSB ADCRESH CMD = ADCCTRL write SCNV = 1, INPSEL = HS3 SSB à CNVRDYIF ADCRESH = I(HS2) SPI Bus: Pipelining ADC Conversion and Result Read Settings:Register SPIDPTR = ADCCTRL addressResult formatting: truncated 8-bit result SBC

© 2016 Integrated Device Technology, Inc. 90 January 26, 2016 9 2 1 0 ADCRESLADCRESH7 0 7 6 Read 0 ADCRESLADCRESH7 0 7 6 Read 0S Unsigned RESSIGN = 0 Signed RESSIGN = 1 S = Sign bit: 0 = Positive result 1 = Negative result => RESCODE (ADCRES[9:0]) (Software Variable) SPI TRANSFER LEFT JUSTIFIED 9 8 7 0 ADCRESLADCRESH7 0 7 6 ADCRESLADCRESH7 0 7 6 S Unsigned RESSIGN = 0 Signed RESSIGN = 1 S = Sign bit: 0 = Positive result 1 = Negative result => RESCODE (ADCRES[9:0]) (Software Variable) SPI TRANSFER Read 0 Read S RIGHT JUSTIFIED

© 2016 Integrated Device Technology, Inc. 92 January 26, 2016 S_P SPSWEN VDD5V0 ZAMC4100 A) S_P pin protection and diagnostic VDD5V0 AINCSHEN AINCSLEN Open/Short Detect SPOSF AINx ZAMC4100 B) AINx pin diagnostic VDD5V0 AINCSHEN AINCSLEN AINxOSFOpen/Short Detect

© 2016 Integrated Device Technology, Inc. 93 January 26, 2016 Table 3.43 AINDIAG Register Bits Mapping Name AINDIAG Bit No 7 6 5 4 3 2 1 0 Bit name SPOSF AIN4OSF AIN3OSF AIN2OSF AIN1OSF AINCSHEN AINCSLEN

© 2016 Integrated Device Technology, Inc. 94 January 26, 2016 Table 3.45 External ADC Inputs Diagnostic Bits Description AINCSHEN AINCSLEN SPOSF or AINxOSF Description 1) 0 0 x Diagnostic disabled 1 1 x Undefined result 0 1 0 Normal sensor or short to VSSA 1 0 0 0 1 0 Open sensor connection 1 0 1 0 1 1 Short to sensor supply 1 0 1 0 1 1 Not possible in normal application 1 0 0 1) The descriptions given are based on use of the external connections shown on the application diagram (see Figure 6.1). If another configuration of external connections is used, the meaning of the SPOSF and AINxOSF bits will be different.

© 2016 Integrated Device Technology, Inc. 95 January 26, 2016 LIN LIN PHY RXD LIN Short DebounceLINSHIF TX PD LINFAST STBY SLEEP VDDE Pull-up LINWUIF LIN Wake-up Detect RX LINDTOIF TXD VSS Dominant Time- Out Detect LINSHDB ZAMC4100 SBC LINWUMD This module has two registers: • LIN control register LINCTRL (see Table 3.46) • LIN status register LINSTAT (see Table 3.48)

© 2016 Integrated Device Technology, Inc. 97 January 26, 2016 Bit name LINWUMD LINSHDB[1] LINSHDB[0] LINFAST Reset U U U U 0 0 0 0 Access U U U U R/W R/W R/W R/W Address 0x17 R/W = Read/Write bit U = Unimplemented, read as ‘0’

© 2016 Integrated Device Technology, Inc. 99 January 26, 2016 0x00 0x1B 0x1C 0x1F AUTHSIG Analog trim registers Global system control and status registers Control and status registers for drivers Control and status registers for ADC LIN PHY registers PWM control registers Application Registers

© 2016 Integrated Device Technology, Inc. 103 January 26, 2016 4 ZAMC4100 MCU Functional Description 4.1. Overview The ZAMC4100 features a 32-bit ARM® Cortex™-M0 MCU with following peripherals: • 32KB FLASH program memory • 2KB SRAM data memory • SPI master • 32-bit timer • 8 configurable GPIOs • LIN UART Note: Since the ZAMC4100 MCU is based on common Cortex M0 core architecture the description below excludes this topic. Refer to the ARM® CORTEX™-M0 Document Kit for MCU core details.

1 Page = 512 Byte

1 ROW = 32 WORDS

1 WORD = 32Bits 031

1 WORD, ½ WORD and Byte AccessBOOT

0x00E00 progStart [0x07]

© 2016 Integrated Device Technology, Inc. 108 January 26, 2016 The entire RAM is always accessible by the ARM® processor, but there are restrictions for RAM access via the JTAG interface. From the perspective of the JTAG interface, the RAM is split into two sections with a boundary configurable via the RAMSPLIT bit field in the SYS_MEMINFO register (see Table 4.7). Figure 4.2 Example of RAMSPLIT Address Configuration SRAM 0x0063C 0x007FF 0x000000x00003 0x000040x00007 0x0063F 0x006380x0063B 0x007FF Program m ed RA M SPLIT address

4 Byte = 1 W ord

32 BIT TIMER

Z1_LINIRQEN Z1_LINSTAT Z1_SPISTAT Z1_SPICFG Peripherals ARM® CORTEX™-M0 CORE SBC Interrupt Controller SBC NVIC Interrupt Controller CORTEX™-M0 PROCESSOR TIMER MODULE (Counter Overflow) FC-IRQ-EN FC-STAT-CORE NMIECC PROG: Double Bit Error MCU CONTAINS IRQ EN BITS IRQN Note: The Systick has an NVIC number of -1 which is within the Cortex™-M0 core. For more details, refer to the ARM® CORTEX™-M0 Document Kit.

© 2016 Integrated Device Technology, Inc. 114 January 26, 2016 SPICFG SPISTAT SPICLKCFG INTERNAL DATA BUS SHIFTREG SPIDATA RxBUFTxBUF SPI CONTROL LOGIC SPICLK CSN MOSI MISO SBC SPI SLAVE MCUSBC IRQ FF OSCH SPICLK Where CDIV is the clock divider value bit field in the Z1_SPICLKCFG register. Note: For the SPI to operate within its valid speed range, the value programmed in CDIV must not be less than 2.

© 2016 Integrated Device Technology, Inc. 117 January 26, 2016 Data Unit (LIN UART) INTERNAL DATA BUS BreakSync Detector Inactivity Timer RX Sync & Filter CTRL SIGNAL SYNC;BANDRATE TIMEOUT CTRL SIGNAL IRQ LIN MCUSBC LIN RXD LIN TXD SBC LIN-PHY

© 2016 Integrated Device Technology, Inc. 118 January 26, 2016 HEADER RESPONSE RESPONSE SPACE BREAK FIELD SYNC FIELD PROTECTED IDENTIFIER FIELD INTER-BYTE SPACE DATA-1 DATA-2 DATA-N CHECKSUM INTER-BYTE SPACE INTERNAL DATA BUS LINIRQEN LINCFG LINSTATUS BAUDRATE SHIFTREG LINDATA RxBUF TxBUF LIN CONTROL LOGIC RXD TXD RXBIT TXBIT IRQ

© 2016 Integrated Device Technology, Inc. 121 January 26, 2016 RXD_I RXACTIVE_R TXEMPTY_R TXACTIVE_R TXD_O CLEARED BY DATA PRESENT IN TX BUFFER SET BY DATA PRESENT IN TX BUFFER CLEARED BY NO DATA PRESENT IN TX BUFFER END OF STOP BIT FROM RECEIVED PID TX-START

© 2016 Integrated Device Technology, Inc. 129 January 26, 2016 31 : 0 RELOADVAL R / W R 0 Timer-reload value; when the timer (counter) overflows, the reload value is copied into the counter register. In reload mode, the timer continues; however it stops if reload mode is not enabled.

© 2016 Integrated Device Technology, Inc. 142 January 26, 2016 5.2. MCU Activated Diagnostic Functions All hardware resources needed for these diagnostics are available in the SBC, but the procedures must be executed by the MCU. 5.2.1. Open-Load Detection Event There is an open in one or more drivers’ outputs. Detection A current source is connected to the output and the voltage drop over the load is observed. If the load is open , the voltage drop is zero. More information for this procedure is given in sections Capturing The event is captured as diag nostic status flag in SBC chip and can be read via the SPI . Reaction Should be implemented in MCU software depending on the application requirements . 5.2.2. Short to Vbat or GND Detection Event The driver output is shorted to V bat or GND. Detection Two current sources (sink and source) are connected to the output and the voltage drop over them is observed. If an event occurs, the poten tial will not be changed (zero in the event of a short to GND or Vbat in the event of a short to Vbat). More informat ion for this procedure is given Capturing The event is captured as a diagnostic status flag in the SBC and can be read via the SPI . Reaction A response should be implemented in MCU software depending on the application requirements . Note: The short to Vbat or GND diagnostic is possible only for the half -bridge drivers. For high -side drivers, only short to VBAT can be detected independently. Short to GND will cause an over-current event. 5.2.3. Floating Analog Input Det ection Event One of the analog inputs (AINx pins) is floating or shorted. Detection Current sink and source are connected to the pin and the voltage drop over them is monitored. Capturing The event is captured as a diagnostic status flag in the SBC and can be read via the SPI. Reaction A response should be implemented in the MCU software depending on application requirements.

© 2016 Integrated Device Technology, Inc. 146 January 26, 2016 HB1 HB2 HB3 HB4 HS4 M M M HS3 Turn signal Puddle lamp HS2 BSD lamp HS1 Heater EC_RES EC_M S_P S_N AIN1 AIN2 EC Mirror VDDE CAP_5V0 VSS1-5VSSD1-2VSSA AIN3/TEMP1 GPIO0 GPIO7 LIN GND Vbat CAP_CP VDDE1-8 VSS_LIN ext. temp CAP_3V3 CAP_1V8 CAP_MCU ZAMC4100 VSS_IO C1C3 C9 D2 AIN4/TEMP2

© 2016 Integrated Device Technology, Inc. 148 January 26, 2016 SBC MCU Off-chip bonding wiresExternal pin bonding wires Exposed pad Figure 7.2 Pin Layout for ZAMC4100 PQFN65 – Top View EXPOSED PAD (pin 65) VDDE1 n.c. VSS4 HB3 EC_RES EC_M VSS5 HS4 CAP_CP LIN VSS_LIN VSS_IO STO VSSD2 TEST TRSTNVDDE VSSD1 CAP_5V0 S_P AIN1 AIN2 S_N AIN4/TEMP2 VSSA AIN3/TEMP1 n.c. HB4 VSS1 n.c. n.c. VDDE8 TCK TMS TDO TDI GPIO0 GPIO1 GPIO2 GPIO3 GPIO4 GPIO5 GPIO6 GPIO7 n.c. CAP_3V3 CAP_1V8 HB2a VSS3 HB1b VDDE2 VDDE3 HS1a VDDE4 VDDE5 HS2 HS1b VDDE6 VDDE7 HB1a HS3 VSS2 HB2b CAP_MCU

© 2016 Integrated Device Technology, Inc. 149 January 26, 2016 Table 7.1 Pin Description Note: See important table notes at the end of the table. Pin Name Position Purpose Mode Description SUPPLY PINS VDDE 32 Supply Input Supply for the system VDDE1 64 Supply Input High current supply for the drivers VDDE2 4 VDDE3 5 VDDE4 7 VDDE5 8 VDDE6 11 VDDE7 12 VDDE8 17 VSS1 (1) 20 Supply Input High current ground for drivers VSS2 (1) 15 VSS3 (1) 2 VSS4 (1) 62 VSS5 (1) 58 VSS_LIN (1) 54 Supply Input Ground for LIN transceiver VSSA (1) 24 Supply Input Ground for analog blocks (low noise) VSSD1 (1) 31 Supply Input Ground for digital blocks of SBC VSSD2 (1) 51 Supply Input Ground for MCU VSS_IO (1) 53 Supply Input Ground for SBC digital IOs EXPOSED PAD (2) 65 Heat sink - Connected to digital ground CAP_5V0 (3) 30 Analog In/Out Connection to external capacitor for 5V (analog supply) CAP_3V3 (3) 34 Analog In/Out Connection to external capacitor for 3.3V (MCU peripheral supply) CAP_1V8 (3) 33 Analog In/Out Connection to external capacitor for 1.8V (SBC digital and MCU core supply) CAP_MCU (3) 35 Analog In/Out Connection to external capacitor for MCU 1V8 core voltage supply CAP_CP (3) 56 Analog In/Out Connection to external capacitor for the charge pump

© 2016 Integrated Device Technology, Inc. 150 January 26, 2016 Pin Name Position Purpose Mode Description SENSORS INTERFACE S_P 29 Analog Output Positive supply for sensors (5V) S_N (4) 26 Analog Output Negative supply for sensors (0V) AIN1 (5) 28 Analog Input General purpose ADC input AIN2 (5) 27 Analog Input General purpose ADC input AIN3/TEMP1 (5) 23 Analog In/Out General purpose ADC input/temperature sensor input AIN4/TEMP2 (5) 25 Analog In/Out General purpose ADC input/temperature sensor input ACTUATORS INTERFACE HB1a 13 Analog Output Output of half-bridge driver 1 HB1b 3 HB2a 1 Analog Output Output of half-bridge driver 2 HB2b 16 HB3 61 Analog Output Output of half-bridge driver 3 HB4 21 Analog Output Output of half-bridge driver 4 HS1a 6 Analog Output Output of high-side switch 1 HS1b 10 HS2 9 Analog Output Output of high-side switch 2 HS3 14 Analog Output Output of high-side switch 3 HS4 57 Analog Output Output of high-side switch 4 EC_M 59 Analog Output Output for EC mirror control EC_RES 60 Analog Input Connection to external resistor for EC COMMUNICATION INTERFACE LIN 55 Analog In/Out LIN bus GPIO0 (5) 44 Digital In/Out General purpose I/O pin GPIO1 (5) 43 Digital In/Out General purpose I/O pin GPIO2 (5) 42 Digital In/Out General purpose I/O pin GPIO3 (5) 41 Digital In/Out General purpose I/O pin GPIO4 (5) 40 Digital In/Out General purpose I/O pin GPIO5 (5) 39 Digital In/Out General purpose I/O pin GPIO6 (5) 38 Digital In/Out General purpose I/O pin GPIO7 (5) 37 Digital In/Out General purpose I/O pin

© 2016 Integrated Device Technology, Inc. 152 January 26, 2016 8 ZAMC4100 Outline Dimensions: Plastic QFN64 9x9mm (Package Type 1) Figure 8.1 ZAMC4100 Package Dimensions – Plastic QFN64 1732 48 6449 9.00 BSC SQR 5.90 6.00 6.10 SQR EXPOSED PAD BOTTOM VIEW NOTCH = PIN 1

0.5 BSC

0.30 0.40 0.50 0.18 0.23 0.30 0.24 0.42 0.60 0.24 0.42 0.60 0.80 0.85 0.90 0.60 0.65 0.70 0.05 MAX

0.2 REF

DRAWING NOT TO SCALE - ALL DIMENSIONS IN MILLIMETER

© 2016 Integrated Device Technology, Inc. 153 January 26, 2016 9 Ordering Information Product Sales Code Description Package ZAMC4100GA2R ZAMC4100GA PQFN64 – Temperature range: -40°C to +85°C 13” Tape and Reel ZAMC4100GA2V ZAMC4100GA PQFN64 – Temperature range: -40°C to +85°C Tray ZAMC4100 Evaluation Kit V2.0 including the ZAMC4100 Evaluation Board; software available at www.IDT.com/ZAMC4100 ZAMC4100 Application Kit V1.0 including the ZAMC4100 Application Board

10 Related Documents

Document ZAMC4100 Feature Sheet ZAMC4100 Evaluation Kit Description ZAMC4100 Application Kit Description Visit the ZAMC4100 product page at www.IDT.com/zamc4100 or contact your nearest sales office for the latest version of these documents. 11 Glossary Abbreviation Description ADC Analog-to-Digital Converter ARM® Advanced RISC Machine (RISC = Reduced Instruction Set Computing) Cortex™-M0 32-bit RISC processor core licensed by ARM CRC Cyclic Redundancy Check CS Current Source CSH Current Source High-Side CSL Current Source Low-Side CSN Chip Select (Negative) DAC Digital to Analog Converter DDM Driver Door Module ECC Error Correction Controller ECM Electrochromatic Mirror ECU Electronic Control Unit EEPROM Electrically Erasable Programmable Read-Only Memory FLASH Non-volatile memory that can be electrically erased and programmed. Usually where the program is stored.

© 2016 Integrated Device Technology, Inc. 154 January 26, 2016 Abbreviation Description FSR Full-Scale Range GND Ground potential of the application GPIO General Purpose Input Output interface IC Integrated Circuit IRQN Interrupt Request (Negative) JTAG Based on IEEE 1149.1 Standard Test Access Port and Boundary-Scan Architecture LIN Local Interconnect Network LIN PHY LIN Physical layer MCU Microcontroller Unit MOSI Master Out Slave In MISO Master In Slave Out MUX Multiplexer NMI Non-maskable Interrupt NMOS N-type MOSFET NVIC Nested Vector Interrupt Controller OC Over-Current OCH Over-Current for High-Side Driver OCL Over-Current for Low-Side Driver OSCH High frequency oscillator OSCL Low frequency oscillator OSI Open Systems Interconnection OV Over-Voltage OVL Over-Load OVT Over-Temperature PCB Printed Circuit Board POR Power-On-Reset PWM Pulse-Width Modulation RESCODE Result Code from ADC SAR Successive Approximation SBC System Basis Chip SPI Serial Peripheral Interface SIP System-in-Package SRAM Static RAM (RAM = Random Access Memory)

© 2016 Integrated Device Technology, Inc. 155 January 26, 2016 Abbreviation Description SW-LIN Software layer of the LIN protocol STBY Standby UART Universal Asynchronous Receiver Transmitter UV Under Voltage VBAT Battery supply WDT Watchdog Timer

12 Document Revision History

1.00 May 11, 2015 First release

January 25, 2016 Changed to IDT branding. Corporate Headquarters

6024 Silver Creek Valley Road

San Jose, CA 95138 www.IDT.com Sales 1-800-345-7015 or 408-284-8200 Fax: 408-284-2775 www.IDT.com/go/sales Tech Support www.IDT.com/go/support DISCLAIMER Integrated Device Technology, Inc. (IDT) reserves the right to modify the products and/or specifications described herein at any time, without notice, at IDT's sole discretion. Performance specifications and operating parameters of the described products are determined in an independent state and are not guarante ed to perform the same way when installed in customer products. The information contained herein is provide d without representation or warranty of any kind, whether express or implied, including, but not limited to, the suitability of IDT's products for any particular purpose, an implied warranty of merchantability, or non -infringement of the intellectual prope rty rights of others. This document is presented only as a guide and does not convey any license under intellectual property rights of IDT or any third parties. IDT's products are not intended for use in applications involving extreme environmental condit ions or in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT. Integrated Device Technology, IDT and the IDT logo are trademarks or registered trademarks of IDT and its subsidiaries in the United States and other countries. Other trademarks used herein are the property of IDT or their respective third party owners. For datasheet type definitions and a glossary of common terms, visit www.idt.com/go/glossary . All contents of this document are copyright of Integrated Device Techno logy, Inc. All rights reserved.

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Product Information

ZAMC4100 specifications and overview.

Summary

Actuator and Motor Controller January 26, 2016

Description

Actuator and Motor Controller January 26, 2016

Source title ZAMC4100 Datasheet(PDF) - Renesas Technology Corp

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