ZADCS1022

ZADCS1082 ZMD | Alldatasheet

Document overview

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Technical content

Features

• Single Supply Operation: + 2.7V … + 5.25V
• Family approach providing 2 / 4 / 8-Channel Single-Ended or 1 / 2 / 4-Channel Differential Inputs
• Up to 250ksps Conversion Rate
• ± 0.4 LSB INL and DNL
• No Missing Codes
• > 61 dB SINAD
• True fully differential Operation
• Software-Configurable Unipolar or Bipolar output coding
• Internal 3.3MHz oscillator for independent operation from external clock
• Internal 2.5V Reference
• Low Power - < 1.2mA (250ksps, 5V supply) - < 0.5μA (power-down mode)
• SPITM / QSPITM / MICROWIRETM - compatible 4-Wire Serial Interface
• 14 / 16 / 20-Pin SSOP

Applications

• Data Acquisition
• Industrial Process Control
• Portable Data Logging
• Battery-Powered Systems Functional Block Diagram

Description

The ZADCS10x2 family is a set of low power, 10-bit, suc- cessive approximation analog-to-digital (A/D) converters with up to 250ksps conversion rate, two up to eight input channels, high-bandwidth track/hold and synchronous serial interface. The ADCs operate from a single + 2.7V to + 5.25V supply. Their analog inputs are software configurable for unipo- lar/bipolar and single-ended/differential operation. The 4-wire serial interface connects directly to SPI™/ (QSPI™ and MICROWIRE™) devices without external logic. All family devices can use either the external serial- interface clock or an internal clock to perform successive- approximation analog-to-digital conversions. The internal clock can be used to run independent conversions on more than one device in parallel. The ZADCS10x2 V versions are equipped with a highly accurate internal 2.5V reference with an additional external ±1.5% voltage adjustment range. All members of the ZADCS10x2 family provide a hard- wired shut-down pin (nSHDN) pin and software-selectable power-down modes that can be programmed to automati- cally shut down the IC at the end of a conversion. Access- ing the serial interface automatically powers up the IC. A quick turn-on time allows the device to be shut down be- tween all conversions. 8-Channel Analog Input Multiplexer DAC with inherent T&H SAR Serial Interface and Control State Machine + 1.25V Reference Internal

3.3 MHz

x 2.000 Available in ZADCS10x2V versions IN+ IN- Available in ZADCS1042 Available in ZADCS1082 Available in ZADCS1022 Starterkit available

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. Table of Contents Page Important Notice: The information furnished herein by ZMD is believed to be correct and accurate as of the publication date. How- ever, ZMD shall not be liable to any party for any dam- ages, including but not limited to personal injury, property damage, loss of profits, loss of use, interruption of busi- ness, or indirect, special, incidental, or consequential damages of any kind in connection with or arising out of the furnishing, performance, or use of the technical data. No obligation or liability to any third party shall arise from ZMD's rendering technical or other services. Products sold by ZMD are covered exclusively by the ZMD’s standard warranty, patent indemnification, and other provisions appearing in ZMD’s standard "Terms & Conditions". ZMD makes no warranty (express, statutory, implied and/or by description), including without limitation any warranties of merchantability and/or fitness for a particular purpose, regarding the information set forth in the materials pertaining to ZMD products, or regarding the freedom of any products described in such materials from patent and/or other infringement. ZMD reserves the right to discontinue production and change specifications and prices, make corrections, modifications, enhancements, improvements and other changes of its products and services at any time without notice. ZMD products are intended for use in commercial applications. Applications requiring extended temperature range, unusual environmental requirements, or high reli- ability applications, such as military, medical life-support or life-sustaining equipment, are specifically not recom- mended without additional mutually agreed-upon proc- essing by ZMD for such applications. ZMD assumes no liability for application assistance or customer product design. Customers are responsible for their products and applications using ZMD components. SPI and QSPI are registered trademarks of Motorola, Inc. MICROWIRE is a registered trademark of National Semi- conductor Corp. Please notice, that values specified as typical may differ from product to product. The values listed under min or max are guaranteed by design or test.

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

1 General Device Specification

1.1 Absolute Maximum Ratings (Non Operating)

Table 1: Absolute Maximum Ratings Symbol Parameter Min Max Unit Note VDD-GND VDD to AGND, DGND -0.3 6 V VAGND-DGND AGND to DGND -0.3 0.3 V CH0 – CH7, COM to AGND, DGND -0.3 VDD+0.3 V VREF, VREFADJ to AGND -0.3 VDD+0.3 V Digital Inputs to DGND -0.3 6 V Digital Outputs to DGND -0.3 VDD+0.3 V Digital Output Sink Current 25 mA Iin Input current into any pin except supply pins (Latch-Up) -100 100 mA VHBM Electrostatic discharge – Human Body Model (HBM) 2000 V 1 qJCT Maximum Junction Temperature +150° °C Operating Temperature Range ZADCS10x2VIS20 / ZADCS10x2IS20 -25 +85 °C qOP ZADCS10x2VQS20 / ZADCS10x2QS20 -40 +125 °C qSTG Storage temperature -65 +150 °C qlead Lead Temperature 100%Sn JEDEC-J-STD-20C 260 °C H Humidity non-condensing 2 Ptot Total power dissipation 250 mW Thermal resistance of Package Rthj SSOP20 / 5.3mm 100 K/W 1 HBM: C = 100pF charged to V HBM with resistor R = 1.5kW in series, valid for all pins

2 Level 4 according to JEDEC-020A is guaranteed

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

1.2 Package Pin Assignment ZADCS1082 / ZADCS1082V

Table 2: Pin list Package pin number Name Direction Type Description 1 nCS IN CMOS Digital Active Low Chip Select

2 DIN IN CMOS Digital Serial Data Input

3 DGND SUPPLY Digital Ground

4 AGND SUPPLY Analog Ground

5 VREF I/O Analog Reference Buffer Output / External Reference Input

6 COM IN Analog Ground reference for analog inputs in single ended mode

7 CH0 IN Analog Analog Input Channel 0

8 CH1 IN Analog Analog Input Channel 1

9 CH4 IN Analog Analog Input Channel 4

10 CH5 IN Analog Analog Input Channel 5

11 CH7 IN Analog Analog Input Channel 7

12 CH6 IN Analog Analog Input Channel 6

13 CH3 IN Analog Analog Input Channel 3

14 CH2 IN Analog Analog Input Channel 2

15 REFADJ I/O Analog Input to Reference Buffer Amplifier

16 VDD SUPPLY Positive Supply

17 nSHDN IN CMOS Digital Active Low Shutdown

18 DOUT OUT CMOS Digital Serial Data Output

19 SSTRB OUT CMOS Digital Serial Strobe Output

20 SCLK IN CMOS Digital Serial Clock Input

REFADJ on ZADCS1082V, No connect on ZADCS1082 CH2 CH3 CH6 CH7 ZADCS 1082 / ZADCS 1082V Figure 1: Package Pin Assignment for ZADCS1082 & ZADCS1082V

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

1.3 Package Pin Assignment ZADCS1042 / ZADCS1042V

Table 3: Pin list Package pin number Name Direction Type Description 1 nCS IN CMOS Digital Active Low Chip Select

9 CH3 IN Analog Analog Input Channel 3

10 CH2 IN Analog Analog Input Channel 2

11 REFADJ I/O Analog Input to Reference Buffer Amplifier

12 VDD SUPPLY Positive Supply

13 nSHDN IN CMOS Digital Active Low Shutdown

14 DOUT OUT CMOS Digital Serial Data Output

15 SSTRB OUT CMOS Digital Serial Strobe Output

16 SCLK IN CMOS Digital Serial Clock Input

REFADJ on ZADCS1042V, No connect on ZADCS1042 CH2 CH3 ZADCS 1042 / ZADCS 1042V Figure 2: Package Pin Assignment for ZADCS1042 & ZADCS1042V

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

1.4 Package Pin Assignment ZADCS1022 / ZADCS1022V

Table 4: Pin list Package pin number Name Direction Type Description 1 nCS IN CMOS Digital Active Low Chip Select

9 REFADJ I/O Analog Input to Reference Buffer Amplifier

10 VDD SUPPLY Positive Supply

11 nSHDN IN CMOS Digital Active Low Shutdown

12 DOUT OUT CMOS Digital Serial Data Output

13 SSTRB OUT CMOS Digital Serial Strobe Output

14 SCLK IN CMOS Digital Serial Clock Input

REFADJ on ZADCS1022V, No connect on ZADCS1022 CH1 ZADCS 1022 ZADCS 1022V Figure 3: Package Pin Assignment for ZADCS1022 & ZADCS1022V

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

1.5 Electrical Characteristics

1.5.1 General Parameters

(VDD = +2.7V to + 5.25V; f SCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); V REF = 2.500V applied to VREF pin; qOP = qOPmin … qOPmax) Parameter Symbol Conditions Min Typ Max Unit DC Accuracy Resolution 10 Bits Relative Accuracy INL ZADCS1082 / ZADCS1082V ZADCS1042 / ZADCS1042V ZADCS1022 / ZADCS1022V ± 0.4 LSB No Missing Codes NMC 10 Bits Differential Nonlinearity DNL ZADCS1082 / ZADCS1082V ZADCS1042 / ZADCS1042V ZADCS1022 / ZADCS1022V ± 0.4 LSB Offset Error ± 0.5 ± 2.0 LSB Gain Error ± 0.5 ± 2.0 LSB Gain Temperature Coefficient ± 0.25 ppm/°C Dynamic Specifications (10kHz sine-wave input, 0V to 2.500Vpp, 250ksps, 3.3MHz external clock) Signal-to-Noise + Distortion Ratio SINAD 61 dB Total Harmonic Distortion THD Up to the 5th harmonic -72 dB Spurious-Free Dynamic Range SFDR 74 dB Small-Signal Bandwidth -3dB roll off 3.8 MHz Conversion Rate Sampling Time (= Track/Hold Acquisition Time) tACQ Ext. Clock = 3.3MHz, 2.5 clocks/ acquisi- tion 0.758 µs Ext. Clock = 3.3MHz, 10 clocks/ conver- sion 3.03 µs Conversion Time tCONV Int. Clock = 3.3MHz +/- 12% tolerance 2.75 3.50 µs Aperture Delay 30 ns Aperture Jitter < 50 ps External Clock Frequency 0.1 3.3 MHz Internal Clock Frequency 2.81 3.3 3.58 MHz Analog Inputs Unipolar, COM = 0V 0 to VREF Input Voltage Range, Single- Ended and Differential Bipolar, COM = VREF/2 ± VREF / 2 V Input Capacitance 16 pF

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

1.5.2 Specific Parameters of ZADCS10x2V versions (with Internal Reference)

(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); qOP = qOPmin … qOPmax) Parameter Symbol Conditions Min Typ Max Unit Internal Reference at VREF VREF Output Voltage TA = + 25°C 2.480 2.500 2.520 V VREF Short-Circuit Current 30 mA VREF Temperature Coefficient ± 30 ± 50 ppm/°C Load Regulation 0 to 0.2mA output load 0.35 mV Capacitive Bypass at VREF 4.7 µF Capacitive Bypass at REFADJ 0.047 µF REFADJ Adjustment Range ± 1.5 % External Reference at VREF (internal buffer disabled by V(REFADJ) = VDD) VREF Input Voltage Range 1.0 VDD + 50mV V VREF Input Current VREF = 2.5V 180 215 µA VREF Input Resistance 11.5 14 kW Shutdown VREF Input Current 0.1 µA REFADJ Buffer Disable Threshold VDD- 0.5 V External Reference at VREF_ADJ Reference Buffer Gain 2.00 VREF_ADJ Input Current ±80 µA Full Power Down VREFADJ Input Current Full Power-Down mode 0.1 µA Power Requirements Positive Supply Voltage VDD 2.7 5.25 V Operating Mode ext. VREF 0.85 1.0 mA Operating Mode int. VREF 1.3 1.4 mA Fast Power-Down 250 300 Positive Supply Current ZADCS1082VI ZADCS1042VI ZADCS1022VI IDD VDD=3.6V Full Power-Down 0.5 4.0 µA Operating Mode ext. VREF 1.00 1.3 mA Operating Mode int. VREF 1.40 1.6 mA Fast Power-Down 250 300 Positive Supply Current ZADCS1082VI ZADCS1042VI ZADCS1022VI IDD VDD=5.2V Full Power-Down 0.5 4.0 µA Operating Mode ext. VREF 0.85 1.11) mA Operating Mode int. VREF 1.3 1.51) mA Fast Power-Down 250 3501) Positive Supply Current ZADCS1082VQ ZADCS1042VQ ZADCS1022VQ IDD VDD=3.6V Full Power-Down 0.5 151) µA Operating Mode ext. VREF 1.00 1.41) mA Operating Mode int. VREF 1.40 1.71) mA Fast Power-Down 250 3501) Positive Supply Current ZADCS1082VQ ZADCS1042VQ ZADCS1022VQ IDD VDD=5.2V Full Power-Down 0.5 201) µA 1) relaxed maximum limits are due to wider temperature range of automotive qualified version ZADCS10x2VQ

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. Specific Parameters of basic ZADCS10x2 versions (without Internal Reference) (VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); qOP = qOPmin … qOPmax) Parameter Symbol Conditions Min Typ Max Unit External Reference at VREF VREF Input Voltage Range 1.0 VDD + 50mV V VREF Input Current VREF = 2.5V 180 215 µA VREF Input Resistance 11.5 14 kW Shutdown VREF Input Current 0.1 µA Capacitive Bypass at VREF 4.7 µF Power Requirements Positive Supply Voltage VDD 2.7 5.25 V Operating Mode 0.85 1.0 Positive Supply Current ZADCS1082I, ZADCS1042I, ZADCS1022I IDD VDD = 3.6V Full Power-Down 0.5 4.0 µA Operating Mode 1.00 1.3 Positive Supply Current ZADCS1082I, ZADCS1042I, ZADCS1022I IDD VDD = 5.25V Full Power-Down 0.5 4.0 µA Operating Mode 0.85 1.01) Positive Supply Current ZADCS1082Q, ZADCS1042Q, ZADCS1022Q IDD VDD = 3.6V Full Power-Down 0.5 151) µA Operating Mode 1.00 1.31) Positive Supply Current ZADCS1082Q, ZADCS1042Q, ZADCS1022Q IDD VDD = 5.25V Full Power-Down 0.5 201) µA 1) relaxed maximum limits are due to wider temperature range of automotive qualified version ZADCS10x2Q

1.5.3 Digital Pin Parameters

(VDD = +2.7V to + 5.25V; fSCLK = 3.3MHz (50% duty cycle); 13 clocks/conversion cycle (250 ksps); qOP = qOPmin … qOPmax) Parameter Symbol Conditions Min Typ Max Unit Digital Inputs (DIN, SCLK, CS, nSHDN) VDD = 2.7V 1.9 V Logic High Level VIH VDD = 5.25V 3.3 V VDD = 2.7V 0.7 V Logic Low Level VIL VDD = 5.25V 1.4 V Hysteresis VHyst 0.7 V Input Leakage IIN VIN = 0V or VDD ± 0.1 ± 1.0 µA Input Capacitance CIN 5 pF Digital Outptus (DOUT, SSTRB) VDD = 2.7V 3.5 8.5 mA Output High Current IOH VOH= VDD – 0.5V VDD = 5.25V 5.5 10.8 mA VDD = 2.7V 4 11.5 mA Output Low Voltage IOL VOL= 0.4V VDD = 5.25V 6.4 15.3 mA Three-State Leakage Current ILeak nCS = VDD ± 0.1 ± 1.0 µA Three-State Output Capacitance COUT nCS = VDD 5 pF

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

1.6 Typical Operating Characteristics

Integral Nonlinearity vs. Code -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1024 Code INL (LSB) Differential Nonlinearity vs. Code -0.8 -0.6 -0.4 -0.2 0.2 0.4 0.6 0.8 0 128 256 384 512 640 768 896 1024 Code DNL (LSB) IDD vs. VDD 150 300 450 600 750 900 1050 1200 1350 1500 VDD (V) IDD (µA) IDDstatic vs. Temperature ZADCS12x2V, internal reference active, at VDD = 3.3V 500 550 600 650 700 -40 -20 0 20 40 60 80 100 Temperatur (°C) IDD (µA) IDDactive (converting) vs. Temperature ZADCS12x2V, internal reference active, at VDD = 3.3V 900 950 1000 1050 -40 -20 0 20 40 60 80 100 Temperatur (°C) IDD (µA) VREF vs. Temperature 2.498 2.499 2.500 2.501 -25 0 25 50 75 Temperature (°C) Reference Voltage (v) IDDactive (converting) IDDstatic External VREF Internal V REF

Information furnished in this publication is preliminary and subject to changes without notice.

2 DETAILED DESCRIPTION

2.1 General Operation

converter with excellent monotonicity and DNL properties.

2.2 Analog Input

tial applications where both signals can vary over time. converters featuring pseudo differential operation only. Figure 7. Table 5 and Table 6 show the relationship of the code range of the converter.

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice. SW IN ACQ S RC7 t R -´£ For example, if f SCLK = 3.3MHz, the acquisition time is tACQ = 758ns. Thus the output impedance of the signal source RS must be less than 2.41kΩ kΩ320pF7 758ns RS =-´£ If the output impedance of the source is higher than the calculated maximum R S the acquisition time must be extended by reducing f SCLK to ensure 10 bit accuracy. Another option is to add a capacitor of >20 nF to the individual input. Although this limits the bandwidth of the input signal because an RC low pass filter is build to- gether with the source impedance, it may be useful for certain applications. The small-signal bandwidth of the input tracking circuitry is 3.8 MHz. Hence it is possible to digitize high-speed transient events and periodic signals with frequencies exceeding the ADC’s sampling rate. This allows the ap- plication of certain under-sampling techniques like down conversion of modulated high frequency signals. Be aware that under-sampling techniques still require a bandwidth limitation of the input signal to less than the Nyquist frequency of the converter to avoid aliasing ef- fects. Also, the output impedance of the input source must be very low to achieve the mentioned small signal bandwidth in the overall system.

2.3 Internal & External Reference

ZADCS10x2V family members are equipped with a highly accurate internal 2.5V reference voltage source. The voltage is generated from a trimmed 1.25V bandgap with an internal buffer that is set to a gain of 2.00. The band- gap voltage is supplied at VREFADJ with an output im- pedance of 20k Ω. An external capacitor of 47nF at VREFADJ is useful to further decrease noise on the in- ternal reference. The VREFADJ pin also provides an opportunity to exter- nally adjust the bandgap voltage in a limited range (see Figure 10) as well as the possibility to overdrive the inter- nal bandgap with an external 1.25V reference. The internal bandgap reference and the VREF buffer can be shut down completely by setting VREFADJ to VDD. This reduces power consumption of the ZADCS10x2 V devices and allows the supply of an external reference at VREF. Basic ZADCS10x2 devices do not contain the internal bandgap or the VREF buffer. An external reference must be supplied all the time at VREF. The value of the reference voltage at VREF sets the input range of the converter and the analog voltage weight of each digital code. The size of the LSB (least significant bit) is equal to the value of VREF (reference to AGND) divided by 1024. For example at a reference voltage of 2.500V, the voltage level of a LSB is equal to 2.441mV. It is important to know that certain inherent errors in the A/D converter, like offset or gain error, will appear to increase at lower reference voltages while the actual performance of the device does not change. For instance a static offset error of 2.441mV is equal to 1 LSB at 2.5V reference, while it is equivalent to 2.5 LSB for a reference voltage of 1.0V Likewise, the uncertainty of the digitized output code will increase with lower LSB size (lower VREF). Once the size of an LSB is below the internal noise level, the output code will start to vary around a mean value for constant DC input voltages. Such noise can be reduced by averag- ing consecutive conversions or applying a digital filter. The average current consumption at VREF depends on the value of VREF and the sampling frequency. Two effects contribute to the current at VREF, a resistive con- nection from VREF to AGND and charge currents that result from the switching and recharging of the capacitor array (CDAC) during sampling and conversion. For an external reference of 2.5V the input current at VREF is approximately 100µA.

2.4 Digital Interface

All devices out of the ZADCS10x2 family are controlled by a 4-wire serial interface that is compatible to SPI™, QSPI™ and MICROWIRE™ devices without external logic. Any conversion is started by sending a control byte into DIN while nCS is low. A typical sequence is shown in Figure 11. The control byte defines the input channel(s), unipolar or bipolar operation and output coding, single-ended or differential input configuration, external or internal con- version clock and the kind of power down that is activated after the completion of a conversion. A detailed descrip- tion of the control bits can be obtained from Table 7. As it can also be seen in Figure 11 the acquisition of the input signal occurs at the end of the control byte for 2.5 clock cycles. Outside this range, the Track & Hold is in hold mode. The conversion process is started, with the falling clock edge (SCLK) of the eighth bit in the control byte. It takes twelve clock cycles to complete the conversion and one additional cycle to shift out the last bit of the conversion result. During the remaining five clock cycles the output is filled with zeros in 24-Clock Conversion Mode. Depending on what clock mode was selected, either the external SPI clock or an internal clock is used to drive the successive approximation. Figure 12 shows the Timing for Internal Clock Mode. VREFADJ ZADCS10x2V 510kΩ VDD = +2.7V … +5.25V Figure 10: Reference Adjust Circuit 47nF

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

2.5 Power Dissipation

The ZADCS10x2 family offers three different ways to save operating current between conversions. Two differ- ent software controlled power down modes can be acti- vated to automatically shut-down the device after comple- tion of a conversion. They differ in the amount of circuitry that is powered down. Software Power Down Full Power Down Mode shuts down the entire analog part of the IC, reducing the static IDD of the device to less than 0.5µA if no external clock is provided at SCLK. Fast Power Down mode is only useful with ZADCS10x2V devices if the internal voltage reference is used. During Fast Power-Down the bandgap and the VREFADJ output buffer are kept alive while all other internal analog cir- cuitry is shut down. The benefit of Fast Power Down mode is a shorter turn on time of the reference compared to Full Power-Down Mode. This is basically due to the fact that the low pass which is formed at the VREFADJ output by the internal 20k Ω resistor and the external buffer capacitor of 47nF is not discharged in Fast Power- Down Mode. The settling time of the low pass at VREFADJ is about 7 ms to reach 10 bit accuracy. The Fast Power Down mode omits this settling and reduces the turn on time to about 200µs. To wake up the IC out of either software power down mode, it is sufficient to send a Start Bit while nCS is LOW. Since micro controllers can commonly transfer full bytes per transaction only, a dummy conversion is usually carried out to wake the device. In all application cases where an external reference volt- age is supplied (basic ZADCS10x2 and ZADCS10x2 V with VREFADJ tied to VDD) there is no turn on time to be considered. The first conversion is already valid. Fast Power-Down and Full Power-Down Mode do not show any difference in this configuration. Hardware Power Down The third power down mode is called Hardware Power- Down. It is initiated by pulling the nSHDN pin LOW. If this condition is true, the device will immediately shut down all circuitry just as in Full Power Down-Mode. The IC wakes up if nSHDN is tied HIGH. There is no internal pull-up that would allow nSHDN to float during normal operation. This ensures the lowest possible power consumption in power down mode. General Power Considerations Even without activating any power down mode, the de- vices out of the ZADCS10x2 family reduce their power consumption between conversions automatically. The comparator, which contributes a considerable amount to the overall current consumption of the device, is shut off as soon as a conversion is ended. It gets turned on at the start of the next acquisition period. This explains the difference between the IDDstatic and IDDactive meas- urements shown in chapter 1.6 Typical Operating Char- acteristics. The average current consumption of the device depends very much on the sampling frequency and the type of protocol used to communicate with the device. In order to achieve the lowest power consumption at low sampling frequencies, it is suggested to keep the conver- sion clock frequency at the maximum level of 3.3MHz and to power down the device between consecutive conver- sions. Figure 18 shows the characteristic current con- sumption of the ZADCS10x2 family with external refer- ence supply versus Sampling Rate

3 Layout

To achieve optimum conversion performance care must be taken in design and layout of the application board. It is highly recommended to use printed circuit boards in- stead of wire wrap designs and to establish a single point 01 … 111 01 … 110 10 … 000 10 … 001 00 … 000 +FS -FS Input Voltage (LSB) +FS-3/2 LSB ZS = V(IN-) + FS = ½VREF +V(IN-) 1LSB = VREF 1024 Output Code 00 … 001 00 … 011 11 … 111 11 … 110 11 … 101 ZS - FS = -½VREF +V(IN-) Figure 17: Bipolar Transfer Function Figure 16: Unipolar Transfer Function 11 … 111 11 … 110 11 … 1 01 00 … 000 00 … 001 00 … 010 1 2 3 FS 0 Input Voltage (LSB) FS-3/2 LSB ZS = V(IN-) FS = VREF +V(IN-) 1LSB = VREF 1024 (ZS) Output Code

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

4 Package Drawing

ZADCS1082 devices are delivered in a 20-pin SSOP-package that has the dimensions as shown in Figure 20 and Table 9. ZADCS1042 and ZADCS1022 devices apply respective 16-pin and 14-pin SSOP-packages. Their dimensions are specified in Table 10 and Table 11. Table 9: Package Dimensions for ZADC1082 devices (mm) Symbol A A1 A2 bP c D E enom HE LP Z k Q 0.65 7.65 0.63 0.25 0° Table 10: Package Dimensions for ZADC1042 devices (mm) Symbol A A1 A2 bP c D E enom HE LP Z k Q 0.65 7.65 0.63 0.25 0° Table 11: Package Dimensions for ZADC1022 devices (mm) Symbol A A1 A2 bP c D E enom HE LP Z k Q 0.65 7.65 0.63 0.25 0° Figure 20: Package Outline Dimensions

ZADCS1082/1042/1022 Family Copyright © 2008, ZMD AG, Rev. 1.1 All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without the prior written consent of the copyright owner. The Information furnished in this publication is preliminary and subject to changes without notice.

5 Ordering Information

[Bit] Channels [number] Sample Rate [ksps] Temperature range [°C] QC 100 Qualified Internal Vref INL DNL Pins [number] Package [Type] packing ZADCS1082VIS20T 10 8 250 -25°C to +85°C -- ü ± 0,4 LSB ± 0,4 LSB 20 SSOPTube ZADCS1082IS20T 10 8 250 -25°C to +85°C -- -- ± 0,4 LSB ± 0,4 LSB 20 SSOPTube ZADCS1042VIS16T 10 4 250 -25°C to +85°C -- ü ± 0,4 LSB ± 0,4 LSB 16 SSOPTube ZADCS1042IS16T 10 4 250 -25°C to +85°C -- -- ± 0,4 LSB ± 0,4 LSB 16 SSOPTube ZADCS1022VIS14T 10 2 250 -25°C to +85°C -- ü ± 0,4 LSB ± 0,4 LSB 14 SSOPTube ZADCS1022IS14T 10 2 250 -25°C to +85°C -- -- ± 0,4 LSB ± 0,4 LSB 14 SSOPTube ZADCS1082VQS20T 10 8 250 -40°C to +125°C üü ± 0,4 LSB ± 0,4 LSB 20 SSOPTube ZADCS1082QS20T 10 8 250 -40°C to +125°C ü -- ± 0,4 LSB ± 0,4 LSB 20 SSOPTube ZADCS1042VQS16T 10 4 250 -40°C to +125°C üü ± 0,4 LSB ± 0,4 LSB 16 SSOPTube ZADCS1042QS16T 10 4 250 -40°C to +125°C ü -- ± 0,4 LSB ± 0,4 LSB 16 SSOPTube ZADCS1022VQS14T 10 2 250 -40°C to +125°C üü ± 0,4 LSB ± 0,4 LSB 14 SSOPTube ZADCS1022QS14T 10 2 250 -40°C to +125°C ü -- ± 0,4 LSB ± 0,4 LSB 14 SSOPTube

6 ZMD Distribution Partner

ZMD ADC products as well as the ZADCS1282 Starterkit can be purchased from RUTRONIK Elektronische Bauelemente GmbH. RUTRONIK Elektronische Bauelemente GmbH Industriestrasse 2

78228 Ispringen, Germany

Phone: +49 7231 801-0 Fax: +49 7231 82282 E-mail: rutronik@rutronik.com Internet: www.rutronik.com

7 ZMD Contact

ZMD AG, Headquarters Grenzstraße 28 D-01109 Dresden Phone: +49 351 88227 -ADC (-232) Fax: +49 351 882278 -ADC (-232) E-mail: SARah@zmd.de Internet: www.zmd.biz/ADC ZMD America Inc., New York

201 Old Country Road, Suite 204

Melville, NY 11747 Phone.: +1 631 549 2666 Fax: +1 631 549 2882 ZMD Far East, Hsinchu City 1F, No14, Lane 268 Sec. 1 Guangfu Rd. Hsinchu City 300, Taiwan Phone: +886 03 563 1388 Fax: +886 03 563 6385 ZMD AG, Tokyo 212-0061 7-6-10-103 Hanahata, Adachi Tokyo, Japan Phone: +81 3 6805 0669 Fax: +81 2 6805 0669 For the most current revision of this document and for additional product information please visit www.zmd.biz/ADC.